Texas Instruments DAC 3202 Series User manual

DACx3202 12-Bit and 10-Bit, Dual, Voltage and Current Output Smart DACs With
Auto-Detected I2C, PMBus™, or SPI Interface
1 Features
• Programmable voltage or current outputs with
flexible configuration:
– Voltage outputs:
• 1 LSB INL and DNL (10-bit and 8-bit)
• Gains of 1x, 1.5x, 2x, 3x, and 4x
– Current outputs:
• 1 LSB INL and DNL (8-bit)
• ±25 μA, ±50 μA, ±125 μA, ±250 μA output
range options
• Programmable comparator mode for all channels
• High-impedance output when VDD is off
• High-impedance and resistive pulldown power-
down modes
• 50-MHz SPI-compatible interface
• Automatically detected I2C, PMBus™, or SPI
interface
– 1.62-V VIH with VDD = 5.5 V
• General-purpose input/output (GPIO) configurable
as multiple functions
• Predefined waveform generation: sine, cosine,
triangular, sawtooth
• User-programmable nonvolatile memory (NVM)
• Internal, external, or power-supply as reference
• Wide operating range:
– Power supply: 1.8 V to 5.5 V
– Temperature: –40˚C to +125˚C
• Tiny package: 16-pin WQFN (3 mm × 3 mm)
2 Applications
•Rack server
•Optical module
•Inter-DC interconnect (metro)
•High performance computing
•Standard notebook PC
3 Description
The 12-bit DAC63202 and 10-bit DAC53202
(DACx3202) are a pin-compatible family of dual-
channel, buffered, voltage-output and current-output
smart digital-to-analog converters (DACs). The
DACx3202 devices support Hi-Z power-down mode
and Hi-Z output during power-off conditions. The
DAC outputs provide a force-sense option for
use as a programmable comparator and current
sink. The multifunction GPIO, function generation,
and NVM enable these smart DACs for processor-
less applications and design reuse. These devices
automatically detect I2C, PMBus, and SPI interfaces
and contain an internal reference.
The feature set combined with the tiny package and
low power make these smart DACs an excellent
choice for applications such as voltage margining and
scaling, dc set-point for biasing and calibration, and
waveform generation.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
DACx3202 WQFN (16) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SMPS / LDO R1
R2
VFB
SENSE
PH
GND
VOUT
IN
BOOT
CL
CB
L
DACx3202
VDD
VIN
VOUT/
IOUT
VOUT/
IOUT
DAC
REG
DAC
BUF
DAC
REG
DAC
BUF
NVM
Internal
Reference
LDO
Output Configuration
Logic
VREF CAP
AGND
Digital Interface
SCL/SYNC
SDA/SCLK
A0/SDI
PROTECT
R3
R3
1.5 μ
F
0.1 μ

10 kΩ
Power-supply: 0
Power-supply: 1
Voltage Margining and Scaling Using the DACx3202
DAC53202, DAC63202
SLASF47 – MAY 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: Voltage Output...................5
6.6 Electrical Characteristics: Current Output...................7
6.7 Electrical Characteristics: Comparator Mode..............8
6.8 Electrical Characteristics: General..............................9
6.9 Timing Requirements: I2C Standard Mode............... 10
6.10 Timing Requirements: I2C Fast Mode.....................10
6.11 Timing Requirements: I2C Fast Mode Plus............. 10
6.12 Timing Requirements: SPI Write Operation............ 11
6.13 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 0).......................................11
6.14 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 1).......................................11
6.15 Timing Requirements: GPIO...................................12
6.16 Timing Diagrams.....................................................12
6.17 Typical Characteristics: Voltage Output.................. 14
6.18 Typical Characteristics: Current Output.................. 19
6.19 Typical Characteristics: Comparator.......................23
6.20 Typical Characteristics: General............................. 24
7 Detailed Description......................................................25
7.1 Overview...................................................................25
7.2 Functional Block Diagram.........................................25
7.3 Feature Description...................................................26
7.4 Device Functional Modes..........................................27
7.5 Programming............................................................ 44
7.6 Register Map.............................................................52
8 Application and Implementation..................................70
8.1 Application Information............................................. 70
8.2 Typical Application.................................................... 70
9 Power Supply Recommendations................................73
10 Layout...........................................................................73
10.1 Layout Guidelines................................................... 73
10.2 Layout Example...................................................... 73
11 Device and Documentation Support..........................74
11.1 Documentation Support.......................................... 74
11.2 Receiving Notification of Documentation Updates..74
11.3 Support Resources................................................. 74
11.4 Trademarks............................................................. 74
11.5 Electrostatic Discharge Caution..............................74
11.6 Glossary.................................................................. 74
12 Mechanical, Packaging, and Orderable
Information.................................................................... 74
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
May 2022 * Initial Release
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5 Pin Configuration and Functions
16 VREF5GPIO/SDO
1FB0 12 FB1
15 VDD6SCL/SYNC
2OUT0 11 OUT1
14 AGND7A0/SDI
3NC 10 NC
13 CAP8SDA/SCLK
4NC 9 NC
Not to scale
Thermal Pad
Figure 5-1. RTE (16-pin WQFN) Package, Top View
Table 5-1. Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 FB0 Input
Voltage feedback pin for channel 0.
In voltage-output mode, connect to OUT0 for closed-loop amplifier output.
In current-output mode, keep the FB0 pin unconnected to minimize leakage current.
2 OUT0 Output Analog output voltage from DAC channel 0.
3 NC NC No connection. Leave the pin unconnected.
4 NC NC No connection. Leave the pin unconnected.
5 GPIO/SDO Input/Output
General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS.
For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor.
If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD.
6 SCL/SYNC Output I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using an external
pullup resistor. This pin can ramp up before VDD.
7 A0/SDI Input
Address configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 7.5.2.2.1).
For SDI, this pin does not need to be pulled up or pulled down. This pin can ramp up before VDD.
8 SDA/SCLK Input/Output Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external
pullup resistor in I2C mode. This pin can ramp up before VDD.
9 NC NC No connection. Leave the pin unconnected.
10 NC NC No connection. Leave the pin unconnected.
11 OUT1 Output Analog output voltage from DAC channel 1.
12 FB1 Input
Voltage feedback pin for channel 1.
In voltage-output mode, connect to OUT1 for closed-loop amplifier output.
In current-output mode, keep the FB1 pin unconnected to minimize leakage current.
13 CAP Power External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.
14 AGND Ground Ground reference point for all circuitry on the device.
15 VDD Power Supply voltage.
16 VREF Power
External reference input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND.
Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In case
an external reference is used, make sure the reference ramps up after VDD.
Thermal
pad Thermal Pad Ground Connect the thermal pad to AGND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage, VDD to AGND –0.3 6 V
Digital inputs to AGND –0.3 VDD + 0.3 V
CAP to AGND –0.3 1.65 V
VFBX to AGND –0.3 VDD + 0.3 V
VOUTX to AGND –0.3 VDD + 0.3 V
VREF External reference, VREF to AGND –0.3 VDD + 0.3 V
Current into any pin except the OUTx pins –10 10 mA
TJJunction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Positive supply voltage to ground (AGND) 1.7 5.5 V
VREF External reference to ground (AGND) 1.7 VDD V
VIH Digital input high voltage, 1.7 V < VDD ≤ 5.5 V 1.62 V
VIL Digital input low voltage 0.4 V
CCAP External capacitor on CAP pin 0.5 15 μF
TAAmbient temperature –40 125 °C
6.4 Thermal Information
THERMAL METRIC(1)
DACx3202
UNITRTE (WQFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 49 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50 °C/W
RθJB Junction-to-board thermal resistance 24.1 °C/W
ΨJT Junction-to-top characterization parameter 1.1 °C/W
ΨJB Junction-to-board characterization parameter 24.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.7 °C/W
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics: Voltage Output
at 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL =
5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all minimum and maximum
specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC63202 12 Bits
DAC53202 10
INL Integral nonlinearity(1) DAC63202 –4 4 LSB
DAC53202 –1 1
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error(4)
Code 0d into DAC, external reference, VDD = 5.5 V 6 12
mV
Code 0d into DAC, internal VREF, gain = 4x,
VDD = 5.5 V 6 15
Zero-code error temperature
coefficient(4) Code 0d into DAC ±10 µV/°C
Offset error(4) (6)
1.7 V ≤ VDD < 2.7 V, FBx pin shorted to OUTx, DAC
code: 32d for 12-bit resolution, 8d for 10-bit resolution –0.75 0.3 0.75
%FSR
2.7 V ≤ VDD ≤ 5.5 V, FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit
resolution
–0.5 0.25 0.5
Offset-error temperature
coefficient(4) FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution ±0.0003 %FSR/°C
Gain error(4) Between end-point codes: 32d to 4064d for 12-bit
resolution, 8d to 1016d for 10-bit resolution –0.5 0.25 0.5 %FSR
Gain-error temperature
coefficient(4) Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution ±0.0008 %FSR/°C
Full-scale error(4) (6) 1.7 V ≤ VDD < 2.7 V, DAC at full-scale –1 1 %FSR
2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale –0.5 0.5
Full-scale-error temperature
coefficient(4) DAC at full-scale ±0.0008 %FSR/°C
OUTPUT
Output voltage Reference tied to VDD 0 VDD V
CLCapacitive load(2) RL = infinite, phase margin = 30° 200 pF
Phase margin = 30° 1000
Short-circuit current
VDD = 1.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 15
mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 50
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 60
Output-voltage headroom(2)
To VDD (DAC output unloaded, internal reference =
1.21 V), VDD ≥ 1.21 V ☓ gain + 0.2 V 0.2 V
To VDD and AGND (DAC output unloaded, external
reference at VDD, gain = 1x, the VREF pin is not
shorted to VDD)
0.8
%FSR
To VDD and AGND (ILOAD = 10 mA at VDD = 5.5 V, ILOAD
= 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V),
external reference at VDD, gain = 1x, the VREF pin is
not shorted to VDD
10
ZOVFB dc output impedance(3)
DAC output enabled, internal reference (gain = 1.5x or
2x) or external reference at VDD (gain = 1x), the VREF
pin is not shorted to VDD
400 500 600 kΩ
DAC output enabled, internal VREF, gain = 3x or 4x 325 400 485
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6.5 Electrical Characteristics: Voltage Output (continued)
at 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL =
5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all minimum and maximum
specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power supply rejection ratio
(dc)
Internal VREF, gain = 2x, DAC at midscale,
VDD = 5 V ±10% 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V 20
µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4x 25
Slew rate VDD = 5.5 V 0.3 V/µs
Power-on glitch magnitude At startup (DAC output disabled) 75 mV
At startup (DAC output disabled), RL = 100 kΩ 200
Output-enable glitch
magnitude
DAC output disabled to enabled (DAC registers at zero
scale), RL = 100 kΩ 250 mV
VnOutput noise voltage (peak to
peak)
f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 50
µVPP
Internal VREF, gain = 4x, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V 90
Output noise density
f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.35
µV/√Hz
Internal VREF, gain = 4x, f = 1 kHz, DAC at midscale,
VDD = 5.5 V 0.9
Power supply rejection ratio
(ac)(3)
Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power supply voltage, DAC at
midscale
-68 dB
Code change glitch impulse ±1-LSB change around midscale (including
feedthrough) 10 nV-s
Code change glitch impulse
magnitude
±1-LSB change around midscale (including
feedthrough) 15 mV
POWER
IDD Current flowing into VDD(4) (5) Normal operation, DACs at full scale, digital pins static, external reference at VDD but the VREF pin is not
shorted to VDD
150 µA/ch
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point
codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4) Measured with DAC output unloaded.
(5) The total power consumption is calculated by IDD x (total number of channels powered on) + (sleep-mode current).
(6) When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show
parametric drift.
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6.6 Electrical Characteristics: Current Output
at 1.7 V ≤ VDD ≤ 5.5 V, ±250-µA output range, digital inputs at VDD or AGND, and all minimum and maximum specifications
at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 8 Bits
INL Integral nonlinearity DAC codes between 0d and 255d –1 1 LSB
DNL Differential nonlinearity DAC codes between 0d and 255d –1 1 LSB
Offset error DAC at midscale ±1 %FSR
Gain error DAC codes between 0d and 255d ±1.3 %FSR
OUTPUT
Output compliance voltage(1) To VDD and AGND 400 mV
ZOIOUT dc output impedance(2) DAC at midscale, DAC output kept at VDD/2 60 MΩ
Power supply rejection ratio
(dc)
DAC at midscale, all bipolar ranges, VDD changed from
4.5 V to 5.5 V 0.23 LSB/V
DYNAMIC PERFORMANCE
tsett Output current settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB
at 8-bit resolution, VDD = 5.5 V, common-mode voltage
at OUTx pin is VDD/2
60 µs
VnOutput noise current (peak to
peak)
0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range 150 nAPP
Output noise density f = 1 kHz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range 1 nA/√Hz
Power supply rejection ratio
(ac)(3)
±250-µA output range, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power-supply voltage, DAC at
midscale
0.65 LSB/V
POWER
IDD Current flowing into VDD(3) (4)
Normal operation, DACs at full scale, ±25-µA output
range, digital pins static 42 50
µA/ch
Normal operation, DACs at full scale, ±50-µA output
range, digital pins static 56 70
Normal operation, DACs at full scale, ±125-µA output
range, digital pins static 98 120
Normal operation, DACs at full scale, ±250-µA output
range, digital pins static 167 200
(1) Measured between DAC codes 0d and 255d.
(2) Specified by design and characterization, not production tested.
(3) The current flowing into VDD does not account for the load current sourced or sinked on the OUTx pins. The VREF pin is connected to
VDD.
(4) The total power consumption is calculated by IDD x (total number of channels powered on) + (sleep-mode current).
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6.7 Electrical Characteristics: Comparator Mode
at 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x in voltage output mode, DAC output pin (OUT) loaded with
resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all
minimum and maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Offset error(1) (2) 1.7 V ≤ VDD ≤ 5.5 V, DAC at midscale, comparator input at Hi-Z, and DAC operating with external
reference
–5 0 5 mV
Offset error time drift(1)
VDD = 5.5 V, external reference, TA = 125°C, FBx in
Hi-Z mode, DAC at full scale and VFB at 0 V or DAC
at zero scale and VFB at 1.84 V, drift specified for 10
years of continuous operation
4 mV
OUTPUT
Input voltage
VREF connected to VDD, FBx resistor network
connected to ground 0 VDD
V
VREF connected to VDD, FBx resistor network
disconnected from ground 0 VDD (1/3 – 1/100)
VOL Logic low output voltage ILOAD = 100 μA, output in open-drain mode 0.1 V
DYNAMIC PERFORMANCE
tresp Output response time
DAC at midscale with 10-bit resolution, FBx input at
Hi-Z, and transition step at FBx node is
(VDAC – 2 LSB) to (VDAC + 2 LSB), transition time
measured between 10% and 90% of output, output
current of 100 µA, comparator output configured in
push-pull mode, load capacitor at DAC output is
25 pF
10 µs
(1) Specified by design and characterization, not production tested.
(2) This specification does not include the total unadjusted error (TUE) of the DAC.
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6.8 Electrical Characteristics: General
at 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x in voltage output mode or ±250-µA output range in current
output mode, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) in voltage-output mode and capacitive
load (CL = 200 pF to AGND), digital inputs at VDD or AGND, and all minimum and maximum specifications at
–40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL REFERENCE
Initial accuracy TA = 25°C 1.1979 1.212 1.224 V
Reference output temperature
coefficient(1) (2) 50 ppm/°C
EXTERNAL REFERENCE
VREF input impedance(1) (3) 192 kΩ/ch
EEPROM
Endurance(1) –40°C ≤ TA ≤ +85°C 20000 Cycles
TA = 125°C 1000
Data retention(1) TA = 25°C 50 Years
EEPROM programming write
cycle time(1) 200 ms
Device boot-up time(1) Time taken from power valid (VDD ≥ 1.7 V) to output valid state (output state as programmed in EEPROM),
0.5-µF capacitor on the CAP pin
5 ms
DIGITAL INPUTS
Digital feedthrough Voltage output mode, DAC output static at midscale,
fast mode plus, SCL toggling 20 nV-s
Pin capacitance Per pin 10 pF
POWER-DOWN MODE
IDD Current flowing into VDD(1)
DAC in sleep mode, internal reference powered down,
external reference at 5.5 V 28
µA
DAC in sleep mode, internal reference
enabled, additional current through internal reference 10
DAC channels enabled, internal reference enabled,
additional current through internal reference per DAC
channel in voltage-output mode
12.5
HIGH-IMPEDANCE OUTPUT
ILEAK Current flowing into VOUTX and
VFBX
DAC in Hi-Z output mode, 1.7 V ≤ VDD ≤ 5.5 V 10
nA
VDD = 0 V, VOUT ≤ 1.5 V, decoupling capacitor between
VDD and AGND = 0.1 μF 200
VDD = 0 V, 1.5 V < VOUT ≤ 5.5 V, decoupling capacitor
between VDD and AGND = 0.1 μF 500
100 kΩ between VDD and AGND, VOUT ≤ 1.25 V, series
resistance of 10 kΩ at OUTx pin ±2 µA
(1) Specified by design and characterization, not production tested.
(2) Measured at –40°C and +125°C and calculated the slope.
(3) Impedances for the DAC channels are connected in parallel.
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6.9 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V
MIN NOM MAX UNIT
fSCLK SCL frequency 100 kHz
tBUF Bus free time between stop and start conditions 4.7 µs
tHDSTA Hold time after repeated start 4 µs
tSUSTA Repeated start setup time 4.7 µs
tSUSTO Stop condition setup time 4 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 250 ns
tLOW SCL clock low period 4700 ns
tHIGH SCL clock high period 4000 ns
tFClock and data fall time 300 ns
tRClock and data rise time 1000 ns
tVD_DAT Data valid time 3.45 µs
tVD_ACK Data valid acknowledge time 3.45 µs
6.10 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V
MIN NOM MAX UNIT
fSCLK SCL frequency 400 kHz
tBUF Bus free time between stop and start conditions 1.3 µs
tHDSTA Hold time after repeated start 0.6 µs
tSUSTA Repeated start setup time 0.6 µs
tSUSTO Stop condition setup time 0.6 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 100 ns
tLOW SCL clock low period 1300 ns
tHIGH SCL clock high period 600 ns
tFClock and data fall time 300 ns
tRClock and data rise time 300 ns
tVD_DAT Data valid time 0.9 µs
tVD_ACK Data valid acknowledge time 0.9 µs
6.11 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V
MIN NOM MAX UNIT
fSCLK SCL frequency 1 MHz
tBUF Bus free time between stop and start conditions 0.5 µs
tHDSTA Hold time after repeated start 0.26 µs
tSUSTA Repeated start setup time 0.26 µs
tSUSTO Stop condition setup time 0.26 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 50 ns
tLOW SCL clock low period 0.5 µs
tHIGH SCL clock high period 0.26 µs
tFClock and data fall time 120 ns
tRClock and data rise time 120 ns
tVD_DAT Data valid time 0.45 µs
tVD_ACK Data valid acknowledge time 0.45 µs
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6.12 Timing Requirements: SPI Write Operation
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, and –40°C ≤ TA ≤ +125°C
MIN NOM MAX UNIT
f(SCLK) Serial clock frequency 50 MHz
tSCLKHIGH SCLK high time 9 ns
tSCLKLOW SCLK low time 9 ns
tSDIS SDI setup time 8 ns
tSDIH SDI hold time 8 ns
tCSS CS to SCLK falling edge setup time 18 ns
tCSH SCLK falling edge to CS rising edge 10 ns
tCSHIGH CS hight time 50 ns
tDACWAIT Sequential DAC update wait time for same channel 2 µs
tBCASTWAIT Broadcast DAC update wait time 2 µs
6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and FSDO = 0
MIN NOM MAX UNIT
f(SCLK) Serial clock frequency 1.25 MHz
tSCLKHIGH SCLK high time 350 ns
tSCLKLOW SCLK low time 350 ns
tSDIS SDI setup time 8 ns
tSDIH SDI hold time 8 ns
tCSS SYNC to SCLK falling edge setup time 400 ns
tCSH SCLK falling edge to SYNC rising edge 400 ns
tCSHIGH SYNC hight time 1 µs
tSDODLY SCLK rising edge to SDO falling edge, IOL ≤ 5 mA, CL = 20 pF. 300 ns
6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and FSDO = 1
MIN NOM MAX UNIT
f(SCLK) Serial clock frequency 2.5 MHz
tSCLKHIGH SCLK high time 175 ns
tSCLKLOW SCLK low time 175 ns
tSDIS SDI setup time 8 ns
tSDIH SDI hold time 8 ns
tCSS SYNC to SCLK falling edge setup time 300 ns
tCSH SCLK falling edge to SYNC rising edge 300 ns
tCSHIGH SYNC hight time 1 µs
tSDODLY SCLK rising edge to SDO falling edge, IOL ≤ 5 mA, CL = 20 pF. 300 ns
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6.15 Timing Requirements: GPIO
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, and –40°C ≤ TA ≤ +125°C
MIN NOM MAX UNIT
tGPIHIGH GPI high time(1) 2 µs
tGPILOW GPI low time(1) 2 µs
tGPAWGD LDAC falling edge to DAC update delay(2) 2 µs
tCS2LDAC SYNC rising edge to LDAC falling edge 1 µs
tSTP2LDAC I2C stop bit rising edge to LDAC falling edge 1 µs
tLDACW LDAC low time 2 µs
(1) The SCL, SDA, A0, and A1 pins can be configured as GPIOs that perform different channel-specific or independent operations. The
actual response time of the GPIO is determined by the delay provided by the configured function and the settling time of the DAC.
(2) The GPIOs can be configured as channel-specific or global LDAC function.
6.16 Timing Diagrams
SCL
SDA
PS
tBUF
tHDSTA
tLOW tR
tHDDAT
tHIGH
tF
tSUDAT
tSUSTA
tHDSTA
S
tSUSTO
P
Low byte ACK cycle
Figure 6-1. I2C Timing Diagram
tCSS
tSDIS tSDIH
SYNC
SDI
tCSHIGH
Bit 23
tSCLKLOW
Bit 1 Bit 0
tCSH
SCLK tSCLKHIGH
tCS2LDAC tLDACW
GPIO/
LDAC
Figure 6-2. SPI Write Timing Diagram
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Bit 22 Bit 0
tCSH
Bit 23 Bit 1 Bit 0
SDO
FSDO = 0
Bit 23 Bit 1 Bit 0
tSDODZ tSDODLY
FIRST READ COMMAND
tCSS
tSDIS tSDIH
SDI
tCSHIGH
Bit 23
SCLK
SDO
FSDO = 1
Bit 23 Bit 1 Bit 0
tSDODLY
ANY COMMAND
DATA FROM FIRST READ COMMAND
DATA FROM FIRST READ COMMAND
tSCLKHIGH tSCLKLOW
SYNC
Figure 6-3. SPI Read Timing Diagram
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6.17 Typical Characteristics: Voltage Output
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Code
Voltage Output INL (LSB)
32 544 1056 1568 2080 2592 3104 3616 4064
-4
-3.2
-2.4
-1.6
-0.8
0
0.8
1.6
2.4
3.2
4
Channel 1
Channel 0
Internal reference, gain = 4x
Figure 6-4. Voltage Output INL vs Digital Input Code
Code
Voltage Output INL (LSB)
32 544 1056 1568 2080 2592 3104 3616 4064
-4
-3.2
-2.4
-1.6
-0.8
0
0.8
1.6
2.4
3.2
4
Channel 1
Channel 0
Figure 6-5. Voltage Output INL vs Digital Input Code
Temperature (C)
Voltage Output INL (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-4
-3.2
-2.4
-1.6
-0.8
0
0.8
1.6
2.4
3.2
4
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-6. Voltage Output INL vs Temperature
Supply Voltage (V)
Voltage Output INL (LSB)
1.8 2.725 3.65 4.575 5.5
-4
-3.2
-2.4
-1.6
-0.8
0
0.8
1.6
2.4
3.2
4
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-7. Voltage Output INL vs Supply Voltage
Code
Voltage Output DNL (LSB)
32 544 1056 1568 2080 2592 3104 3616 4064
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Channel 1
Channel 0
Internal reference, gain = 4x
Figure 6-8. Voltage Output DNL vs Digital Input Code
Code
Voltage Output DNL (LSB)
32 544 1056 1568 2080 2592 3104 3616 4064
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Channel 1
Channel 0
Figure 6-9. Voltage Output DNL vs Digital Input Code
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Temperature (C)
Voltage Output DNL (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-10. Voltage Output DNL vs Temperature
Supply Voltage (V)
Voltage Output DNL (LSB)
1.8 2.725 3.65 4.575 5.5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-11. Voltage Output DNL vs Supply Voltage
Code
Voltage Output TUE (%FSR)
0 512 1024 1536 2048 2560 3072 3584 4095
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
Channel 1
Channel 0
Internal reference, gain = 4x
Figure 6-12. Voltage Output TUE vs Digital Input Code
Code
Voltage Output TUE (%FSR)
0 512 1024 1536 2048 2560 3072 3584 4095
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
Channel 1
Channel 0
Figure 6-13. Voltage Output TUE vs Digital Input Code
Temperature (C)
Voltage Output TUE (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
Channel 1
Channel 0
DAC channels at midscale
Figure 6-14. Voltage Output TUE vs Temperature
Supply Voltage (V)
Voltage Output TUE (%FSR)
1.8 2.725 3.65 4.575 5.5
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
Channel 1
Channel 0
DAC channels at midscale
Figure 6-15. Voltage Output TUE vs Supply Voltage
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Temperature (C)
Voltage Output Offset Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Channel 1
Channel 0
Figure 6-16. Voltage Output Offset Error vs Temperature
Temperature (C)
Voltage Output Gain Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Channel 1
Channel 0
Figure 6-17. Voltage Output Gain Error vs Temperature
Load Current (mA)
Voltage Output (V)
-5 -3.75 -2.5 -1.25 0 1.25 2.5 3.75 5
2.74
2.742
2.744
2.746
2.748
2.75
2.752
2.754
2.756
2.758
2.76
Channel 1
Channel 0
DAC channels at midscale
Figure 6-18. Voltage Output vs Load Current
Frequency (Hz)
AC Power-Supply Rejection Ratio (dB)
10 2030 50 100 200 5001000 10000 100000
-70
-60
-50
-40
-30
-20
-10
0
10
Figure 6-19. Voltage Output AC PSRR vs Frequency
Time (s)
0 10 20 30 40 50
LDAC (1 V/div)
VOUT (1 LSB/div)
Figure 6-20. Voltage Output Code-to-Code Glitch - Rising Edge
Time (s)
0 10 20 30 40 50
LDAC (1 V/div)
VOUT (1 LSB/div)
Figure 6-21. Voltage Output Code-to-Code Glitch - Falling Edge
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Time (s)
0 10 20 30 40 50
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
Zero scale to full scale swing
Figure 6-22. Voltage Output Setting Time - Rising Edge
Time (s)
0 10 20 30 40 50
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
Full scale to zero scale swing
Figure 6-23. Voltage Output Setting Time - Falling Edge
Time (s)
0 200 400 600 800 1000 1200 1400 1600
VDD (1 V/div)
VOUT (15 mV/div)
DAC in Hi-Z power-down mode
Figure 6-24. Voltage Output Power-On Glitch
Time (s)
0 200 400 600 800 1000 1200 1400 1600
VDD (1 V/div)
VOUT (1 mV/div)
DAC at zero scale
Figure 6-25. Voltage Output Power-Off Glitch
Frequency (Hz)
Noise Density (V/Hz)
10 2030 50 100 200 5001000 10000 100000
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
Internal reference, gain = 4x
Figure 6-26. Voltage Output Noise Density
Frequency (Hz)
Noise Density (V/Hz)
10 2030 50 100 200 5001000 10000 100000
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Figure 6-27. Voltage Output Noise Density
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6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Time (s)
Noise Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
Internal reference, gain = 4x, f = 0.1 Hz to 10 Hz
Figure 6-28. Voltage Output Flicker Noise
Time (s)
Noise Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
-25
-20
-15
-10
-5
0
5
10
15
20
25
f = 0.1 Hz to 10 Hz
Figure 6-29. Voltage Output Flicker Noise
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6.18 Typical Characteristics: Current Output
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
Code
Current Output INL (LSB)
0 32 64 96 128 160 192 224 255
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Channel 1
Channel 0
Figure 6-30. Current Output INL vs Digital Input Code
Temperature (C)
Current Output INL (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-31. Current Output INL vs Temperature
Supply Voltage (V)
Current Output INL (LSB)
1.8 2.725 3.65 4.575 5.5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-32. Current Output INL vs Supply Voltage
Code
Current Output DNL (LSB)
0 32 64 96 128 160 192 224 255
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Channel 1
Channel 0
Figure 6-33. Current Output DNL vs Digital Input Code
Temperature (C)
Current Output DNL (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-34. Current Output DNL vs Temperature
Supply Voltage (V)
Current Output DNL (LSB)
1.8 2.725 3.65 4.575 5.5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
CH1 MAX
CH0 MAX
CH1 MIN
CH0 MIN
Figure 6-35. Current Output DNL vs Supply Voltage
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6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
Code
Current Output TUE (%FSR)
0 32 64 96 128 160 192 224 255
-2
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2
Channel 1
Channel 0
Figure 6-36. Current Output TUE vs Digital Input Code
Temperature (C)
Current Output TUE (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-2
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2
Channel 1
Channel 0
DAC channels at midscale
Figure 6-37. Current Output TUE vs Temperature
DAC channels at midscale
Figure 6-38. Current Output TUE vs Supply Voltage
Temperature (C)
Current Output Offset Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
Channel 1
Channel 0
Figure 6-39. Current Output Offset Error vs Temperature
Temperature (C)
Current Output Gain Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
Channel 1
Channel 0
Figure 6-40. Current Output Gain Error vs Temperature
Load Voltage (V)
Current Output (A)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
CH1, DAC Code = 0
CH0, DAC Code = 0
CH1, DAC Code = 255
CH0, DAC Code = 255
Figure 6-41. Current Output vs Load Voltage
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