Texas Instruments TPS40003 User manual

User’s Guide
TPS40003 Based 5–A Converter in
Less Than One Square Inch
User’s Guide

2
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Copyright 2003, Texas Instruments Incorporated

3
DYNAMIC WARNINGS AND RESTRICTIONS
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

SLUU130A –September 2002 –Revised February 2003
4TPS40003-Based 5-A Converter in Less Than One Square Inch
TPS40003-Based 5-A Converter in Less Than One Square
Inch
Mark Dennis Systems Powe
r
Contents
1 Introduction 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Features 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Schematic 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Design Procedure 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 PowerPADPackaging 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Test Results/Performance Data 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 PCB Layout 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 List of Material 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction
The TPS40002 and the TPS40003 are voltage-mode, synchronous buck PWM controllers that utilize TI’s
proprietary Predictive Gate Drivetechnology to wring maximum efficiency from step-down converters. These
controllers provide a bootstrap charging circuit to allow the use of an N-channel MOSFET as the topside buck
switch to reduce conduction losses and increase silicon device utilization. Predictive Gate Drivetechnology
controls the delay from main switch turn-off to synchronous rectifier turn-on and also the delay from rectifier
turn-off to main switch turn-on. This allows minimization of the losses in the MOSFET body diodes by reducing
conduction and reverse recovery time. This user’s guide provides details on a 5-A buck converter that converts
3.3 V down to a 1.2-V level utilizing the TPS40003 controller, with less than one square inch board area.
A schematic for the board is shown in Figure 1. A list of material is provided in the final section.
2 Features
The specification for this board is as follows:
DVIN = 3.0 V to 3.6 V
DVOUT = 1.2 V ±3%
D0 A ≤IOUT ≤5 A
DEfficiency > 90% with a load of 2 A
DOutput voltage ripple < 2% VOUT
DPhysical size < 1 square inch circuit area

SLUU130A –September 2002 –Revised February 2003
5
TPS40003-Based 5-A Converter in Less Than One Square Inch
3 Schematic
+
Figure 1. Application Diagram for the TPS40002/3

SLUU130A –September 2002 –Revised February 2003
6TPS40003-Based 5-A Converter in Less Than One Square Inch
4 Design Procedure
4.1 TPS4000X Family Device Selection
The TPS4000X family of devices offers four selections to encompass the frequency and output current mode
choices. The TPS40003 is selected for the following reasons. First, the internal oscillator components set a fixed
switching frequency of 600 kHz. This allows minimally sized filter components in this compact design. The other
choice related to the TPS4000X family involves the selection of Discontinuous Current Mode (DCM) operation
or Continuous Current Mode (CCM) operation at lighter loads. In this design the TPS40003 is selected to keep
the current continuous all the way to zero load, to provide robust control characteristics.
4.2 Inductance Value
The output inductor value is selected to set the ripple current to a value most suited to overall circuit functionality.
The inductor value is calculated in equation (1).
L+VOUT
f IRIPPLEȧ
ȡ
Ȣ1*VOUT
VIN(max)ȧ
ȣ
Ȥ+1.2 V
600 kHz 1.25 A ǒ1*1.2 V 3.6 VǓ+1.07 mH
where IRIPPLE is chosen to be 25% of IOUT, or 1.25 A. A common value of 1 µH is selected.
4.3 Input Capacitor Selection
Bulk input capacitor selection is based on allowable input voltage ripple and required RMS current carrying
capability. In typical buck converter applications, the converter is fed from an upstream power converter with
its own output capacitance. In this converter, onboard capacitance is provided to supply the current required
during the top MOSFET on-time while keeping ripple within acceptable limits. For this power level, input voltage
ripple of 150 mV is reasonable, and a conservative minimum value of capacitance is calculated in equation (2).
C+I Dt
DV+5A 606 ns
0.15 V +20 mF
To meet this requirement with the lowest size and cost, a single 22 µF, X5R ceramic capacitor might be
considered. Although these capacitors have an extremely small resistance a typical datasheet indicates that
the part undergoes a 30°C temperature rise with 2 ARMS current at 500 kHz. With VIN= 3.0 V our circuit requires
nearly 2 ARMS of current, so for a conservative design two capacitors are selected to allow for conservative
current derating. These capacitors function as power bypass components and should be located near the
MOSFET package, to keep the high frequency current flow in a tight loop. The low impedance characteristics
of the dual ceramic capacitors help to reduce noise on the VDD supply of the device. Specifically, the high side
MOSFET current sense is referenced to this point, so noise at the device must be kept to a low level.
(1)
(2)

SLUU130A –September 2002 –Revised February 2003
7
TPS40003-Based 5-A Converter in Less Than One Square Inch
4.4 Output Capacitor Selection
Selection of the output capacitor is based on many application variables, including function, cost, size, and
availability. The minimum allowable output capacitance is determined by the amount of inductor ripple current
and the allowable output ripple in equation (3).
COUT(min) +IRIPPLE
8 f VRIPPLE +1.25 A
8 600 kHz 12 mV +22 mF
In this design, COUT(min) is 22 µF with VRIPPLE = 12 mV to allow for some margin. However, this only affects the
capacitive component of the ripple voltage. In addition, the voltage component due to the capacitor ESR must
be considered in equation (4).
ESRCout vVRIPPLE
IRIPPLE +0.012 V
1.25 A +9.6 mW
For compactness while maintaining transient response capability, two 22-µF ceramic capacitors are fitted in
parallel. The total ESR of these capacitors is below 3 mΩ, and contributes only a few mV to the output voltage
ripple.
4.5 MOSFET Selection
The small physical size of this design requires the use of a single SO-8 package which contains dual N-channel
MOSFETs. MOSFETs with an RDS(on) of 18 mΩare selected to keep the conduction losses to a manageable
amount at full load.
4.6 Short Circuit Protection
The TPS40003 implements short circuit protection by comparing the voltage across the topside MOSFET while
it is on to a voltage dropped from VDD by RLIM due to an internal current source of 15 µA inside pin 1. Due to
tolerances in the current source and variations in the power MOSFET on-voltage versus temperature, the short
circuit level can protect against gross overcurrent conditions only, and should be set higher than rated load. In
this particular case, RLIM is selected as:
RLIM +R1 +2.5 IOUT 0.018 W
15 mA+15 kW
For this design, RLIM = 15 kΩ, and the factor of 2.5 in the equation accounts for the variations in component
tolerances over temperature and output current ripple. The high currents that are switched under short circuit
conditions may cause SW pin 8 to be driven below ground several volts, possibly injecting substrate current
which can cause improper operation of the device. A 3.3-Ωresistor has been placed in series with this pin to
limit its excursion to safe levels.
(3)
(4)
(5)

SLUU130A –September 2002 –Revised February 2003
8TPS40003-Based 5-A Converter in Less Than One Square Inch
4.7 Compensation Design
The TPS40003 uses voltage mode control in conjunction with a high frequency error amplifier. For the fastest
transient response, the loop crossover frequency is set at 1/10 fS, or 60 kHz. The power circuit L-C double pole
corner frequency fCis situated at 24 kHz, and the output capacitor ESR zero is far higher at approximately 1MHz.
The feedback compensation network is implemented to provide two zeroes and three poles. The first pole is
placed at the origin to improve dc regulation.
The first zero is placed at approximately 2/3 fC, 18 kHz,
fz1 +1
2 p R2 C4
The second zero is selected at fC,
fz2 +1
2 p ǒR4)R5Ǔ C12
The two poles are placed at approximately 300 kHz, which is one-half the switching frequency,
fp1 +1
2 p R2 ǒC4 C8
C4)C8Ǔ
and
fp2 +1
2 p R5 C12
(6)
(7)
(8)
(9)

SLUU130A –September 2002 –Revised February 2003
9
TPS40003-Based 5-A Converter in Less Than One Square Inch
Figure 2 shows the plots for the closed loop gain and phase with VIN = 3.3 V and IOUT = 4.4 A. At the crossover
frequency of 60 kHz the phase margin is approximately 51 degrees.
100
150
100
50
0
–50
–100
40
30
20
10
0
–10
–20
–30
–40
1000 10000 1000000
Frequency – Hz
100000
Phase
–150
Gain – db
GAIN AND PHASE MARGIN
vs
FREQUENCY
Phase – degrees
ILOAD = 4.4 A
VI= 3.3 V
Gain
Figure 2.
4.8 Snubber Component Selection
The switch node where Q1 and L1 come together is very noisy. An R–C network fitted between this node and
ground can help reduce ringing and voltage overshoot on Q1:B. This ringing noise should be minimized to
prevent it from confusing the control circuitry which is monitoring this node for current limit and Predictive Gate
Drive.
As a starting point, the snubber capacitor, C9, is generally chosen to be 5 to 8 times larger than the parasitic
capacitance at the node, which is primarily COS of Q1:B. Since COS is 440 pF for Q1:B, C9 is chosen to be 3.3 nF.
R3 is empirically determined to be 2.2 Ω, which minimizes the ringing and overshoot at the switch node. With
low input voltages the power loss, 1/2×C×V2×f , is relatively small at 24 mW.

SLUU130A –September 2002 –Revised February 2003
10 TPS40003-Based 5-A Converter in Less Than One Square Inch
5 PowerPADPackaging
The TPS4000X family is available in the DGQ version of TI’s PowerPADthermally enhanced package. In the
PowerPAD, a thermally conductive epoxy is utilized to attach the integrated circuit die to the leadframe die
pad, which is exposed on the bottom of the completed package. The leadframe die pad can be soldered to the
PCB using standard solder flow techniques when maximum heat dissipation is required. However, depending
on power dissipation requirements, the PowerPADmay not need to soldered to the PCB.
The PowerPADpackage helps to keep the junction temperature rise relatively low even with the power
dissipation inherent in the onboard MOSFET drivers. This power loss is proportional to switching frequency,
drive voltage, and the gate charge needed to enhance the N-channel MOSFETs. Effective heat removal allows
the use of ultra small packaging while maintaining high component reliability.
To effectively remove heat from the PowerPADpackage, a thermal land should be provided directly
underneath the package whether the package needs to be soldered or not. This thermal land usually has vias
that help to spread heat to internal copper layers and/or the opposite side of the PCB. The vias should not have
thermal reliefs that are often used on ground planes, because this reduces the copper area which transfers heat.
Additionally, the vias should be small enough so that the holes are effectively plugged when plated. This
prevents the solder from wicking away from the connection between the PCB surface and the bottom of the part.
A typical construction utilizes a few vias of 0.013”diameter plated with 1 ounce copper in the land under the
TPS40003. A typical layout pattern is shown in Figure 2, but does not show the copper land which would
encompass the vias above and below the device.
2.92mm
(0.115”)
0.5mm
(0.0197”)
0.28mm
(0.011”)
1.40mm
(0.055”)Via Dia.
0.33mm
(0.013”)
Miminum
PowerPad ”X”
1.3mm
(0.050”)
Minimum
PowerPad ”Y”
1.7mm
(0.068”)
Figure 3. PowerPAD PCB Layout Guidelines
The Texas Instrument document, PowerPADThermally Enhanced Package Application Report (SLMA002)
should be consulted for more information on the PowerPADpackage. This report offers in-depth information
on the package, assembly and rework techniques, and illustrative examples of the thermal performance of the
PowerPADpackage.

SLUU130A –September 2002 –Revised February 2003
11
TPS40003-Based 5-A Converter in Less Than One Square Inch
6 Test Results/Performance Data
The test setup is shown in figure 4
SLUP182
TP2 TP1
TP4
TP6
TP3
TP5
J1
J2
LOAD
VIN
VOUTGND
GND
(+)
(–)
DVM2
(–)
(+)
DVM1
(–)(+)
SCOPE
C+
DC Power
Supply
CIN = 470 µF or larger, 6.3 V or higher,
low ESR AIEA or OSCON capacitor.
Place within 2 inches of J1.
Input wires 18 gauge
or larger short as feasible
Output wires 18 gauge
or larger short as feasible
Resistive load: 0.5 Ω, ≥5 W
Active Load: set for 2.4 A
IN
Figure 4.

SLUU130A –September 2002 –Revised February 2003
12 TPS40003-Based 5-A Converter in Less Than One Square Inch
Typical efficiency curves are shown in Figure 5 for an input of 3.3 V.
Efficiency –%
EFFICIENCY
vs
OUTPUT CURRENT
IOUT –Output Current –A
0123456
50
55
60
65
70
75
80
85
90
95
100
Figure 5.
Figure 6 shows the switch node during typical operation at full load. Note that there is very minimal body diode
conduction in the bottom MOSFET. This is a result of using the predictive delay control implementation. This
technique is able to dynamically change the delays in the MOSFET drive circuit to account for variations in line,
load, and between devices.
t –Time –250 ns/div
2 V/div
TYPICAL SWITCH NODE WAVEFORM
Figure 6.

SLUU130A –September 2002 –Revised February 2003
13
TPS40003-Based 5-A Converter in Less Than One Square Inch
Circuit operation with an output short circuit is shown in Figure 7. After each restart into a short circuit the pulses
terminate for a period of approximately 6 ms. This causes the input power to collapse to minuscule levels, and
the circuit is protected.
t –Time –1 ms/div
2 V/div
SHORT CIRCUIT OPERATION
Figure 7.
Figure 8 shows the output voltage ripple which is approximately half the 24-mV limit.
t –Time –500 ns/div
10 mV/div
OUTPUT VOLTAGE RIPPLE
Figure 8.

SLUU130A –September 2002 –Revised February 2003
14 TPS40003-Based 5-A Converter in Less Than One Square Inch
Figure 9 shows the startup waveforms with an input voltage of 3.3 V and a load of 0.3 Ω. Note that the output
is held low until VSS (pin 4) goes above 0.12 V, and then the output comes up smoothly under closed loop
softstart control.
STARTUP WAVEFORM
t –Time –200 µs/div
1 V/div
500 mV/div
500 mV/div
Figure 9.
Figure 10 shows the transient response for a fast load step from 1 A to 2 A.
TRANSIENT RESPONSE
t –Time –20 µs/div
50 mV/div
Figure 10.

SLUU130A –September 2002 –Revised February 2003
15
TPS40003-Based 5-A Converter in Less Than One Square Inch
7 PCB Layout
Figures 11 through13 show the top copper layer, the bottom copper layer, and top assembly layer, of SLUP182.
Figure 12
Figure 13

SLUU130A –September 2002 –Revised February 2003
16 TPS40003-Based 5-A Converter in Less Than One Square Inch
8 List of Material
Table 1 lists the components used in this design. With minor component tweaks this design could be modified
to meet a wide range of applications.
Reference Qty Description Manufacturer Part Number
Capacitor C1, C2, C5, C6 4Ceramic, 22 µF, 6.3 V, X5R, 20%, 1210 Panasonic ECJ–4YB0J226M
C10 1 Ceramic, 0.001 µF, 10 V, X5R, 10%, 805 Panasonic ECJ–2YB1A105K
C11 1 Ceramic, 0.0047 µF, 50 V, X7R, 10% Vishay VJ0603Y472KXAAT
C12 1 Ceramic, 470 pF, 50 V, X7R, 10% Vishay VJ0603Y471KXAAT
C3 1 Ceramic, 0.1 µF, 50 V, X5R, 10% Vishay VJ0805Y104KXAAT
C4 1 Ceramic, 0.001 µF, 50 V, X7R, 10% Vishay VJ0603Y102KXAAT
C8 1 Ceramic, 68 pF, 50 V, NPO, 10% Vishay VJ0603A680KXAAT
C9 1 Ceramic, 0.0033 µF, 50 V, X7R, 10% Vishay VJ0805Y332KXAAT
Terminal Block J1, J2 22 pin, 15 A, 5.1 mm OST ED1609
Inductor L1 1 SMT, 1.0 µH, 8.5 A, 10 mΩVishay IHLP–2525CZ–01
MOSFET Q1 1 Dual N–channel, 20 V, 9.4 A, 18 mΩFairchild FDS6898A
Resistor R1 1 Chip, 15 kΩ, 1/16W, 1% Std Std
R2 1 Chip, 8.66 kΩ, 1/16 W, 1% Std Std
R3 1 Chip, 2.2 Ω, 1/10 W, 5% Std Std
R4 1 Chip, 12.1 kΩ, 1/16 W, 1% Std Std
R5 1 Chip, 1 kΩ, 1/16 W, 1% Std Std
R6 1 Chip, 16.9 Ω, 1/16 W, 1% Std Std
R7 1 Chip, 3.3 Ω, 1/16 W, 5%, 603 Std Std
JACK TP1, TP3, TP4, 5Test point, red Farnell 240–345
JACK TP2, TP6 2Test point, black Farnell 240–333
Adaptor TP5 1 3.5-mm probe clip (or 131–5031–00) Tektronix 131–4244–00
Device U1 1 Syncronous buck controller, 600 kHz TI TPS40003DGQ

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Post Office Box 655303
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Copyright 2003, Texas Instruments Incorporated