Texas Instruments TPS40001 User manual

User’s Guide
TPS40001 Based Converter Delivers
10-A Output
User’s Guide

2
EVM IMPORTANT NOTICE
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Copyright 2003, Texas Instruments Incorporated

3
DYNAMIC WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 VDC to 5.5 VDC.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.
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maintained. These components include but are not limited to linear regulators, switching transistors, pass
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

SLUU131A –September 2002 –Revised February 2003
4TPS40001 Based Converter Delivers 10-A Output
TPS40001 Based Converter Delivers 10-A Output
Mark Dennis DC to DC Controller Products
Contents
1 Introduction 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Features 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Schematic 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Design Procedure 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PowerPAD Packaging 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Test Results/Performance Data 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 PCB Layout 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 List of Material 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction
The TPS40000 and the TPS40001 are voltage-mode, synchronous buck PWM controllers that utilize TI’s
proprietary Predictive Gate Drivetechnology to wring maximum efficiency from step-down converters. This
controller family provides a bootstrap circuit to allow the use of an N-channel MOSFET as the topside buck
switch to reduce conduction losses and increase silicon device utilization. Predictive Gate Drivetechnology
controls the delay from main switch turn-off to synchronous rectifier turn-on and also the delay from rectifier
turn-off to main switch turn-on. This allows minimization of the losses in the MOSFET body diodes, both
conduction and reverse recovery. This design note provides details on a buck converter that converts an input
of 3 V to 5 V down to a 2.5-V output level utilizing either the TPS40000 or TPS40001 controller.
A schematic for the board is shown in Figure 1. The list of material is provided in section 7 of this User’s Guide.
2 Features
The specification for this board is as follows:
DVIN = 3.0 V to 5 V
DVOUT = 2.5 V +/–3%
DIOUT = 0 A to 10 A
DEfficiency = >95% with VIN = 3.3 V, load 4 A
DOutput voltage ripple < 2% VOUT
DPower semiconductor devices: Each MOSFET is a single SO-8 package

SLUU131A –September 2002 –Revised February 2003
5
TPS40001 Based Converter Delivers 10-A Output
3 Schematic
+
+
+
+
Figure 1. Application Diagram for the TPS40002/3

SLUU131A –September 2002 –Revised February 2003
6TPS40001 Based Converter Delivers 10-A Output
4 Design Procedure
4.1 TPS4000X Family Device Selection
The TPS4000X family of devices offers four selections to encompass the frequency and
continuous/discontinuous inductor current options. The TPS4000/1 are selected for this high current application
because the 300-kHz switching frequency enables higher efficiency. The TPS40002/3 are available for
applications needing 600-kHz operation. The TPS4000X family also allows the user to select Discontinuous
Current Mode (DCM) operation or Continuous Current Mode (CCM) operation at lighter loads. In this reference
design the TPS40001 is selected to maintain continuous mode operation down to zero load. If desired, the
TPS40000 can be installed to turn the synchronous MOSFET off when the controller senses the inductor current
reaching zero, indicating the circuit is entering the DCM of operation.
4.2 Inductance Value
The output inductor value is selected to set the ripple current to a value most suited to overall circuit functionality.
An inductor selection that is too small leads to larger ripple current that increases RMS current losses in the
inductor and MOSFETs, and also leads to more ripple voltage on the output. The inductor value is calculated
by equation (1),
LMIN +VOUT
f IRIPPLE ǒ1*VOUT
VIN(max)Ǔ+2.5 V
300 kHz 4A ǒ1*2.5 V 5VǓ+1.0 mH
in which IRIPPLE is chosen to be 40% of IOUT, or 4 A at max VIN. This high value of ripple current is selected to
keep the inductor small to minimize the RDS(on) losses due to the high output current. A synchronous rectifier
controller that maintains continuous inductor current down to no load eliminates concerns arising from crossing
the DCM boundary. A standard value of 1 µH with a resistance of 3.5 mΩis selected. At full load the power loss
is only 0.35 W, which is only 1.4% of the 25-W output power.
4.3 Input Capacitor Selection
Bulk input capacitor selection is based on allowable input voltage ripple and required RMS current carrying
capability. In typical buck converter applications, the converter is fed from an upstream power converter with
its own output capacitance. In this standalone supply, onboard capacitance is added to handle input voltage
ripple and RMS current considerations. For this power level, input voltage ripple of 150 mV is reasonable, and
a conservative minimum value of capacitance is calculated as
C+I Dt
DV+10 A 2.5 ms
0.15 V +167 mF
In addition to this minimum capacitance requirement, the RMS current stresses must be considered. In this
converter, the large duty cycle causes the input RMS current to be nearly as large as the output current. This
simplified formula calculates the RMS current for a trapazoidal current waveform, shown in equation (3).
IRMS +I D
Ǹ+I VOUT
VIN(min)
Ǹ+10 A 2.5 V
3.0 V
Ǹ+9.1 A
Additional terms for the ripple component of the current add only a small amount to the total RMS current, and
can be neglected. To meet this initial requirement with small size and cost, a combination of capacitors is
considered. To carry the high frequency ripple current, three 22-µF, X5R ceramic capacitors are placed close
to the power circuitry. Although these capacitors have an extremely small resistance, the datasheet indicates
that the part undergoes a 30_C temperature rise with 2 ARMS current at 500 kHz, so more current capability is
needed. Two 330-µF POSCAPs with an RMS current capability of 4.4 A each is selected. In typical embedded
converters, these POSCAPs is not required if the upstream converter feeding this buck has sufficient current
handling capability.
(1)
(2)
(3)

SLUU131A –September 2002 –Revised February 2003
7
TPS40001 Based Converter Delivers 10-A Output
4.4 Output Capacitor Selection
Selection of the output capacitor is based on many application variables, including function, cost, size, and
availability. First, the minimum allowable output capacitance should be determined by the amount of inductor
ripple current and one-half the allowable output ripple, as given in equation (4).
COUT(min) +IRIPPLE
8 f VRIPPLE +4A
8 300 kHz 25 mV +67 mF
This only affects the capacitive component of the ripple voltage. In addition, the voltage component due to the
capacitor ESR must be considered, shown in equation (5).
ESRCout vVRIPPLE
IRIPPLE +25 mV
4A +6.25 mW
To minimize capacitor size while maintaining good transient response, two 470-µF POSCAPs (with an ESR of
10 mΩeach) are fitted in paralleled with a 1-µF ceramic capacitor.
4.5 MOSFET Selection
One constraint of this design is the use of one SO-8 MOSFET in the upper switch device and one SO-8 in the
lower synchronous rectifier location in the buck converter power stage. The upper device loss is usually
dominated by switching loss, so a device with lower gate charge and switching times was selected. Since this
application has a relatively high output voltage, the upper device runs at a high duty cycle and needs to have
a low RDS(on) to keep conduction losses low, and an 8-mΩdevice with a maximum gate charge of 30 nC is
selected. The same device is fitted in the bottom switch location to achieve high efficiency.
4.6 Short Circuit Protection
The TPS40003 implements short circuit protection by comparing the voltage across the topside MOSFET while
it is on to a voltage dropped from VDD by RLIM due to an internal current source of 15 µA inside pin 1. Due to
tolerances in the current source and variations in the power MOSFET on-voltage versus temperature, the short
circuit level can protect against gross overcurrent conditions only, and should be set much higher than rated
load. In this particular case, RLIM is selected as shown in equation (6).
RLIM +R2 +3 IOUT RDS(on)
15 mA+3 10 A 0.008 W
15 mA+15 kW
For this design, a standard value of 16.2 kΩis selected for R2. The factor of 3 in the equation accounts for the
variations in component tolerances (both initial and over temperature) and output current ripple. The component
tolerances include MOSFET RDS(on), ILIM sink current, and the VOS offset voltage of SW vs ILIM. The high
currents that are switched under short circuit conditions may cause SW pin 8 to be driven below ground several
volts, possibly injecting substrate current which can cause improper operation of the device. A 3.3-Ωresistor
has been placed in series with this pin to limit its excursion to safe levels.
(4)
(5)
(6)

SLUU131A –September 2002 –Revised February 2003
8TPS40001 Based Converter Delivers 10-A Output
4.7 Compensation Design
The TPS40000 uses voltage mode control in conjunction with a high frequency error amplifier. The power circuit
L-C double pole corner frequency fCis located in equation (7).
FreqLC +1
2 p LOUT COUT
Ǹ+5.1 kHz
The output capacitor ESR zero is calculated by equation (8),
FZ(esr) +1
2 p RESR COUT +33.8 kHz
where the two POSCAPs ESR of 5 mΩis used in the calculation because the 1 µF is effectively out of the picture
at these relatively low frequencies.
The feedback compensation network is implemented to provide two zeroes and three poles. The first pole is
placed near the origin to improve dc regulation.
The first zero is placed below fCat 2.2 kHz in equation (9).
fz1 +1
2 p ǒR6)R7Ǔ C15
The second zero is placed at 18 kHz shown in equation (10).
fz2 +1
2 p R4 C7
The first pole is placed near the ESR zero frequency in equation (11),
fp1 +1
2 p R7 C15
and the second pole is placed at one-half the switching frequency at 150 kHz to allow a high-speed transient
response, shown in equation (12).
fp2 +1
2 p R4 ǒC7 C11
C7)C11Ǔ
(7)
(8)
(9)
(10)
(11)
(12)

SLUU131A –September 2002 –Revised February 2003
9
TPS40001 Based Converter Delivers 10-A Output
Figure 2 is presents the measured loop gain and phase characteristics. At the loop crossover frequency of
20 kHz the phase margin is approximately 50 degrees.
Gain – db
GAIN AND PHASE MARGIN
vs
FREQUENCY
Phase – degrees
–40
–30
–20
–10
0
10
20
30
40
50
30
–200
–150
–100
–50
0
50
100
150
200
100 1000 10000 100000 1000000
Phase
Gain
Frequency – Hz
Figure 2.
4.8 Snubber Component Selection
The switch node where Q1 and L1 come together is very noisy. An R-C network fitted between this node and
ground can help reduce ringing and voltage overshoot on Q2. This ringing noise should be minimized to prevent
it from confusing the control circuitry which is monitoring this node for current limit, Predictive Gate Drivet, and
DCM control functions.
As a starting point, the snubber capacitor, C12, is generally chosen to be 5 to 8 times larger than the parasitic
capacitance at the node, which is primarily COS of Q2. Since COS is around 1600 pF for Q2at5V, C12 is chosen
to be 10 nF. R3 is empirically determined to be 2.2 Ω, which minimizes the ringing and overshoot at the switch
node. With the relatively low input voltage of 5 V, the power loss, ½CV2f, is relatively small at 37 mW.

SLUU131A –September 2002 –Revised February 2003
10 TPS40001 Based Converter Delivers 10-A Output
5 PowerPAD Packaging
The TPS4000X family is available in the DGQ version of TI’s PowerPADtthermally enhanced package. In the
PowerPADt, a thermally conductive epoxy is utilized to attach the integrated circuit die to the leadframe die
pad, which is exposed on the bottom of the completed package. The leadframe die pad can be soldered to the
PCB using standard solder flow techniques when maximum heat dissipation is required. However, depending
on power dissipation requirements, the PowerPADtmay not need to soldered to the PCB.
The thermally conductive epoxy bonding the circuit die to the leadframe die pad causes a high resistance from
the leadframe die pad to the device ground pin 5. When the PowerPadtpackage is soldered to the PCB, the
leadframe die pad can be connected to ground (pin 5), but this is not required. The leadframe die pad should
not be connected to other potentials in the circuit.
The PowerPADtpackage helps to keep the junction temperature rise relatively low even with the power
dissipation inherent in the onboard MOSFET drivers. This power loss is proportional to switching frequency,
drive voltage, and the gate charge needed to enhance the N-channel MOSFETs. Effective heat removal allows
the use of ultra small packaging while maintaining high component reliability.
To effectively remove heat from the PowerPADtpackage, a thermal land should be provided directly
underneath the package. This thermal land usually has vias that help to spread heat to internal copper layers
and/or the opposite side of the PCB. The vias should not have thermal reliefs that are often used on ground
planes, because this reduces the copper area to transfer heat. Additionally, the vias should be small enough
so that the holes are effectively plugged when plated. This prevents the solder from wicking away from the
connection between the PCB surface and the bottom of the part. A typical footprint pattern is shown in Figure 2,
but does not include the additional copper plane which includes the vias above and below the device.
2.92mm
(0.115”)
0.5mm
(0.0197”)
0.28mm
(0.011”)
1.40mm
(0.055”)Via Dia.
0.33mm
(0.013”)
Miminum
PowerPad ”X”
1.3mm
(0.050”)
Minimum
PowerPad ”Y”
1.7mm
(0.068”)
Figure 3. PowerPADtPCB Layout Guidelines
The Texas Instrument document, PowerPADtThermally Enhanced Package Application Report (Texas
Instrument Literature Number SLMA002) should be consulted for more information on the PowerPADt
package. This report offers in-depth information on the package, assembly and rework techniques, and
illustrative examples of the thermal performance of the PowerPADtpackage.

SLUU131A –September 2002 –Revised February 2003
11
TPS40001 Based Converter Delivers 10-A Output
6 Test Results/Performance Data
6.1 Test Setup
LOAD (+)
(–)
DVM2
(–)
(+)
DVM1
(–)
(+)
SCOPE
Load adjustable
from 0–10Amps
GND
VOUT
VIN
GND
SLUP183A
J1
J2
TP6 TP5
TP7
TP1 TP3
TP2 TP4
dc power supply
adjustable from
0 V to 5 V
Input wires 16
gauge or larger, as
short as feasible
Output wires 16
gauge or larger, as
short as feasible
IIN
IOUT
Figure 4. Test Setup

SLUU131A –September 2002 –Revised February 2003
12 TPS40001 Based Converter Delivers 10-A Output
Typical efficiency curves are shown in Figure 5 for 3.3-V input. It should be stressed that measuring high
efficiencies requires the utmost care in instrumentation. The power losses are so low that small errors can lead
to large variations in measured efficiency. The input and output voltages are measured on the PCB as shown
in the test diagram to avoid the losses associated with the input and output connectors.
Efficiency –%
EFFICIENCY
vs
OUTPUT CURRENT
IOUT –Output Current –A
50
55
60
65
70
75
80
85
90
95
100
0.00 2.00 6.00 8.00 10.00
4.00
Figure 5.
Figure 6 shows the switch node at VIN = 5 V and IOUT =10 A. As the picture indicates, there is almost negligible
body diode conduction using the Predictive Gate Drivettechnique.
t –Time –500 ns/div
2 V/div
TYPICAL SWITCH NODE WAVEFORM
Figure 6.

SLUU131A –September 2002 –Revised February 2003
13
TPS40001 Based Converter Delivers 10-A Output
Figure 7 shows the output voltage ripple at high VIN and full load, which is the worst case condition for output
voltage ripple.
t –Time –1 µs/div
10 mV/div
OUTPUT VOLTAGE RIPPLE
Figure 7.
Figure 8 shows the transient response with a 50% load step from 2.5 A to 7.5 A.
t –Time –20 µs/div
50 mV/div
TRANSIENT RESPONSE
Figure 8.

SLUU131A –September 2002 –Revised February 2003
14 TPS40001 Based Converter Delivers 10-A Output
7 PCB Layout
The PCB top assembly and copper layers are shown in Figures 9 through 11.
Figure 9 Figure 10
Figure 11

SLUU131A –September 2002 –Revised February 2003
15
TPS40001 Based Converter Delivers 10-A Output
8 List of Material
Table 1 lists the components used in this design. With minor component tweaks this design could be modified
to meet a wide range of applications.
Reference Qty Description Manufacturer Part Number
Capacitor C1, C2 2POSCAP, 330 µF, 6.3 V, 10 milliohm, 20%,
7343 (D) Sanyo 6TPD330M
C11 1 Ceramic, 180 pF, 50 V, NPO, 10%, 805 Vishay VJ0805A181KXAAT
C12 1 Ceramic, 0.01µF, 50 V, X7R, 10%, 805 Vishay VJ0805Y103KXAAT
C13 1 Ceramic, 0.0047 µF, 50 V, X7R, 10%, 805 Vishay VJ0805Y472KXAAT
C15 1 Ceramic, 6.8 nF, 50 V, X7R, 10%, 805 Vishay VJ0805Y682KXAAT
C3, C4, C5 3Ceramic, 22 µF, 6.3 V, X5R, 20%, 1210 Panasonic ECJ–4YB0J226M
C6, C10, C14 3Ceramic, 1 µF, 10 V, X5R, 10%, 805 Panasonic ECJ–2YB1A105K
C7 1 Ceramic, 1.5 nF, 50 V, X7R, 10%, 805 Vishay VJ0805Y152KXAAT
C8, C9 2POSCAP, 470 µF, 4 V, 10 mΩ, 20%, 7343 (D) Sanyo 4TPD470M
Terminal Block J1, J2 24-pin, 15 A, 5.1 mm, 291126 OST ED2227
Inductor L1 1 Inductor, SMT, 1 µH, 15 A, 3.5 mΩ, 0.51 x 0.51 Vishay IHLP–5050CE–01
MOSFET Q1, Q2 2MOSFET, N-channel, 12 V, 17 A, 5.5 mΩ, SO8 Siliconix Si4866DY
Resistor R1, R5 1Chip, 1.8 Ω, 1/10 W, 5%, 805 Std Std
R2 1 Chip, 16.2 kΩ, 1/10 W, 1%, 805 Std Std
R3 1 Chip, 2.2 Ω, 1/10 W, 5%, 805 Std Std
R4 1 Chip, 5.90 kΩ, 1/10 W, 1%, 805 Std Std
R6 1 Chip, 10 kΩ, 1/10 W, 1%, 805 Std Std
R7 1 Chip, 698 Ω, 1/10 W, 1%, 805 Std Std
R8 1 Chip, 3.92 Ω, 1/10 W, 1%, 805 Std Std
R9 1 Chip, 3.3 Ω, 1/10 W, 5%, 805 Std Std
JACK TP1, TP4, TP5, 3Red, 1 mm, 0.038”, 6400”Farnell 240–345
Adapter TP2, TP6 23.5-mm probe clip (or 131–5031–00), 72900 Tektronix 131–4244–00
JACK TP3, TP7 1Black, 1mm, 0.038”,6400”Farnell 240–333
Device U1 1 Low Input Voltage Mode,
Syncronous Buck Controller DGQ10 TI TPS40001DGQ

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Copyright 2003, Texas Instruments Incorporated