Texas Instruments TMS320DM36X User manual

TMS320DM36x DMSoC Analog to DigitalConverter (ADC) Interface
User's Guide
Literature Number: SPRUFI7March 2009

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Contents
Preface ........................................................................................................................................ 51 Features .............................................................................................................................. 81.1 Block Diagram ............................................................................................................. 81.2 Industry Compliance Statement ......................................................................................... 92 Peripheral Architecture ......................................................................................................... 92.1 Clock Control .............................................................................................................. 92.2 Signal Descriptions ....................................................................................................... 92.3 Functional Operation ..................................................................................................... 92.4 Reset Considerations ................................................................................................... 102.5 Interrupt Support ......................................................................................................... 102.6 EDMA Event Support ................................................................................................... 112.7 Power Management ..................................................................................................... 112.8 Emulation Considerations .............................................................................................. 113 Registers ........................................................................................................................... 113.1 ADCTL ................................................................................................................... 123.2 CMPTGT .................................................................................................................. 133.3 CMPLDAT ................................................................................................................ 133.4 CMPUDAT ................................................................................................................ 143.5 SETDIV ................................................................................................................... 143.6 CHSEL .................................................................................................................... 143.7 AD0DAT .................................................................................................................. 153.8 AD1DAT .................................................................................................................. 153.9 AD2DAT .................................................................................................................. 163.10 AD3DAT .................................................................................................................. 163.11 AD4DAT .................................................................................................................. 163.12 AD5DAT .................................................................................................................. 173.13 EMUCTRL ................................................................................................................ 17
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List of Figures
1 ADC IF Block Diagram ...................................................................................................... 82 ADC Control (ADCTL) Register .......................................................................................... 123 Comparator Target Channel (CMPTGT) Register ..................................................................... 134 Comparison A/D Lower Data (CMPLDAT) Register ................................................................... 135 Comparison A/D Upper Data (CMPUDAT) Register .................................................................. 146 Setup Divide Value for Start A/D (SETDIV) Register .................................................................. 147 Analog Input Channel Select (CHSEL) Register ....................................................................... 158 A/D Conversion Data 0 (AD0DAT) Register ............................................................................ 159 A/D Conversion Data 1 (AD1DAT) Register ............................................................................ 1510 A/D Conversion Data 2 (AD2DAT) Register ............................................................................ 1611 A/D Conversion Data 3 (AD3DAT) Register ............................................................................ 1612 A/D Conversion Data 4 (AD4DAT) Register ............................................................................ 1613 A/D Conversion Data 5 (AD5DAT) Register ............................................................................ 1714 Emulation Control (EMUCTRL) Register ................................................................................ 17
List of Tables
1 ADC interface Memory Map Registers .................................................................................. 112 ADC Control (ADCTL) Field Descriptions ............................................................................... 123 Comparator Target Channel (CMPTGT) Field Descriptions .......................................................... 134 Comparison A/D Lower Data (CMPLDAT) Field Descriptions ....................................................... 135 Comparison A/D Upper Data (CMPUDAT) Field Descriptions ....................................................... 146 Setup Divide Value for Start A/D (SETDIV) Field Descriptions ...................................................... 147 CHSEL setting for Channel selection .................................................................................... 158 Analog Input Channel Select (CHSEL) Field Descriptions ........................................................... 159 A/D Conversion Data 0 (AD0DAT) Field Descriptions ................................................................ 1510 A/D Conversion Data 1 (AD1DAT) Field Descriptions ................................................................ 1611 A/D Conversion Data 2 (AD2DAT) Field Descriptions ................................................................ 1612 A/D Conversion Data 3 (AD3DAT) Field Descriptions ................................................................ 1613 A/D Conversion Data 4 (AD4DAT) Field Descriptions ................................................................ 1714 A/D Conversion Data 5 (AD5DAT) Field Descriptions ................................................................ 1715 Emulation Control (EMUCTRL) Field Descriptions .................................................................... 17
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Preface
SPRUFI7 – March 2009
Read This First
About This Manual
This document describes the analog-to-digital converter (ADC) interface peripheral in the TMS320DM36xDigital Media System-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM36x Digital Media System-on-Chip (DMSoC). Copies ofthese documents are available on the internet at www.ti.com .
SPRUFG5 —TMS320DM36x Digital Media System-on-Chip (DMSoC) ARM Subsystem Users GuideThis document describes the ARM Subsystem in the TMS320DM36x Digital Media System-on-Chip(DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of thedevice. In general, the ARM is responsible for configuration and control of the device; including thecomponents of the ARM Subsystem, the peripherals, and the external memories.
SPRUFG8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Front End(VPFE) Users Guide This document describes the Video Processing Front End (VPFE) in theTMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFG9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Back End(VPBE) Users Guide This document describes the Video Processing Back End (VPBE) in theTMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide Thisdocument describes the operation of the software-programmable 64-bit timers in theTMS320DM36x Digital Media System-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are usedas general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchainedmode, or dual 32-bit chained mode; Timer 2 is used only as a watchdog timer. The GP timer modescan be used to generate periodic interrupts or enhanced direct memory access (EDMA)synchronization events and Real Time Output (RTO) events (Timer 3 only). The watchdog timermode is used to provide a recovery mechanism for the device in the event of a fault condition, suchas a non-exiting code loop.
SPRUFH1 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI)Users Guide This document describes the serial peripheral interface (SPI) in the TMS320DM36xDigital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/outputport that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out ofthe device at a programmed bit-transfer rate. The SPI is normally used for communication betweenthe DMSoC and external peripherals. Typical applications include an interface to external I/O orperipheral expansion via devices such as shift registers, display drivers, SPI EPROMs andanalog-to-digital converters.
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Related Documentation From Texas Instruments www.ti.com
SPRUFH2 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal AsynchronousReceiver/Transmitter (UART) Users Guide This document describes the universal asynchronousreceiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip(DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from aperipheral device, and parallel-to-serial conversion on data received from the CPU.
SPRUFH3 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C)Peripheral Users Guide This document describes the inter-integrated circuit (I2C) peripheral in theTMS320DM36x Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interfacebetween the DMSoC and other devices compliant with the I2C-bus specification and connected byway of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receiveup to 8-bit wide data to and from the DMSoC through the I2C peripheral. This document assumesthe reader is familiar with the I2C-bus specification.
SPRUFH4 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Memory Stick Controller UsersGuide This document This document describes the memory stick controller in the TMS320DM36xDigital Media System-on-Chip (DMSoC). Memory Stick cards are used in a number of applicationsto provide removable data storage. The memory stick controller provides an interface to externalMemory Stick cards. The communication between the controller and the cards is performed by theMemory Stick protocol.
SPRUFH5 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/SecureDigital (SD) Card Controller Users Guide This document describes the multimedia card(MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media System-on-Chip(DMSoC). The MMC/SD card is used in a number of applications to provide removable datastorage. The MMC/SD controller provides an interface to external MMC and SD cards. Thecommunication between the MMC/SD controller and MMC/SD card(s) is performed by the MMC/SDprotocol.
SPRUFH6 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM)Users Guide This document describes the pulse-width modulator (PWM) peripheral in theTMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH7 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) ControllerUsers Guide This document describes the Real Time Out (RTO) controller in the TMS320DM36xDigital Media System-on-Chip (DMSoC).
SPRUFH8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output(GPIO) Users Guide This document describes the general-purpose input/output (GPIO) peripheralin the TMS320DM36x Digital Media System-on-Chip (DMSoC). The GPIO peripheral providesdedicated general-purpose pins that can be configured as either inputs or outputs. When configuredas an input, you can detect the state of the input by reading the state of an internal register. Whenconfigured as an output, you can write to an internal register to control the state driven on theoutput pin.
SPRUFH9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB)Controller Users Guide This document describes the universal serial bus (USB) controller in theTMS320DM36x Digital Media System-on-Chip (DMSoC). The USB controller supports datathroughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devicesand also supports host negotiation.
SPRUFI0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct MemoryAccess (EDMA) Controller Users Guide This document describes the operation of the enhanceddirect memory access (EDMA3) controller in the TMS320DM36x Digital Media System-on-Chip(DMSoC). The EDMA controller's primary purpose is to service user-programmed data transfersbetween two memory-mapped slave endpoints on the DMSoC.
SPRUFI1 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External MemoryInterface (EMIF) Users Guide This document describes the asynchronous external memoryinterface (EMIF) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The EMIF supportsa glueless interface to a variety of external devices.
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www.ti.com Related Documentation From Texas Instruments
SPRUFI2 —TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR(DDR2/mDDR) Memory Controller Users Guide This document describes the DDR2/mDDRmemory controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). TheDDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2SDRAM and mobile DDR devices.
SPRUFI3 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Multibuffered Serial PortInterface (McBSP) User's Guide This document describes the operation of the multibuffered serialhost port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The primaryaudio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to theprimary audio modes, the McBSP supports general serial port receive and transmit operation.
SPRUFI4 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Host Port Interface(UHPI) User's Guide This document describes the operation of the universal host port interface inthe TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFI5 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media AccessController (EMAC) User's Guide This document describes the operation of the ethernet mediaaccess controllerface in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
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1 Features
1.1 Block Diagram
32-bit Peripheral bus
ADC
Timing and channel
controller
Comparator
CMPUDATA
Interrupt to CPU
CMPTGT
CMPLDATA
Interrupt
controller
10-bit
Analog-to-digital
converter
6 to 1 Analog input
selector
ADC_CH0
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
ADC_CH5
ADCTL
AD1DAT
AD2DAT
AD4DAT
AD3DAT
AD5DAT
AD0DAT
SETDIV
CHSEL
EMUCTRL
SPRUFI7-001
User's GuideSPRUFI7 – March 2009
Analog to Digital Converter (ADC) Interface
DM36x has a 6-channel, 10-bit analog-to-digital converter (ADC) interface. The CPU communicates to theADC interface using 32-bit-wide control registers accessible via the internal peripheral bus.
The DM36x ADC interface has following features:•Supports six configurable analog Input•Supports for successive approximation type 10-bit, A-D converter•Programmable sampling / conversion time (base clock is AUXCLK)•Supports channel select by auto scan conversion•Supports mode select by one-shot mode or free-run mode•Programmable setup (Idle) period to secure A/D sampling start time•Supports the clock stop signals to connect the PSC
Figure 1 shows the data path and control path of ADC interface.
Figure 1. ADC IF Block Diagram
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1.2 Industry Compliance Statement
2 Peripheral Architecture
2.1 Clock Control
2.2 Signal Descriptions
2.3 Functional Operation
2.3.1 One-Shot Mode Operation
www.ti.com Peripheral Architecture
The ADC interface does not conform to any recognized industry standards.
The ADC interface is driven by the auxiliary clock of the PLL controller. The frequency of the auxiliaryclock is equal to the input reference clock of the PLL controller, and therefore is not affected by themultiplier and divider values of the PLL controller. For more information on device clocking, refer to theTMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (SPRUFG5 ).
The ADC interface receives analog inputs on six separate pins: ADC_CH [5:0]. Refer to theTMS320DM365 Digital Media System-on-Chip Data Manual (SPRS457 ) for more information on thesepins.
The ADC interface can operate in either one-shot mode or free-run mode. In both modes, the ADCperipheral has a Comparison A/D Lower data register (CMPLDAT) and a Comparison A/D Upper dataregister (CMPUDAT) to specify, respectively, the lower and upper data for comparison. The analog inputchannel to be used for scan conversion can be configured using the CHSEL registers and on theCMPTGT register, set the analog input data to be the target of comparator. For one-shot mode operation,see Section 2.3.1 ; for Free-Run mode operation, see Section 2.3.2 .
In one-shot mode operation, the ADC interface does not run continuously and A/D conversion terminateswhen scanning is completed.
For one-shot mode operation, the ADC interface should first be configured for scan mode (SCNMD) andcomparator mode (CMPMD) in ADC interface control register (ADCTL), along with other configurationoptions. The ADC interface sets the BUSY bit in ADCTL once it is started by writing a 1 to the START bitin the ADCTL register
Once started, the ADC interface genertaes the output after A/D conversion time. A/D conversion time isobtained by Analog switch setup time + ADC setup time + A/D conversion time.•Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2•ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2•A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24
When the A/D scan conversion is finished for all channels, the peripheral sends an interrupt to the system(if the interrupt is enabled in ADCTL register). The START bit will cleared automatically when A/Dconversion in One-Shot mode terminates. The ADC interface then becomes inactive until the START bit iswritten a 1 again.
The ADC Interface is stopped during one-shot mode operation by changing the START bit to 0 in ADCTL.After START bit turns to '0', it will be stop at the completion of current sample conversion. If user changeconfiguration, then user need to wait at least a time which defined by SETDIV register after writing '0' intoSTART bit.
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2.3.2 Free-Run Mode Operation
2.4 Reset Considerations
2.4.1 Software Reset Considerations
2.4.2 Hardware Reset Considerations
2.5 Interrupt Support
2.5.1 Interrupt Events and Requests
2.5.2 Interrupt Multiplexing
Peripheral Architecture www.ti.com
In free-run mode operation, the ADC interface performs A/D conversion continuously without stopping.
For free-run mode operation, the ADC interface should first be configured for scan mode(SCNMD), andcomparator mode (CMPMD) in ADC interface control register (ADCTL), along with other configurationoptions. The ADC interface sets the BUSY bit in ADCTL once it is started by writing a 1 to the START bitin the ADCTL register.
Once started, the ADC interface genertaes the output after A/D conversion time. A/D conversion time isobtained by Analog switch setup time + ADC setup time + A/D conversion time.•Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2•ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2•A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24
When the A/D scan conversion is finished for all channels, the peripheral sends an interrupt to the system(if the interrupt is enabled in ADCTL register). Note that unlike normal one-shot mode operation, anotherwrite to the START bit is not required for the one-shot mode operation to start.Once A/D conversion of allthe channels is finished A/D conversion re-start from CH0.
The ADC interface is stopped during the free-run mode operation by writing '0' into START bit. AfterSTART bit turns to '0', it will be stop at the completion of current sample conversion. If user changeconfiguration, then user need to wait at least a time which defined by SETDIV register after writing '0' intoSTART bit. The ADC interface can also stopped during the free-run mode operatioor by reconfiguring it toone-shot mode using the SCNMD bit in ADCTL register.
A software reset (such as a reset generated by the emulator) causes the ADC interface registers to returnto their default state after reset.
A hardware reset of the processor causes the ADC interface registers to return to their default values afterreset.
The ADC interface generates a single pulse interrupt. This interrupt is tied directly to the AINTC. ADCinterface generates Scan Interrupt to CPU when A/D scan conversion is finished for all channels once.
The cause of comparator interrupt is selected according to the CMPMD bit in ADCTL register. A singlecommon comparative data window has provided for every individual channel. Depending on theComparator mode selected an interrupt occurs after the A/D conversion in each channel for either of thefollowing condition.•Conversion data is out of the range of the comparative data window•Conversion data is within the range of the comparative data window
The ADC interface is supported by the ARM Interrupt Controller (AINTC) module. The ARM_INTMUXregister in the system control module must be used to select the interrupt source for multiplexed interrupts.In particular, the ADC interface interrupt is multiplexed with other interrupts. Refer to the TMS320DM365Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (SPRUFG5 ) for moreinformation on the System Control Module and ARM Interrupt Controller.
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2.6 EDMA Event Support
2.7 Power Management
2.8 Emulation Considerations
3 Registers
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The ADC interface module does not generate an EDMA event.
The ADC interface can be placed in reduced-power modes to conserve power during periods of lowactivity. Power management of the ADC Interface is controlled by the power and sleep controller (PSC)processor. The PSC acts as a master controller for power management for all of the peripherals on thedevice. For detailed information on power management procedures using the PSC, see theTMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (SPRUFG5 )
ADC interface supports the emulation suspend function. At the enable emulator suspend, this modulekeep the following condition and restart.•Stop after a A-D convert•Bus access is available under the suspend time•Restart with the setting condition after the suspend time
Table 1 lists the memory-mapped registers for the analog-to-digital Controller (ADC) interface. See thedevice-specific data manual for the memory address of these registers
Table 1. ADC interface Memory Map Registers
Offset Register Description Location
0x0 ADCTL Control register Section 3.10x4 CMPTGT Comparator target channel Section 3.20x8 CMPLDAT Comparison A/D Lower data Section 3.30xC CMPUDAT Comparison A/D Upper data Section 3.40x10 SETDIV SETUP divide value for start Section 3.5A/D conversion0x14 CHSEL Analog Input channel select Section 3.60x18 AD0DAT A/D conversion data 0 Section 3.70x1C AD1DAT A/D conversion data 1 Section 3.80x20 AD2DAT A/D conversion data 2 Section 3.90x24 AD3DAT A/D conversion data 3 Section 3.100x28 AD4DAT A/D conversion data 4 Section 3.110x2C AD5DAT A/D conversion data 5 Section 3.120x30 EMUCTRL Emulation Control Section 3.13
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3.1 ADCTL
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The ADC control register (ADCTL) is shown in Figure 2 and described in Table 2 .
Figure 2. ADC Control (ADCTL) Register
31 24Reserved
R-0
23 16
Reserved
R-0
15 8
Reserved
R-0
76543210
BUSY CMPFLG CMPIEN CMPMD SCNFLG SCNIEN SCNMD STARTR-0 R/C-0 R/W-0 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 2. ADC Control (ADCTL) Field Descriptions
Bit Field Value Description
31-8 Reserved Any writes to these bit(s) must always have a value of 0.7 BUSY Busy flag6 CMPFLG Comparator interrupt flag clear bit. Writing ‘1’ into this bit clears the comparator interrupt flag andthen it will be cleared automatically. At read time, comparator interrupt status can be read.0 No interrupt1 Interrupt5 CMPIEN Comparator interrupt enable bit0 Disable
1 Enable4 CMPMD Comparator mode select bit0 If the value of A/D input data is larger or smaller than the comparative data, a comparator interruptis generated. ADC input data < CMPLDAT or ADC input data > CMPUDAT1 If the value of A/D input data is within the range of the comparative data, a comparator interrupt isgenerated. CMPLDAT ≤ADC input data ≤CMPUDAT3 SCNFLG Scan interrupt flag clear bit. Writing '1' into this bit clears the scan interrupt flag then it will becleared automatically. At read time, scan interrupt status can be read.0 No interrupt1 Interrupt2 SCNIEN Scan interrupt enable bit0 Disable
1 Enable1 SCNMD Scan mode selection0 One shot1 Free run0 START A/D conversion start bit The status is cleared automatically when A/D conversion in One-Shot modeterminates. Writing '0' into this bit in Free-Run mode terminates A/D conversion.'0' can be read atthe time of read-access if no analog channel is selected on the CHSEL register. ('1' can be readonly at the time of A/D conversion.)
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3.2 CMPTGT
3.3 CMPLDAT
www.ti.com Registers
The comparator target channel (CMPTGT) register is shown in Figure 3 and described in Table 3 .
Figure 3. Comparator Target Channel (CMPTGT) Register
31 6 5 0Reserved CMPTGTR-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 3. Comparator Target Channel (CMPTGT) Field Descriptions
Bit Field Value Description
31-6 Reserved 1 0 Any writes to these bit(s) must always have a value of 0.5-0 CMPTGT Comparator target channel at A/D conversion The analog input that has written ‘1’ into CMPTGT isthe target of the comparator.
The comparison A/D lower data (CMPLDAT) register is shown in Figure 4 and described in Table 4 .
Figure 4. Comparison A/D Lower Data (CMPLDAT) Register
31 10 9 0Reserved CMPLDATR-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 4. Comparison A/D Lower Data (CMPLDAT) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Any writes to these bit(s) must always have a value of 0.9-0 CMPLDAT Comparative data (lower) value of CMPLDAT should be the same as or smaller than that ofCMPUDAT.
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3.4 CMPUDAT
3.5 SETDIV
3.6 CHSEL
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The comparison A/D Upper data (CMPUDAT) register is shown in Figure 5 and described in Table 5 .
Figure 5. Comparison A/D Upper Data (CMPUDAT) Register
31 10 9 0Reserved CMPUDATR-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 5. Comparison A/D Upper Data (CMPUDAT) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Any writes to these bit(s) must always have a value of 0.9-0 CMPUDAT Comparativer data (upper) value of CMPUDAT should be the same as or larger than that ofCMPLDAT.
The SETUP divide value for start A/D conversion (SETDIV) register is shown in Figure 6 and described inTable 6 .
A/D conversion time is obtained by Analog switch setup time + ADC setup time + A/D conversion time.Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24.
Note: A/D conversion time can't be less than 6us.
Figure 6. Setup Divide Value for Start A/D (SETDIV) Register
31 16Reserved
R-0
15 0
SETDIV
R/W-0xFFFF
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 6. Setup Divide Value for Start A/D (SETDIV) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Any writes to these bit(s) must always have a value of 0.15-0 SETDIV SETDIV bits set the Analog switch setup time, ADC setup (Idle) time and A/D conversion time.Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24.
The analog Input channel select (CHSEL) register is shown in Figure 7 and described in Table 8 . CHSELsetting for the selection of different channel is shown in Table 7 . In order to select two or more channels,ORing of these setting is needed.
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3.7 AD0DAT
3.8 AD1DAT
www.ti.com Registers
Table 7. CHSEL setting for Channel selection
CHSEL Selected Channel
000001b Channel 0000010b Channel 1000100b Channel 2001000b Channel 3010000b Channel 4100000b Channel 5
Figure 7. Analog Input Channel Select (CHSEL) Register
31 6 5 0Reserved CHSELR-0 R/W-0x3F
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 8. Analog Input Channel Select (CHSEL) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Any writes to these bit(s) must always have a value of 0.5-0 CHSEL A/D conversion select bit0 Analog Input unselected1 Analog Input selected
The A/D conversion data 0 (AD0DAT) register is shown in Figure 8 and descried in Table 9 .
Figure 8. A/D Conversion Data 0 (AD0DAT) Register
31 10 9 0Reserved AD0DATR-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 9. A/D Conversion Data 0 (AD0DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.9-0 AD0DAT A/D conversion data for channel 0
The A/D conversion data 1 (AD1DAT) register is shown in Figure 9 and described in Table 10 .
Figure 9. A/D Conversion Data 1 (AD1DAT) Register
31 10 9 0Reserved AD1DATR-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
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3.9 AD2DAT
3.10 AD3DAT
3.11 AD4DAT
Registers www.ti.com
Table 10. A/D Conversion Data 1 (AD1DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.9-0 AD1DAT A/D conversion data for channel 1
The A/D conversion data 2 (AD2DAT) register is shown in Figure 10 and described in Table 11 .
Figure 10. A/D Conversion Data 2 (AD2DAT) Register
31 10 9 0Reserved AD2DATR-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 11. A/D Conversion Data 2 (AD2DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.9-0 AD2DAT A/D conversion data for channel 2
The A/D conversion data 3 (AD3DAT) register is shown in Figure 11 and described in Table 12 .
Figure 11. A/D Conversion Data 3 (AD3DAT) Register
31 10 9 0Reserved AD3DATR-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 12. A/D Conversion Data 3 (AD3DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.9-0 AD3DAT A/D conversion data for channel 3
The A/D conversion data 4 (AD4DAT) register is shown in Figure 12 and described in Table 13 .
Figure 12. A/D Conversion Data 4 (AD4DAT) Register
31 10 9 0Reserved AD4DATR-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
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3.12 AD5DAT
3.13 EMUCTRL
www.ti.com Registers
Table 13. A/D Conversion Data 4 (AD4DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.9-0 AD4DAT A/D conversion data for channel 4
The A/D conversion data 5 (AD5DAT) register is shown in and described in .
Figure 13. A/D Conversion Data 5 (AD5DAT) Register
31 10 9 0Reserved AD5DATR-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 14. A/D Conversion Data 5 (AD5DAT) Field Descriptions
Bit Field Value Description
31-10 Reserved Any writes to these bit(s) must always have a value of 0.9-0 AD5DAT A/D conversion data for channel 5
The emulation control (EMUCTRL) register is shown in Figure 14 and described in Table 15 .
Figure 14. Emulation Control (EMUCTRL) Register
31 16Reserved
R-0
15 3 2 1 0
Reserved RT_SEL SOFT FREER-0 R-0 R-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; - n= value after reset
Table 15. Emulation Control (EMUCTRL) Field Descriptions
Bit Field Value Description
31-2 Reserved Any writes to these bit(s) must always have a value of 0.2 RT_SEL 0 Support only emulation suspend1 SOFT Support only soft stop1 Soft stop: Stop peripheral operations gracefully at the earliest opportunity after the currentapplication specific processing task is completed.0 FREE This bit controls whether or not the peripheral will respond to the emulation suspend signal that ithas been programmed to monitor0 Peripheral suspends according to mode specified by the SOFT bit1 Peripheral ignores suspend and operates normally
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