Texas Instruments LDC3114 User manual

LDC3114 4-Channel Hybrid Inductive Touch and Inductance to Digital Converter
1 Features
• Multiple modes of operation:
– Raw data mode: access pre-processed
inductance measurement data to enable
advanced algorithms on MCU for linear sensing
– Button mode: button press detection with
baseline tracking and advanced on-chip post
processing
– Force level measurement of touch buttons
• Pin and register compatible to LDC2114
• Robust EMI performance allows for CISPR 22 and
CISPR 24 compliance
• Four independent channel operation
• Configurable scan rates:
– 0.625 SPS to 160 SPS
– Continuous scanning option
• Advanced button press detection algorithms:
– Adjustable force threshold per button
– Environmental shift compensation
– Simultaneous button press detection
• Low current consumption:
– One button: 6 µA at 0.625 SPS
– Two buttons: 72 µA at 20 SPS
• Temperature range
– TSSOP (16) : –40°C to +125°C
• Interface:
– 1.8-V and 3.3-V compliant I2C and INTB
– 1.8-V logic output per channel for buttons
2 Applications
• Consumer Electronics:
– Wearables
– Smart Speakers
– Sound Bars
• Industrial Applications:
– HMI Panels and Keypads
– Home Appliances
3 Description
The LDC3114 is an inductive sensing device that
enables touch button design for human machine
interface (HMI) on a wide variety of materials by
measuring small deflections of conductive targets
using a coil that can be implemented on a small
printed circuit board (PCB) located behind the panel.
This technology can be used for precise linear
position sensing of metal targets for automotive,
consumer and industrial applications by allowing
access to the raw data representing the inductance
value. Inductive sensing solution is insensitive to
humidity or non-conductive contaminants such as oil
and dirt.
The button mode of LDC3114 is able to automatically
correct for any deformation in the conductive targets.
The LDC3114 offers well-matched channels, which
allow for differential and ratiometric measurements
which enable compensation of environmental and
aging conditions such as temperature and mechanical
drift. The LDC3114 includes an ultra-low power mode
intended for power on/off buttons or position sensors
in battery powered applications.
The LDC3114 is easily configured through an I2C
interface. The LDC3114 is available in a 16-pin
TSSOP package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LDC3114 TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Inductive
Sensing Core
IN0
LP Mode &
Data
Processing
GND
SCL
SDA
I2C
LPWRB
IN3
COM
Digital
Button Press
Algorithm
VDD
Resonant
Circuit
Driver
OUT0
IN1
IN2
OUT1
OUT2
OUT3
Raw Data
& Config
INTB
3.3 V
LDC3114 Simplified Schematic
LDC3114
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................4
6.6 Digital Interface........................................................... 5
6.7 I2C Interface................................................................6
6.8 Timing Diagram...........................................................6
6.9 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................14
7.5 Register Maps...........................................................15
8 Application and Implementation.................................. 37
8.1 Application Information............................................. 37
8.2 Typical Application.................................................... 48
9 Power Supply Recommendations................................51
10 Layout...........................................................................51
10.1 Layout Guidelines................................................... 51
10.2 Layout Example...................................................... 51
11 Device and Documentation Support..........................52
11.1 Documentation Support.......................................... 52
11.2 Receiving Notification of Documentation Updates.. 52
11.3 Support Resources................................................. 52
11.4 Trademarks............................................................. 52
11.5 Electrostatic Discharge Caution.............................. 52
11.6 Glossary.................................................................. 52
12 Mechanical, Packaging, and Orderable
Information.................................................................... 52
4 Revision History
DATE VERSION NOTES
December 2021 * Initial release.
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5 Pin Configuration and Functions
LPWRB SDA
OUT1
OUT0
SCLCOM
GND
GND
OUT2
OUT3
INTB
IN3
VDD
IN2
IN1 IN0
3
4
5
6
7
8 9
10
11
12
13
14
15
161
2
Figure 5-1. LDC3114 PW Package 16-Pin TSSOP Top View
Table 5-1. Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
VDD 4 P Power supply
GND 2G Ground(2)
10
INTB 5 O Interrupt output
Polarity can be configured in Register 0x11.
LPWRB 3 I Normal / Low Power Mode select
Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode.
COM 1 A
Common return current path for all LC resonator sensors
A capacitor should be connected from this pin to GND. Refer to Setting COM Pin
Capacitor.
IN0 9 A Channel 0 LC sensor input
IN1 8 A Channel 1 LC sensor input
IN2 7 A Channel 2 LC sensor input
IN3 6 A Channel 3 LC sensor input
OUT0 15 O Channel 0 logic output
Polarity can be configured in Register 0x1C.
OUT1 13 O Channel 1 logic output
Polarity can be configured in Register 0x1C.
OUT2 12 O Channel 2 logic output
Polarity can be configured in Register 0x1C.
OUT3 11 O Channel 3 logic output
Polarity can be configured in Register 0x1C.
SCL 16 I I2C clock
SDA 14 I/O I2C data
I2C address = 0x2A.
(1) I = Input, O = Output, P=Power, G=Ground, A=Analog
(2) Both pins should be connected to the system ground on the PCB.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating temperature range unless otherwise noted.(1)
MIN MAX UNIT
VDD Supply voltage 2.2 V
VI
Voltage on SCL, SDA. INTB –0.3 3.6 V
Voltage on any other pin –0.3 2.2(2) V
TJJunction temperature –40 135 ℃
TSTG Storage temperature –65 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Maximum voltage across any two pins (not including SCL or SDA) is VDD + 0.3 V.
6.2 ESD Ratings
VALUE UNIT
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating temperature range unless otherwise noted.
MIN NOM MAX UNIT
VDD Supply voltage 1.71 1.89 V
TAAmbient temperature (TSSOP Package) –40 125 °C
6.4 Thermal Information
THERMAL METRIC(1)
LDC3114
UNITTSSOP
16 PINS
RθJA Junction-to-ambient thermal resistance 105.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 40.3 °C/W
RθJB Junction-to-board thermal resistance 50.2 °C/W
ΨJT Junction-to-top characterization parameter 3.6 °C/W
ΨJB Junction-to-board characterization parameter 49.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over operating temperature range unless otherwise noted.
Over operating VDD range unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
VDD Supply voltage 1.71 1.8 1.89 V
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Over operating temperature range unless otherwise noted.
Over operating VDD range unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDDNP
Normal power mode supply
current (4 channels)(1) (2)
4 channels, 40 SPS per channel,
1 ms sampling window per channel,
LPWRB = VDD
-40℃ ≤ TA ≤ 125℃
0.46 2 mA
Normal power mode supply
current (2 channels)(1) (2)
2 channels, 40 SPS per channel,
1 ms sampling window per channel,
LPWRB = VDD
-40℃ ≤ TA ≤ 125℃
0.31 1 mA
IDDLP
Low power mode supply current (1)
(2)
1 channel, 1.25 SPS per channel,
1 ms sampling window per channel,
LPWRB = Ground
-40℃ ≤ TA ≤ 125℃
10 35 µA
IDDSB Standby supply current No button active (EN = 0x00)
-40℃ ≤ TA ≤ 125℃7 22 µA
SENSOR
ISENSOR, MAX Maximum sensor current drive Registers SENSORn_CONFIG: RPn =
0(3) 2.5 mA
RP, MIN
Minimum sensor parallel resonant
impedance 350 Ω
RP, MAX
Maximum sensor parallel resonant
impedance 10 kΩ
f SENSOR Sensor resonant frequency(4) 5 30 MHz
QSENSOR, MIN Minimum sensor quality factor 5
QSENSOR, MAX Maximum sensor quality factor 30
VSENSOR, PP
Sensor oscillation peak-to-peak
voltage
Measured on the INn (3) pins with
reference to COM. 0.9 V
CIN Sensor input pin capacitance 17 pF
CONVERTER
SRNP, MIN
Minimum normal power mode scan
rate(5) LPWRB = VDD 7 10 13 SPS
SRNP, MAX
Maximum normal power mode scan
rate(5) LPWRB = VDD 56 80 104 SPS
SRLP, MIN
Minimum low power mode scan
rate(5) LPWRB = Ground 0.438 0.625 0.813 SPS
SRLP, MAX
Maximum low power mode scan
rate(5) LPWRB = Ground 3.5 5 6.5 SPS
fREF_CLK Internal Reference clock frequency TA=25℃44 MHz
fREF_CLK_TC
Internal Reference clock frequency
variation from TA=25℃ to over
temperature
-40℃ ≤ TA ≤ 125℃3 %
(1) Sensor configuration: LSENSOR = 0.85 µH, CSENSOR = 58 pF, QSENSOR = 11, RP = 0.7 kΩ.
(2) I2C communication and pull-up resistors current is not included.
(3) The italic n is the channel index, n = 0, 1, 2, or 3 for LDC3114.
(4) For optimal performance, configure the sensor frequency to be greater than 3 MHz
(5) For typical distribution of the scan rates, refer to Figure 6-9.
6.6 Digital Interface
Over operating temperature range unless otherwise noted. Pins: LPWRB, INT_DR, OUT0, OUT1, OUT2, OUT3, and ADDR.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE LEVELS
VIH Input high voltage, LPWRB pin 0.8 × VDD V
VIL Input low voltage, LPWRB pin 0.2 × VDD V
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Over operating temperature range unless otherwise noted. Pins: LPWRB, INT_DR, OUT0, OUT1, OUT2, OUT3, and ADDR.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output high voltage, OUTx pins ISOURCE = 400 µA 0.8 × VDD V
VOL Output low voltage, OUTx pins ISINK = 400 µA 0.2 × VDD V
ILDigital input leakage current –500 500 nA
VOL_INTB Output low voltage, INTB pin 3 mA sink current 0.4 V
6.7 I2C Interface
MIN TYP MAX UNIT
VOLTAGE LEVELS
VIH_I2C Input high voltage 0.7 × VDD V
VIL_I2C Input low voltage 0.3 × VDD V
VOL_I2C Output low voltage 3 mA sink current 0.2 × VDD V
HYSI2C Hysteresis 0.05 × VDD V
I2C TIMING CHARACTERISTICS
fSCL Clock frequency 400 kHz
tLOW Clock low time 1.3 µs
tHIGH Clock high time 0.6 µs
tHD;STA Hold time repeated START condition After this period, the first
clock pulse is generated. 0.6 µs
tSU;STA
Set-up time for a repeated START
condition 0.6 µs
tHD;DAT Data hold time 0 µs
tSU;DAT Data set-up time 100 ns
tSU;STO Set-up time for STOP condition 0.6 µs
tBUF
Bus free time between a STOP and
START condition 1.3 µs
tVD;DAT Data valid time 0.9 µs
tVD;ACK Data valid acknowledge time 0.9 µs
tSP
Pulse width of spikes that must be
suppressed by the input filter(1) 50 ns
(1) This parameter is specified by design and/or characterization and is not tested in production.
6.8 Timing Diagram
SCL
SDA
tHD;STA
tLOW
tr
tHD;DAT
tHIGH
tf
tSU;DAT
tSU;STA tSU;STO
tf
START REPEATED
START
STOP
tHD;STA
START
tSP
tr
tBUF
Figure 6-1. I2C Timing Diagram
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6.9 Typical Characteristics
Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25°C. One channel enabled with a
button sampling window of 1 ms unless specified otherwise.
Figure 6-2. Supply Current vs Sensor RP for Normal Power
Mode. Sensor Frequency = 10 MHz. Sampling Window = 2mS.
Four Channels Enabled.
Figure 6-3. Supply Current vs Sensor RP for Normal Power
Mode. Sensor Frequency = 10 MHz. Sampling Window = 2mS.
Two Channels Enabled.
Figure 6-4. Supply Current vs Sensor RP for Low Power Mode.
Sensor Frequency = 10 MHz.
Figure 6-5. Supply Current vs Temperature. Sensor RP = 720 Ω,
Scan Rate = 40 SPS, Sensor Frequency = 20 MHz.
Figure 6-6. Supply Current vs. VDD. Sensor RP = 720 Ω, Scan
Rate = 40 SPS, Sensor Frequency = 20 MHz. Figure 6-7. Standby Current vs. Temperature
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6.9 Typical Characteristics (continued)
Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25°C. One channel enabled with a
button sampling window of 1 ms unless specified otherwise.
Figure 6-8. Standby Current vs VDD
Percentage Offset ()
Occurrences
0
50
100
150
200
250
300
350
400
450
-12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4
D007
Figure 6-9. Scan Rate Distribution at 30°C
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7 Detailed Description
7.1 Overview
The LDC3114 is a hybrid multichannel, low-noise, high-resolution inductance-to-digital converter (LDC)
optimized for inductive touch applications as well as linear position sensing. Button presses form micro-
deflections in the conductive targets which cause frequency shifts in the resonant sensors. The LDC3114 can
measure such frequency shifts and determine when button presses occur. With adjustable sensitivity per input
channel, the LDC3114 can reliably operate with a wide range of physical button structures and materials. The
high resolution measurement enables the implementation of force level buttons. The LDC3114 incorporates
customizable post-processing algorithms for enhanced robustness.
The LDC3114 additionally implements a raw data access mode. The MCU can read directly the data
representing the effective inductance of the sensor and implement further post processing. In this mode,
additional post processing features such as baseline tracking and algorithms for false button detection are
ignored. This mode is useful for linear or rotary position sensing with inductive sensors while having excellent
EMI performance across wide range of applications. This mode can also be used to measure the micro-
deflection for button-like applications as well.
The LDC3114 can operate in an ultra-low power mode for optimal battery life, or can be toggled into a higher
scan rate for more responsive button press detection for game play or other low latency applications. The
LDC3114 is operational from –40°C to +125°C with a 1.8 V ± 5% power supply voltage.
The LDC3114 is configured through 400-kHz I2C. Button presses can be reported through the I2C interface
or with configurable polarity dedicated push-pull outputs. Besides the LC resonant sensors, the only external
components necessary for operation are supply bypassing capacitors and a COM pin capacitor to ground.
7.2 Functional Block Diagram
Inductive
Sensing Core
IN0
LP Mode &
Data
Processing
GND
SCL
SDA
I2C
LPWRB
IN3
COM
Digital
Button Press
Algorithm
VDD
Resonant
Circuit
Driver
OUT0
IN1
IN2
OUT1
OUT2
OUT3
Raw Data
& Config
INTB
3.3 V
Figure 7-1. Block Diagram of LDC3114
7.3 Feature Description
7.3.1 Multimode Operation
LDC3114 offers two main modes of operations: raw data access mode and button algorithm mode which is
controlled by the BTN_ALG_EN field in Register INTPOL Address 0x11. Figure 7-2 shows conceptually how
these two modes are implemented.
Raw data access mode allows an external MCU to extract data from the signal after the inductance-to-digital
converter from registers through I2C (see Raw Data Output). There is no further processing on this raw data
such as baseline tracking, integrated button algorithms and button thresholding. This mode gives MCU full
control over the measured raw data to implement algorithms for linear position sensing, rotational encoder
applications, metal presence/deflection applications, smart button algorithms and for multimodal sensor fusion
applications.
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The second mode is button algorithm mode. Here further processing with parameters defined by the user (see
Baseline Tracking and Integrated Button Algorithms) is done on the data and a button thresholding as defined
by the user is applied. The processed data are available in separate registers to be read by I2C and any button
press detection is indicated on the OUTx pins (see Button Output Interfaces) This mode is used to implement
button press functionality and can also be used to implement the measurement of force applied for button press
along with detection to implement multilevel button press.
For register settings that are applicable to button mode versus raw access data mode are clearly identified in the
descriptions of the registers (see Register Maps).
L to
Digital
Converter
LC Driver
&
Sampler
Baseline
Tracking
Button
Press
Detection
OUTx, INTB Pins
DATAx Regs
I2C Add: 0x02-0x09
INTB Pin
RAW_DATAx Regs
I2C Add: 0x59-0x64
BTN_ALG_EN=1
BTN_ALG_EN=0
Figure 7-2. Multimode Operation in LDC3114
7.3.2 Multichannel and Single-Channel Operation
The LDC3114 provides four independent sensing channels. In the following sections, some parameters, such as
DATAn and SENSORn_CONFIG, contain a channel index n.
Any of the four channels available in the LDC3114 can be independently enabled by setting the ENn and LPENn
(n = 0, 1, 2, or 3) bit fields in Register EN (Address 0x0C). The low-power-enable bit LPENn only takes effect
if the corresponding ENn bit is also set. If only one channel is set active, the LDC3114 periodically samples the
single active channel at the configured scan rate. When several channels are set active, the LDC3114 operates
in multichannel mode, and the device sequentially samples the active channels at the configured scan rate. Each
channel of the LDC3114 can be independently enabled in Low Power Mode and Normal Power Mode.
7.3.3 Raw Data Output
Raw data mode is enabled by setting BTN_ALG_EN=0x0 field in Register INTPOL Address 0x11. Figure 7-2
shows that this operation will extract data directly from the output of the inductance-to-digital converter.
The data is read from the I2C interface of the LDC3114. The DATA_RDY field in Register OUT (Address 0x01)
indicates when new data is available for reading. In the raw data mode, the INTB pin also assserted when new
data is available and can be used by the MCU as an interrupt. The raw data can be extracted by reading, the
output RAW_DATAn_x registers (n = 0, 1, 2, or 3, for each channel, x= 1, 2, or 3 splitting 24-bit data over 3 8-bit
register fields). Equation 1 shows the relationship between 24-bit data and the sensor frequency.
REF _ CLK
SENSOR
30 W f
fraw _ data
u u
(1)
where:
• fsensor is the instantaneous frequency of the inductive sensor
• fREF_CLK is the internal reference clock frequency as specified in Electrical Characteristics
• raw_data is the decimal representation of 24-bit binary data read from the RAW_DATAn_x for a particular
channel
• W calculated in Equation 2 (see Programming Button or Raw Data Sampling Window for details):
 
LCDIV
W 128 1 SENCY 2u  un
(2)
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7.3.4 Button Output Interfaces
Button events may be reported by using two methods. The first method is to monitor the OUTn pins (n = 0, 1, 2,
or 3), which are push-pull outputs and can be used as interrupts to a microcontroller. The polarities of these pins
are programmable through Register OPOL_DPOL (Address 0x1C). Any button press or error condition is also
reported by the open-drain pin, INTB. The INTB pin polarity is configurable through Register INTPOL (Address
0x11). Any assertion of INTB is cleared upon reading Register STATUS (Address 0x00). Each push-pull output
must be assigned to a dedicated general-purpose input pin on the microcontroller to avoid potential current
fights.
The second method is through the I2C interface. The Register OUT (Address 0x01) contains the fields OUT0,
OUT1, OUT2, and OUT3, which indicate when a button press has been detected. For more advanced button
press measurements, the output DATAn registers (n = 0, 1, 2, or 3, Register DATA0_LSB - Address 0x02), which
are 12-bit two’s complements, can be retrieved for all active buttons, and processed on a microcontroller. A valid
button push is represented by a positive value. The polarity is configurable in Register OPOL_DPOL (Address
0x1C). The DATAn values can be used to implement multilevel buttons, where the data value is correlated to the
amount of force applied to the button.
7.3.5 Programmable Button Sensitivity
The GAINn registers (Addresses 0x0E, 0x10, 0x12, and 0x14) enable sensitivity enhancement of individual
buttons to ensure consistent behavior of different mechanical structures. The sensitivity has a 64-level gain
factor for a normalized gain between 1 and 232. Each gain step increases the gain by an average of 9%.
The gain required for an application is primarily determined by the mechanical rigidity of each individual button.
The individual gain steps are listed in the Gain Table.
7.3.6 Baseline Tracking
The LDC3114 incorporates a baseline tracking algorithm to automatically compensate for any slow change in the
sensor output caused by environmental variations, such as temperature drift. The baseline tracking is configured
independently for Normal Power Mode and Low Power Mode. For more information, refer to Tracking Baseline.
Note
The baseline tracking feature is applicable only for button algorithm functionality and cannot be
bypassed. To disable baseline tracking, LDC3114 must be used in raw data access mode. See
Multimode Operation for details.
7.3.7 Integrated Button Algorithms
The LDC3114 features several algorithms that can mitigate false button detections due to mechanical non-
idealities. The algorithms look for correlated button responses, such as similar or opposite responses between
two neighboring buttons, to determine if there is any undesirable mechanical crosstalk. For more information,
refer to Mitigating False Button Detections.
7.3.8 I2C Interface
The LDC3114 features an I2C Interface that can be used to program the internal registers and read channel
data. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2 or 3, Addresses 0x02 through 0x09)
registers for button press data or raw channel data, RAW_DATAn_x (n = 0, 1, 2, or 3, for each channel, x= 1,
2, or 3 splitting 24-bit data over 3 8-bit register fields), the user should always read Register STATUS (Address
0x00) first to lock the data. The LDC3114 supports burst mode with auto-incrementing register addresses. The
LDC3114 has a fixed I2C address of 0x2A.
For the write sequence, there is a special handshake process that has to take place to ensure data integrity. The
sequence of register writes is:
• Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 1 to start the register write session.
• Poll for RDY_TO_WRITE (Register STATUS, Address 0x00) bit = 1.
• Perform I2C write to configure registers.
• Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 0 to terminate the register write session.
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After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. Figure 7-3 shows the
waveform of the above process.
CONFIG_MODE
RDY_TO_WRITE
25 ms scan cycle
Sampling
25 ms scan cycle
Sampling
(Register STATUS)
(Register RESET)
Program registers only after
confirming RDY_TO_WRITE = 1
< 1 ms
Figure 7-3. Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for
an I2C Write Handshake
Note
The I2C interface pin, the SDA, the SCL, and the INTB pins are all open-drain and 3.3-V compatible.
These pins can be used to connect to an MCU which is supplied by 3.3-V supply without requiring
voltage level translation between LDC3114 and the MCU.
7.3.8.1 I2C Interface Specifications
The maximum speed of the I2C interface is 400 kHz. This sequence uses the standard I2C 7-bit target address
followed by an 8-bit pointer to set the register address. For both write and read, the address pointer will
auto-increment as long as the controller acknowledges.
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
Slave
Start by
Master
R/W
Ack
by
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register Address
1 9
Ack
by
Slave
Frame 3
Data Byte
D3 D1D2D4D5D6
D7
A2 A0A1A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued)
Stop by
Master
D0
Figure 7-4. I2C Sequence of Writing a Single Register
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D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
Slave
Start by
Master
R/W
Ack
by
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register Address (ADDR) from
Master
1 9
Ack
by
Slave
Frame 3
Data Byte to
Register ADDR
D3 D1D2
D4D5D6D7
A2 A0A1
A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued) D0
1 9
Ack
by
Slave
Frame N+3
Data Byte to Register
ADDR+N
D3 D1D2
D4D5D6D7
SCL
(continued)
SDA
(continued)
Stop by
Master
D0
1 9
D7 D6 D5 D4 D3 D2 D1 D0
Frame 4
Data Byte to
Register ADDR+1
Ack
by
Slave
Figure 7-5. I2C Sequence of Writing Consecutive Registers
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
Slave
Start by
Master
R/W
Ack
by
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register Address from Master
A2 A0A1 A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued) D7 D6 D5 D4 D3 D2 D1 D0
1 9
Ack
by
Slave
Repeat
Start by
Master
No Ack
by
Master
Stop
by
Master
1 9
Frame 3
Serial Bus Address Byte
from Master
R/W
A2 A0A1A3A4A5A6
Frame 4
Data Byte from Slave
Figure 7-6. I2C Sequence of Reading a Single Register
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D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
Slave
Start by
Master
R/W
Ack
by
Slave
Frame 1
Serial Bus Address Byte
from Master
Frame 2
Slave Register Address (ADDR) from
Master
A2 A0A1
A3A4A5A6
SCL
SDA
SCL
(continued)
SDA
(continued) D7 D6 D5 D4 D3 D2 D1 D0
1 9
Ack
by
Slave
Repeat
Start by
Master
Ack
by
Master
Stop
by
Master
1 9
Frame 3
Serial Bus Address Byte
from Master
R/W
A2 A0A1
A3A4A5A6
Frame 4
Data Byte from Slave Register ADDR
SCL
(continued)
SDA
(continued) D7 D6 D5 D4 D3 D2 D1 D0
Ack
by
Master
No Ack
by
Master
1 9
Frame 5
Data Byte from Slave Register ADDR+1
Frame N+4
Data Byte from Slave Register
ADDR+N
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Figure 7-7. I2C Sequence of Reading Consecutive Registers
7.3.8.2 I2C Bus Control
The LDC3114 cannot drive the I2C clock (SCL), that is the device does not support clock stretching. In the
unlikely event where the SCL is stuck LOW, power cycle any device that is holding the SCL to activate its
internal Power-On Reset (POR) circuit. If the LDC is connected to the same power supply as that device, there
will be about 66-ms setup time before the LDC becomes active again. For more information, refer to Defining
Power-On Timing. If the data line (SDA) is stuck LOW, the I2C controller should send nine clock pulses. The
device that is holding the bus LOW should release the bus sometime within those nine clocks. If not, then power
cycle to clear the bus.
The LDC3114 has built-in monitors to check that the device is currently working. In the unlikely event of a device
fault, the device state will be reset internally, and all the registers will be reset with default settings. For system
robustness, TI recommends to check the value of a modified register periodically to monitor the device status
and reload the register settings, if needed.
7.4 Device Functional Modes
The LDC3114 supports two power modes of operation: a Normal Power Mode for active sampling at 10, 20, 40,
or 80 SPS, and a Low Power Mode for reduced current consumption at 0.625, 1.25, 2.5, or 5 SPS. The device
can also be configured in Normal Power Mode for additional faster sampling rate of 160 SPS or for a continuous
sampling rate. Refer to Configuring Button or Raw Data Scan Rate for details.
7.4.1 Normal Power Mode
When the LPWRB input pin is set to VDD, all enabled channels operate in Normal Power Mode. Each channel
can be enabled independently through Register EN (Address 0x0C). For the electrical specification of Normal
Power Mode Scan Rate, refer to the Electrical Characteristics table.
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7.4.2 Low Power Mode
When the LPWRB input pin is set to ground, only the low-power-enabled channels are active. Each channel can
be enabled independently to operate in Low Power Mode through Register EN (Address 0x0C). For a channel
to operate in the Low Power Mode, both the LPENn and ENn bits (n is the channel index) must be set to 1. The
Low Power Mode allows for energy-saving monitoring of button activity. In this mode, the device is in an inactive
power-saving state for the majority of the time. Lower scan rates correspond to lower current consumption.
In addition, the individual button sampling window should be set to the lowest effective setting (this is system
dependent, but typically 0.8 ms to 1 ms). For the electrical specification of the configurable Low Power Mode
Scan Rate, refer to the Electrical Characteristics table.
If a channel is operational in both Low Power Mode and Normal Power Mode, TI recommends to toggle the
LPWRB pin only after the button associated with that channel is released.
The Low Power Mode is also applicable for raw data access mode.
7.4.3 Configuration Mode
Before configuring any register settings, the device must be put into the configuration mode first. Setting
CONFIG_MODE = 1 through Register RESET (Address 0x0A) stops data conversion and holds the device
in configuration mode. Any device configuration changes can then be made. The current consumption in this
mode is typically 0.3 mA. After all changes have been written, set CONFIG_MODE = 0 for normal operation.
Refer to I2C Interface for more information.
7.5 Register Maps
7.5.1 LDC3114 Registers
LDC3114 Registers lists the memory-mapped registers for the LDC3114 registers. All register offset addresses
not listed in LDC3114 Registers should be considered as reserved locations and the register contents should not
be modified.
Table 7-1. LDC3114 Registers
Offset Acronym Register Name Section
0h STATUS Device status Section 7.5.1.1
1h OUT Channel output logic states Section 7.5.1.2
2h DATA0_LSB The lower 8 bits of the Button 0 data (Two's
complement
Section 7.5.1.3
3h DATA0_MSB The upper 4 bits of the Button 0 data (Two's
complement)
Section 7.5.1.4
4h DATA1_LSB The lower 8 bits of the Button 1 data (Two's
complement)
Section 7.5.1.5
5h DATA1_MSB The upper 4 bits of the Button 1 data (Two's
complement)
Section 7.5.1.6
6h DATA2_LSB The lower 8 bits of the Button 2 data (Two's
complement)
Section 7.5.1.7
7h DATA2_MSB The upper 4 bits of the Button 2 data (Two's
complement)
Section 7.5.1.8
8h DATA3_LSB The lower 8 bits of the Button 3 data (Two's
complement)
Section 7.5.1.9
9h DATA3_MSB The upper 4 bits of the Button 3 data (Two's
complement)
Section 7.5.1.10
Ah RESET Reset device and register configurations Section 7.5.1.11
Ch EN Enable channels and low power modes Section 7.5.1.12
Dh NP_SCAN_RATE Normal Power Mode scan rate Section 7.5.1.13
Eh GAIN0 Gain for Channel 0 sensitivity adjustment for
button algorithm
Section 7.5.1.14
Fh LP_SCAN_RATE Low Power Mode scan rate Section 7.5.1.15
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Table 7-1. LDC3114 Registers (continued)
Offset Acronym Register Name Section
10h GAIN1 Gain for Channel 1 sensitivity adjustment for
button algorithm
Section 7.5.1.16
11h INTPOL Interrupt polarity Section 7.5.1.17
12h GAIN2 Gain for Channel 2 sensitivity adjustment for
button algorithm
Section 7.5.1.18
13h LP_BASE_INC Low power base increment for button
algorithm
Section 7.5.1.19
14h GAIN3 Gain for Channel 3 sensitivity adjustment for
button algorithm
Section 7.5.1.20
15h NP_BASE_INC Normal power base increment for button
algorithm
Section 7.5.1.21
16h BTPAUSE_MAXWIN Baseline tracking pause and Max-win for
button algorithm
Section 7.5.1.22
17h LC_DIVIDER LC oscillation frequency divider Section 7.5.1.23
18h HYST Hysteresis for threshold for button algorithm Section 7.5.1.24
19h TWIST Anti-twist for button algorithm Section 7.5.1.25
1Ah COMMON_DEFORM Anti-common and anti-deformation for button
algorithm
Section 7.5.1.26
1Ch OPOL_DPOL Output polarity for button data and output Section 7.5.1.27
1Eh CNTSC Counter scale Section 7.5.1.28
20h SENSOR0_CONFIG Sensor 0 cycle count, frequency, RP range Section 7.5.1.29
22h SENSOR1_CONFIG Sensor 1 cycle count, frequency, RP range Section 7.5.1.30
24h SENSOR2_CONFIG Sensor 2 cycle count, frequency, RP range Section 7.5.1.31
25h FTF0 Sensor 0 fast tracking factor for button
algorithm
Section 7.5.1.32
26h SENSOR3_CONFIG Sensor3 cycle count, frequency, RP range Section 7.5.1.33
28h FTF1_2 Sensors 1 and 2 fast tracking factors for
button algorithm
Section 7.5.1.34
2Bh FTF3 Sensor 3 fast tracking factor for button
algorithm
Section 7.5.1.35
59h RAW_DATA0_3 Sensor 0 pre-processed raw data Section 7.5.1.36
5Ah RAW_DATA0_2 Sensor 0 pre-processed raw data Section 7.5.1.37
5Bh RAW_DATA0_1 Sensor 0 pre-processed raw data Section 7.5.1.38
5Ch RAW_DATA1_3 Sensor 1 pre-processed raw data Section 7.5.1.39
5Dh RAW_DATA1_2 Sensor 1 pre-processed raw data Section 7.5.1.40
5Eh RAW_DATA1_1 Sensor 1 pre-processed raw data Section 7.5.1.41
5Fh RAW_DATA2_3 Sensor 2 pre-processed raw data Section 7.5.1.42
60h RAW_DATA2_2 Sensor 2 pre-processed raw data Section 7.5.1.43
61h RAW_DATA2_1 Sensor 2 pre-processed raw data Section 7.5.1.44
62h RAW_DATA3_3 Sensor 3 pre-processed raw data Section 7.5.1.45
63h RAW_DATA3_2 Sensor 3 pre-processed raw data Section 7.5.1.46
64h RAW_DATA3_1 Sensor 3 pre-processed raw data Section 7.5.1.47
FCh MANUFACTURER_ID_LSB Manufacturer ID lower byte Section 7.5.1.48
FDh MANUFACTURER_ID_MSB Manufacturer ID upper byte Section 7.5.1.49
FEh DEVICE_ID_LSB Device ID lower byte Section 7.5.1.50
FFh DEVICE_ID_MSB Device ID upper byte Section 7.5.1.51
Complex bit access types are encoded to fit into small table cells. LDC3114 Access Type Codes shows the
codes that are used for access types in this section.
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Table 7-2. LDC3114 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-nValue after reset or the default
value
7.5.1.1 STATUS Register (Offset = 0h) [Reset = 40h]
STATUS is shown in STATUS Register Field Descriptions.
Return to the LDC3114 Registers.
Device status
Table 7-3. STATUS Register Field Descriptions
Bit Field Type Reset Description
7 OUT_STATUS R 0h Output Status
Logic OR of output OUTx bits. This field is cleared by reading this
register.
6 CHIP_READY R 1h Chip Ready Status
0h = Chip not ready after internal reset
1h = Chip ready after internal reset
5 RDY_TO_WRITE R 0h Ready to Write
Indicates if registers are ready to be written. See I2C Interface
section for more information.
0h = Registers not ready
1h = Registers ready
4 MAXOUT R 0h Maximum Output Code
Indicates if any channel button output data reaches the maximum
value (+0x7FF or -0x800). Cleared by a read of the status register.
0h = No maximum output code
1h = Maximum output code
3 FSM_WD R 0h Finite-State Machine Watchdog Error
Reports an error has occurred and conversions have been halted.
Cleared by a read of the status register.
0h = No error in finite-state machine
1h = Error in finite-state machine
2 LC_WD R 0h LC Sensor Watchdog Error
Reports an error when any LC oscillator fails to start. Cleared by a
read of the status register.
0h = No error in LC oscillator initialization
1h = Error in LC oscillator initialization
1 TIMEOUT R 0h Button Timeout
Reports when any button is asserted for more than 50 seconds.
Cleared by a read of the status register. When DIS_BTN_TO is set,
no timeout is asserted
0h = no timeout error
1h = timeout error
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Table 7-3. STATUS Register Field Descriptions (continued)
Bit Field Type Reset Description
0 REGISTER_FLAG R 0h Register Integrity Flag
Reports if any register's value has an unexpected change. Cleared
by a read of the status register.
0h = No unexpected register change
1h = Unexpected register change
7.5.1.2 OUT Register (Offset = 1h) [Reset = 00h]
OUT is shown in OUT Register Field Descriptions.
Return to the LDC3114 Registers.
Channel output logic states
Table 7-4. OUT Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0h Reserved
4 DATA_RDY R 0h Output Logic State for pre-processed data capture for any enabled
channel. Bit cleared on read.
0h = Data Capture in progress
1h = New Data available
3 OUT3 R 0h Button output output Logic State for Channel 3
0h = No button press detected on Channel 3
1h = Button press detected on Channel 3
2 OUT2 R 0h Button output Logic State for Channel 2
0h = No button press detected on Channel 2
1h = Button press detected on Channel 2
1 OUT1 R 0h Button output Logic State for Channel 1
0h = No button press detected on Channel 1
1h = Button press detected on Channel 1
0 OUT0 R 0h Button output Logic State for Channel 0
0h = No button press detected on Channel 0
1h = Button press detected on Channel 0.
7.5.1.3 DATA0_LSB Register (Offset = 2h) [Reset = 00h]
DATA0_LSB is shown in DATA0_LSB Register Field Descriptions.
Return to the LDC3114 Registers.
The lower 8 bits of the Button 0 data (Two's complement
Table 7-5. DATA0_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA0[7:0] R 0h The lower 8 bits of Channel 0 button data (Two's complement).
7.5.1.4 DATA0_MSB Register (Offset = 3h) [Reset = 00h]
DATA0_MSB is shown in DATA0_MSB Register Field Descriptions.
Return to the LDC3114 Registers.
The upper 4 bits of the Button 0 data (Two's complement)
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Table 7-6. DATA0_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA0[11:8] R 0h The upper 4 bits of Channel 0 button data (Two's complement).
7.5.1.5 DATA1_LSB Register (Offset = 4h) [Reset = 00h]
DATA1_LSB is shown in DATA1_LSB Register Field Descriptions.
Return to the LDC3114 Registers.
The lower 8 bits of the Button 1 data (Two's complement)
Table 7-7. DATA1_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA1[7:0] R 0h The lower 8 bits of Channel 1 button data (Two's complement).
7.5.1.6 DATA1_MSB Register (Offset = 5h) [Reset = 00h]
DATA1_MSB is shown in DATA1_MSB Register Field Descriptions.
Return to the LDC3114 Registers.
The upper 4 bits of the Button 1 data (Two's complement)
Table 7-8. DATA1_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA1[11:8] R 0h The upper 4 bits of Channel 1 button data (Two's complement).
7.5.1.7 DATA2_LSB Register (Offset = 6h) [Reset = 00h]
DATA2_LSB is shown in DATA2_LSB Register Field Descriptions.
Return to the LDC3114 Registers.
The lower 8 bits of the Button 2 data (Two's complement)
Table 7-9. DATA2_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA2[7:0] R 0h The lower 8 bits of Channel 2 button data (Two's complement).
7.5.1.8 DATA2_MSB Register (Offset = 7h) [Reset = 00h]
DATA2_MSB is shown in DATA2_MSB Register Field Descriptions.
Return to the LDC3114 Registers.
The upper 4 bits of the Button 2 data (Two's complement)
Table 7-10. DATA2_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA2[11:8] R 0h The upper 4 bits of Channel 2 button data (Two's complement).
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7.5.1.9 DATA3_LSB Register (Offset = 8h) [Reset = 00h]
DATA3_LSB is shown in DATA3_LSB Register Field Descriptions.
Return to the LDC3114 Registers.
The lower 8 bits of the Button 3 data (Two's complement)
Table 7-11. DATA3_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 DATA3[7:0] R 0h The lower 8 bits of Channel 3 button data (Two's complement).
7.5.1.10 DATA3_MSB Register (Offset = 9h) [Reset = 00h]
DATA3_MSB is shown in DATA3_MSB Register Field Descriptions.
Return to the LDC3114 Registers.
The upper 4 bits of the Button 3 data (Two's complement)
Table 7-12. DATA3_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h Reserved
3-0 DATA3[11:8] R 0h The upper 4 bits of Channel 3 button data (Two's complement).
7.5.1.11 RESET Register (Offset = Ah) [Reset = 00h]
RESET is shown in RESET Register Field Descriptions.
Return to the LDC3114 Registers.
Reset device and register configurations
Table 7-13. RESET Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 0h Reserved
4 FULL_RESET R/W 0h Device Reset
0h = Normal operation
1h = Resets the device and register configurations. All registers will
be returned to default values. Normal operation will not resume until
STATUS:CHIP_READY = 1.
3-1 RESERVED R/W 0h Reserved
0 CONFIG_MODE R/W 0h Configuration Mode
Any device configuration changes should be made with this bit set to
1. After all configuration changes have been written, set this bit to 0
for normal operation.
0h = Normal operation
1h = Holds the device in configuration mode (no data conversion),
but maintains current register configurations.
7.5.1.12 EN Register (Offset = Ch) [Reset = 1Fh]
EN is shown in EN Register Field Descriptions.
Return to the LDC3114 Registers.
Enable channels and low power modes
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