Texas Instruments MSP430F643 Series User manual

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MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D –AUGUST 2010–REVISED DECEMBER 2015
MSP430F643x Mixed-Signal Microcontrollers
1 Device Overview
1.1 Features
1
• Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timers With 3, 5, or 7
Capture/Compare Registers
• Ultra-Low Power Consumption • Two Universal Serial Communication Interfaces
– Active Mode (AM): (USCIs)
All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program – USCI_A0 and USCI_A1 Each Support:
Execution (Typical) • Enhanced UART Supports Automatic Baud-
– Standby Mode (LPM3): Rate Detection
Watchdog With Crystal and Supply Supervisor • IrDA Encoder and Decoder
Operational, Full RAM Retention, Fast Wakeup: • Synchronous SPI
1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) – USCI_B0 and USCI_B1 Each Support:
– Shutdown Real-Time Clock (RTC) Mode • I2C
(LPM3.5): • Synchronous SPI
Shutdown Mode, Active RTC With Crystal: • Integrated 3.3-V Power System
1.1 µA at 3.0 V (Typical) • 12-Bit Analog-to-Digital Converter (ADC) With
– Shutdown Mode (LPM4.5): Internal Shared Reference, Sample-and-Hold, and
0.3 µA at 3.0 V (Typical) Autoscan Feature
• Wake up From Standby Mode in 3 µs (Typical) • Dual 12-Bit Digital-to-Analog Converters (DACs)
• 16-Bit RISC Architecture, Extended Memory, up to With Synchronization
20-MHz System Clock • Voltage Comparator
• Flexible Power-Management System • Integrated Liquid Crystal Display (LCD) Driver With
– Fully Integrated LDO With Programmable Contrast Control for up to 160 Segments
Regulated Core Supply Voltage • Hardware Multiplier Supports 32-Bit Operations
– Supply Voltage Supervision, Monitoring, and • Serial Onboard Programming, No External
Brownout Programming Voltage Needed
• Unified Clock System • Six-Channel Internal DMA
– FLL Control Loop for Frequency Stabilization • RTC Module With Supply Voltage Backup Switch
– Low-Power Low-Frequency Internal Clock •Table 3-1 Summarizes the Available Family
Source (VLO) Members
– Low-Frequency Trimmed Internal Reference • For Complete Module Descriptions, See the
Source (REFO) MSP430x5xx and MSP430x6xx Family User's
– 32-kHz Crystals (XT1) Guide (SLAU208)
– High-Frequency Crystals up to 32 MHz (XT2)
1.2 Applications
• Analog and Digital Sensor Systems • Thermostats
• Digital Motor Control • Digital Timers
• Remote Controls • Hand-Held Meters
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D –AUGUST 2010–REVISED DECEMBER 2015 www.ti.com
1.3 Description
The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different
sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-
power modes to active mode in 3 µs (typical).
The MSP430F643x devices are microcontrollers with an integrated 3.3-V LDO, a high-performance 12-bit
ADC, a comparator, two USCIs, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm
capabilities, an LCD driver, and up to 74 I/O pins.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE(2)
MSP430F6438IPZ LQFP (100) 14 mm × 14 mm
MSP430F6438IZQW BGA (113) 7 mm × 7 mm
(1) For the most current device, package, and ordering information, see the Package Option Addendum in
Section 8, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
2Device Overview Copyright © 2010–2015, Texas Instruments Incorporated
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Unified
Clock
System
256KB
128KB
Flash
18KB/
10KB
RAM
+8B Backup
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
SBW
Interface/
Port PJ
PA PB PC PD
DMA
6 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
LCD_B
160
Segments
Comp_B
PJ.x
RTC_B
Battery
Backup
System
PU Port
LDO
PU.0
PU.1 LDOO LDOI
Unified
Clock
System
256KB
128KB
Flash
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
SBW
Interface/
Port PJ
PA PB PC PD
DMA
6 Channel
XT2IN
XT2OUT
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_B
Battery
Backup
System
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
DAC12_A
12 bit
2 channels
voltage out
LCD_B
160
Segments
Comp_B
PJ.x
18KB
RAM
+8B Backup
RAM
PU Port
LDO
PU.0
PU.1 LDOO LDOI
MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
www.ti.com SLAS720D –AUGUST 2010–REVISED DECEMBER 2015
1.4 Functional Block Diagrams
Figure 1-1 shows the functional block diagram for the MSP430F6438 and MSP430F6436 devices.
Figure 1-1. Functional Block Diagram – MSP430F6438, MSP430F6436
Figure 1-2 shows the functional block diagram for the MSP430F6435 and MSP430F6433 devices.
Figure 1-2. Functional Block Diagram – MSP430F6435, MSP430F6433
Copyright © 2010–2015, Texas Instruments Incorporated Device Overview 3
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MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D –AUGUST 2010–REVISED DECEMBER 2015 www.ti.com
Table of Contents
1 Device Overview ......................................... 15.29 Timer_B, Timer TB0 ................................ 33
1.1 Features .............................................. 15.30 Battery Backup...................................... 33
1.2 Applications........................................... 15.31 USCI (UART Mode)................................. 34
1.3 Description............................................ 25.32 USCI (SPI Master Mode)............................ 34
1.4 Functional Block Diagrams........................... 35.33 USCI (SPI Slave Mode)............................. 36
2 Revision History ......................................... 55.34 USCI (I2C Mode) .................................... 38
3 Device Comparison ..................................... 65.35 LCD_B, Recommended Operating Conditions...... 39
4 Terminal Configuration and Functions.............. 75.36 LCD_B, Electrical Characteristics................... 40
4.1 Pin Designation – MSP430F6438IPZ, 5.37 12-Bit ADC, Power Supply and Input Range
MSP430F6436IPZ.................................... 7Conditions ........................................... 41
4.2 Pin Designation – MSP430F6435IPZ, 5.38 12-Bit ADC, Timing Parameters .................... 41
MSP430F6433IPZ.................................... 85.39 12-Bit ADC, Linearity Parameters Using an External
4.3 Pin Designation – MSP430F6438IZQW, Reference Voltage .................................. 42
MSP430F6436IZQW, MSP430F6435IZQW, 5.40 12-Bit ADC, Linearity Parameters Using AVCC as
MSP430F6433IZQW ................................. 9Reference Voltage .................................. 42
4.4 Signal Descriptions.................................. 10 5.41 12-Bit ADC, Linearity Parameters Using the Internal
5 Specifications........................................... 17 Reference Voltage .................................. 42
5.1 Absolute Maximum Ratings......................... 17 5.42 12-Bit ADC, Temperature Sensor and Built-In VMID 43
5.2 ESD Ratings ........................................ 17 5.43 REF, External Reference ........................... 44
5.3 Recommended Operating Conditions............... 17 5.44 REF, Built-In Reference............................. 45
5.4 Active Mode Supply Current Into VCC Excluding 5.45 12-Bit DAC, Supply Specifications.................. 46
External Current..................................... 19 5.46 12-Bit DAC, Linearity Specifications ................ 46
5.5 Low-Power Mode Supply Currents (Into VCC)5.47 12-Bit DAC, Output Specifications .................. 48
Excluding External Current.......................... 19 5.48 12-Bit DAC, Reference Input Specifications ........ 49
5.6 Low-Power Mode With LCD Supply Currents (Into 5.49 12-Bit DAC, Dynamic Specifications................ 49
VCC) Excluding External Current.................... 20 5.50 12-Bit DAC, Dynamic Specifications (Continued)... 50
5.7 Thermal Resistance Characteristics ................ 21 5.51 Comparator_B....................................... 51
5.8 Schmitt-Trigger Inputs – General-Purpose I/O...... 22 5.52 Ports PU.0 and PU.1................................ 52
5.9 Inputs – Ports P1, P2, P3, and P4.................. 22 5.53 LDO-PWR (LDO Power System) ................... 53
5.10 Leakage Current – General-Purpose I/O ........... 22 5.54 Flash Memory....................................... 54
5.11 Outputs – General-Purpose I/O (Full Drive
Strength) ............................................ 22 5.55 JTAG and Spy-Bi-Wire Interface.................... 54
5.12 Outputs – General-Purpose I/O (Reduced Drive 6 Detailed Description ................................... 55
Strength) ............................................ 23 6.1 Overview ............................................ 55
5.13 Output Frequency – Ports P1, P2, and P3.......... 23 6.2 CPU ................................................. 55
5.14 Typical Characteristics – Outputs, Reduced Drive 6.3 Instruction Set....................................... 56
Strength (PxDS.y = 0)............................... 24 6.4 Operating Modes.................................... 57
5.15 Typical Characteristics – Outputs, Full Drive 6.5 Interrupt Vector Addresses.......................... 58
Strength (PxDS.y = 1)............................... 25 6.6 Memory.............................................. 59
5.16 Crystal Oscillator, XT1, Low-Frequency Mode ..... 26 6.7 Bootloader (BSL).................................... 60
5.17 Crystal Oscillator, XT2 .............................. 27
5.18 Internal Very-Low-Power Low-Frequency Oscillator 6.8 JTAG Operation..................................... 60
(VLO)................................................ 28 6.9 Flash Memory (Link to User's Guide)............... 61
5.19 Internal Reference, Low-Frequency Oscillator 6.10 RAM (Link to User's Guide)......................... 62
(REFO) .............................................. 28 6.11 Backup RAM ........................................ 62
5.20 DCO Frequency..................................... 29 6.12 Peripherals .......................................... 62
5.21 PMM, Brownout Reset (BOR)....................... 30 6.13 Input/Output Schematics ............................ 84
5.22 PMM, Core Voltage ................................. 30 6.14 Device Descriptors................................. 107
5.23 PMM, SVS High Side ............................... 31 7 Device and Documentation Support.............. 108
5.24 PMM, SVM High Side............................... 31 7.1 Device Support..................................... 108
5.25 PMM, SVS Low Side................................ 32 7.2 Documentation Support............................ 111
5.26 PMM, SVM Low Side ............................... 32 7.3 Related Links ...................................... 111
5.27 Wake-up Times From Low-Power Modes and 7.4 Community Resources............................. 112
Reset ................................................ 32 7.5 Trademarks ........................................ 112
5.28 Timer_A, Timers TA0, TA1, and TA2 ............... 33
4Table of Contents Copyright © 2010–2015, Texas Instruments Incorporated
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MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
www.ti.com SLAS720D –AUGUST 2010–REVISED DECEMBER 2015
7.6 Electrostatic Discharge Caution ................... 112 7.8 Glossary............................................ 112
7.7 Export Control Notice.............................. 112 8 Mechanical, Packaging, and Orderable
Information............................................. 112
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from August 5, 2013 to December 8, 2015 Page
• Document format and organization changes throughout, including addition of section numbering........................ 1
• Moved all functional block diagrams to Section 1.4,Functional Block Diagrams ............................................ 3
• Added USB column to Table 3-1,Family Members ............................................................................. 6
• Added Section 3,Device Comparison, and moved Table 3-1,Family Members to it ....................................... 6
• Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Table 4-1,Signal Descriptions .. 14
• Moved all electrical specifications to Section 5 ................................................................................. 17
• Added Section 5.2,ESD Ratings.................................................................................................. 17
• Added note to CVCORE............................................................................................................... 17
• Added Section 5.7,Thermal Characteristics .................................................................................... 21
• Added note to RPull .................................................................................................................. 22
• Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF ......................... 26
• In VBAT3 parameter description, changed from "VBAT3 ≠VBAT/3" to "VBAT3 = VBAT/3" ........................................ 33
• Changed from fDAC12_0OUT to fDAC12_1OUT in the first row of the Test Conditions for the "Channel-to-channel
crosstalk" parameter................................................................................................................ 50
• Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from fToggle to 1/fToggle in
Figure 5-22,Crosstalk Test Conditions .......................................................................................... 50
• Corrected the spelling of the MRG bits in the fMCLK,MRG parameter........................................................... 54
• Removed RTC_B from LPM4.5 wake-up options............................................................................... 57
• Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 60
• Added the paragraph that starts "The application report Using the MSP430 RTC_B..." .................................. 64
• Corrected names of interrupt events PMMSWBOR (BOR) and PMMSWPOR (POR) in Table 6-10,System
Module Interrupt Vector Registers ................................................................................................ 65
• Corrected spelling of NMIIFG (added missing "I") in Table 6-10,System Module Interrupt Vector Registers.......... 65
• Added connection from "LCDS40...LCDS42" to AND gate in Figure 6-7,Port P5 (P5.2 to P5.7) Schematic .......... 93
• Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 6-10,Port P7 (P7.3) Schematic ........ 97
• Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows.................................................................. 97
• Changed Table 6-61,Port PU.0, PU.1 Functions ............................................................................. 104
• Added Section 7 and moved Development Tools Support,Device and Development Tool Nomenclature,
Trademarks, and Electrostatic Discharge Caution sections to it ............................................................ 108
• Added Section 8,Mechanical, Packaging, and Orderable Information..................................................... 112
Copyright © 2010–2015, Texas Instruments Incorporated Revision History 5
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MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D –AUGUST 2010–REVISED DECEMBER 2015 www.ti.com
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Family Members(1)(2)
USCI
CHANNEL CHANNEL
FLASH SRAM ADC12_A DAC12_A Comp_B
DEVICE Timer_A(3) Timer_B(4) USB I/O PACKAGE
A: B:
(KB) (KB) (Ch) (Ch) (Ch)
UART, SPI, I2C
IrDA, SPI
12 ext, 100 PZ,
MSP430F6438 256 18 5, 3, 3 7 2 2 2 12 No 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6436 128 18 5, 3, 3 7 2 2 2 12 No 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6435 256 18 5, 3, 3 7 2 2 - 12 No 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F6433 128 10 5, 3, 3 7 2 2 - 12 No 74
4 int 113 ZQW
(1) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
6Device Comparison Copyright © 2010–2015, Texas Instruments Incorporated
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3
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5
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23
24
25
76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
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98
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100
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30
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26
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F6438
MSP430F6436
PZ PACKAGE
(TOP VIEW)
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN LDOI
LDOO PU.1
NC
PU.0
VSSU NC
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
www.ti.com SLAS720D –AUGUST 2010–REVISED DECEMBER 2015
4 Terminal Configuration and Functions
4.1 Pin Designation – MSP430F6438IPZ, MSP430F6436IPZ
Figure 4-1 shows the pinout for the MSP430F6438 and MSP430F6436 devices in the PZ package.
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 4-1. 100-Pin PZ Package (Top View) – MSP430F6438, MSP430F6436
Copyright © 2010–2015, Texas Instruments Incorporated Terminal Configuration and Functions 7
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25
76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
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97
98
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100
75
74
73
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69
68
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64
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P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14
P7.7/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P2.0/P2MAP0
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN LDOI
LDOO PU.1
NC
PU.0
VSSU NC
AVSS3
P1.3/TA0.2/S36
P1.4/TA0.3/S35
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.5/TA0.4/S34
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
P4.2/TB0.2/S21
P4.1/TB0.1/S22
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P8.4 /S11/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
MSP430F6435
MSP430F6433
PZ PACKAGE
(TOP VIEW)
MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
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4.2 Pin Designation – MSP430F6435IPZ, MSP430F6433IPZ
Figure 4-2 shows the pinout for the MSP430F6435 and MSP430F6433 devices in the PZ package.
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 4-2. 100-Pin PZ Package (Top View) – MSP430F6435, MSP430F6433
8Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated
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A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
C1 C2 C3 C11 C12
D1 D2 D4 D5 D6 D7 D8 D9 D11 D12
E1 E2 E4 E5 E6 E7 E8 E9 E11 E12
F1 F2 F4 F5 F8 F9 F11 F12
G1 G2 G4 G5 G8 G9 G11 G12
J1 J2 J4 J5 J6 J7 J8 J9 J11 J12
H1 H2 H4 H5 H6 H7 H8 H9 H11 H12
K1 K2 K11 K12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12
M4
ZQW PACKAGE
(TOP VIEW)
MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
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4.3 Pin Designation – MSP430F6438IZQW, MSP430F6436IZQW, MSP430F6435IZQW,
MSP430F6433IZQW
Figure 4-3 shows the pin diagram for all devices in the ZQW package. See Section 4.4 for pin
assignments and descriptions.
NOTE: For terminal assignments, see Table 4-1
Figure 4-3. 113-Pin ZQW Package (Top View) – MSP430F6438, MSP430F6436, MSP430F6435,
MSP430F6433
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4.4 Signal Descriptions
Table 4-1 describes the signals for all device variants and packages.
Table 4-1. Signal Descriptions
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4
Analog input A4 – ADC
General-purpose digital I/O
P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5
Analog input A5 – ADC
General-purpose digital I/O
Comparator_B input CB6
P6.6/CB6/A6/DAC0 3 B1 I/O Analog input A6 – ADC
DAC12.0 output (not available on F6435 and F6433 devices)
General-purpose digital I/O
Comparator_B input CB7
P6.7/CB7/A7/DAC1 4 C2 I/O Analog input A7 – ADC
DAC12.1 output (not available on F6435 and F6433 devices)
General-purpose digital I/O
P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8
Analog input A12 –ADC
General-purpose digital I/O
P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9
Analog input A13 – ADC
General-purpose digital I/O
Comparator_B input CB10
P7.6/CB10/A14/DAC0 7 D2 I/O Analog input A14 – ADC
DAC12.0 output (not available on F6435 and F6433 devices)
General-purpose digital I/O
Comparator_B input CB11
P7.7/CB11/A15/DAC1 8 D1 I/O Analog input A15 – ADC
DAC12.1 output (not available on F6435 and F6433 devices)
General-purpose digital I/O
P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
P5.1/VREF-/VeREF- 10 E4 I/O Negative terminal for the reference voltage of the ADC for both sources, the
internal reference voltage, or an external applied reference voltage
E1,
AVCC1 11 Analog power supply
E2
AVSS1 12 F2 Analog ground supply
XIN 13 F1 I Input terminal for crystal oscillator XT1
XOUT 14 G1 O Output terminal of crystal oscillator XT1
(1) I = input, O = output, N/A = not available on this package offering
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
AVSS2 15 G2 Analog ground supply
General-purpose digital I/O
P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC
DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/P2MAP0 17 G4 I/O Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/P2MAP1 18 H2 I/O Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
P2.2/P2MAP2 19 J1 I/O Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
P2.3/P2MAP3 20 H4 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function
P2.4/P2MAP4 21 J2 I/O Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and mappable secondary function
P2.5/P2MAP5 22 K1 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/P2MAP6/R03 23 K2 I/O Default mapping: no secondary function
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
P2.7/P2MAP7/LCDREF/R13 24 L2 I/O External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply
VCORE(2) 27 M2 Regulated core power supply (internal use only, no external current loading)
General-purpose digital I/O
P5.2/R23 28 L3 I/O Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
LCDCAP/R33 29 M3 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
COM0 30 J4 O LCD common output COM0 for LCD backplane
General-purpose digital I/O
P5.3/COM1/S42 31 L4 I/O LCD common output COM1 for LCD backplane
LCD segment output S42
General-purpose digital I/O
P5.4/COM2/S41 32 M4 I/O LCD common output COM2 for LCD backplane
LCD segment output S41
General-purpose digital I/O
P5.5/COM3/S40 33 J5 I/O LCD common output COM3 for LCD backplane
LCD segment output S40
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input
P1.0/TA0CLK/ACLK/S39 34 L5 I/O ACLK output (divided by 1, 2, 4, 8, 16, or 32)
LCD segment output S39
General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.1/TA0.0/S38 35 M5 I/O BSL transmit output
LCD segment output S38
General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
P1.2/TA0.1/S37 36 J6 I/O BSL receive input
LCD segment output S37
General-purpose digital I/O with port interrupt
P1.3/TA0.2/S36 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output S36
General-purpose digital I/O with port interrupt
P1.4/TA0.3/S35 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
LCD segment output S35
General-purpose digital I/O with port interrupt
P1.5/TA0.4/S34 39 L6 I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
LCD segment output S34
General-purpose digital I/O with port interrupt
P1.6/TA0.1/S33 40 J7 I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
LCD segment output S33
General-purpose digital I/O with port interrupt
P1.7/TA0.2/S32 41 M7 I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
LCD segment output S32
General-purpose digital I/O with port interrupt
Timer TA1 clock input
P3.0/TA1CLK/CBOUT/S31 42 L7 I/O Comparator_B output
LCD segment output S31
General-purpose digital I/O with port interrupt
P3.1/TA1.0/S30 43 H7 I/O Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S30
General-purpose digital I/O with port interrupt
P3.2/TA1.1/S29 44 M8 I/O Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S29
General-purpose digital I/O with port interrupt
P3.3/TA1.2/S28 45 L8 I/O Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S28
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O with port interrupt
Timer TA2 clock input
P3.4/TA2CLK/SMCLK/S27 46 J8 I/O SMCLK output
LCD segment output S27
General-purpose digital I/O with port interrupt
P3.5/TA2.0/S26 47 M9 I/O Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S26
General-purpose digital I/O with port interrupt
P3.6/TA2.1/S25 48 L9 I/O Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S25
General-purpose digital I/O with port interrupt
P3.7/TA2.2/S24 49 M10 I/O Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S24
General-purpose digital I/O with port interrupt
P4.0/TB0.0/S23 50 J9 I/O Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
LCD segment output S23
General-purpose digital I/O with port interrupt
P4.1/TB0.1/S22 51 M11 I/O Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
LCD segment output S22
General-purpose digital I/O with port interrupt
P4.2/TB0.2/S21 52 L10 I/O Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
LCD segment output S21
General-purpose digital I/O with port interrupt
P4.3/TB0.3/S20 53 M12 I/O Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
LCD segment output S20
General-purpose digital I/O with port interrupt
P4.4/TB0.4/S19 54 L12 I/O Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
LCD segment output S19
General-purpose digital I/O with port interrupt
P4.5/TB0.5/S18 55 L11 I/O Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
LCD segment output S18
General-purpose digital I/O with port interrupt
P4.6/TB0.6/S17 56 K11 I/O Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
LCD segment output S17
General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance
P4.7/TB0OUTH/SVMOUT/S16 57 K12 I/O SVM output
LCD segment output S16
General-purpose digital I/O
P8.0/TB0CLK/S15 58 J11 I/O Timer TB0 clock input
LCD segment output S15
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P8.1/UCB1STE/UCA1CLK/S14 59 J12 I/O USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output
LCD segment output S14
General-purpose digital I/O
P8.2/UCA1TXD/UCA1SIMO/S13 60 H11 I/O USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out
LCD segment output S13
General-purpose digital I/O
P8.3/UCA1RXD/UCA1SOMI/S12 61 H12 I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in
LCD segment output S12
General-purpose digital I/O
P8.4/UCB1CLK/UCA1STE/S11 62 G11 I/O USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable
LCD segment output S11
DVSS2 63 G12 Digital ground supply
DVCC2 64 F12 Digital power supply
General-purpose digital I/O
P8.5/UCB1SIMO/UCB1SDA/S10 65 F11 I/O USCI_B1 SPI slave in/master out; USCI_B1 I2C data
LCD segment output S10
General-purpose digital I/O
P8.6/UCB1SOMI/UCB1SCL/S9 66 G9 I/O USCI_B1 SPI slave out/master in; USCI_B1 I2C clock
LCD segment output S9
General-purpose digital I/O
P8.7/S8 67 E12 I/O LCD segment output S8
General-purpose digital I/O
P9.0/S7 68 E11 I/O LCD segment output S7
General-purpose digital I/O
P9.1/S6 69 F9 I/O LCD segment output S6
General-purpose digital I/O
P9.2/S5 70 D12 I/O LCD segment output S5
General-purpose digital I/O
P9.3/S4 71 D11 I/O LCD segment output S4
General-purpose digital I/O
P9.4/S3 72 E9 I/O LCD segment output S3
General-purpose digital I/O
P9.5/S2 73 C12 I/O LCD segment output S2
General-purpose digital I/O
P9.6/S1 74 C11 I/O LCD segment output S1
General-purpose digital I/O
P9.7/S0 75 D9 I/O LCD segment output S0
B11,
VSSU 76 PU ground supply
B12 General-purpose digital I/O, controlled by PU control register. Port U is supplied by
PU.0 77 A12 I/O the LDOO rail.
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
NC 78 B10 No connect
General-purpose digital I/O, controlled by PU control register. Port U is supplied by
PU.1 79 A11 I/O the LDOO rail.
LDOI 80 A10 LDO input
LDOO 81 A9 LDO output
NC 82 B9 No connect
AVSS3 83 A8 Analog ground supply
General-purpose digital I/O
P7.2/XT2IN 84 B8 I/O Input terminal for crystal oscillator XT2
General-purpose digital I/O
P7.3/XT2OUT 85 B7 I/O Output terminal of crystal oscillator XT2
Capacitor for backup subsystem. Do not load this pin externally. For capacitor
VBAK 86 A7 values, see CBAK in Recommended Operating Conditions.
Backup or secondary supply voltage. If backup voltage is not supplied, connect to
VBAT 87 D8 DVCC externally.
General-purpose digital I/O
P5.7/RTCCLK 88 D7 I/O RTCCLK output
DVCC3 89 A6 Digital power supply
DVSS3 90 A5 Digital ground supply
Test mode pin; selects digital I/O on JTAG pins
TEST/SBWTCK 91 B6 I Spy-Bi-Wire input clock
General-purpose digital I/O
PJ.0/TDO 92 B5 I/O Test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK 93 A4 I/O Test data input or test clock input
General-purpose digital I/O
PJ.2/TMS 94 E7 I/O Test mode select
General-purpose digital I/O
PJ.3/TCK 95 D6 I/O Test clock
Reset input (active low)(3)
RST/NMI/SBWTDIO 96 A3 I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O
P6.0/CB0/A0 97 B4 I/O Comparator_B input CB0
Analog input A0 – ADC
General-purpose digital I/O
P6.1/CB1/A1 98 B3 I/O Comparator_B input CB1
Analog input A1 – ADC
General-purpose digital I/O
P6.2/CB2/A2 99 A2 I/O Comparator_B input CB2
Analog input A2 – ADC
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P6.3/CB3/A3 100 D5 I/O Comparator_B input CB3
Analog input A3 – ADC
E5,
E6,
E8,
F4,
F5,
Reserved N/A F8, Reserved. TI recommends connecting to ground (DVSS, AVSS).
G5,
G8,
H5,
H8,
H9
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5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Voltage applied at VCC to VSS –0.3 4.1 V
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2) –0.3 VCC + 0.3 V
Diode current at any device pin ±2 mA
Maximum junction temperature, TJ95 °C
Storage temperature, Tstg(3) –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6
Supply voltage during program execution and flash PMMCOREVx = 0, 1 2.0 3.6
VCC programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = V
PMMCOREVx = 0, 1, 2 2.2 3.6
DVCC = VCC)(1)(2)
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =
VSS 0 V
DVSS2 = DVSS3 = VSS)TA= 0°C to 85°C 1.55 3.6
VBAT,RTC Backup-supply voltage with RTC operational V
TA= –40°C to +85°C 1.70 3.6
VBAT,MEM Backup-supply voltage with backup memory retained TA= –40°C to +85°C 1.20 3.6 V
TAOperating free-air temperature I version –40 85 °C
TJOperating junction temperature I version –40 85 °C
CBAK Capacitance at pin VBAK 1 4.7 10 nF
CVCORE Capacitor at VCORE(3) 470 nF
CDVCC/Capacitor ratio of DVCC to VCORE 10
CVCORE
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 5.23
for the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
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2.01.8
8
0
12
20
25
System Frequency - MHz
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
2.2 2.4 3.6
0, 1, 2, 30, 1, 20, 10
1, 2, 3
1, 2
1
2, 3
3
2
16
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Recommended Operating Conditions (continued)
MIN NOM MAX UNIT
PMMCOREVx = 0,
1.8 V ≤VCC ≤3.6 V 0 8.0
(default condition)
PMMCOREVx = 1, 0 12.0
Processor frequency (maximum MCLK frequency)(4)(5) 2 V ≤VCC ≤3.6 V
fSYSTEM MHz
(see Figure 5-1)PMMCOREVx = 2, 0 16.0
2.2 V ≤VCC ≤3.6 V
PMMCOREVx = 3, 0 20.0
2.4 V ≤VCC ≤3.6 V
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Figure 5-1. Frequency vs Supply Voltage
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5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
EXECUTION
PARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz UNIT
MEMORY TYP MAX TYP MAX TYP MAX TYP MAX
0 0.32 0.36 2.1 2.4
1 0.36 2.4 3.6 4.0
IAM, Flash Flash 3 V mA
2 0.37 2.5 3.8
3 0.39 2.7 4.0 6.6
0 0.18 0.21 1.0 1.2
1 0.20 1.2 1.7 1.9
IAM, RAM RAM 3 V mA
2 0.22 1.3 2.0
3 0.23 1.4 2.1 3.6
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. LDO disabled (LDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
–40°C 25°C 60°C 85°C
PARAMETER VCC PMMCOREVx UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V 0 71 75 87 81 85 99
ILPM0,1MHz Low-power mode 0(3)(4) µA
3 V 3 78 83 98 89 94 108
2.2 V 0 6.3 6.7 9.9 9.0 11 16
ILPM2 Low-power mode 2(5)(4) µA
3 V 3 6.6 7.0 11 10 12 18
0 1.6 1.8 2.4 4.7 6.5 10.5
2.2 V 1 1.6 1.9 4.8 6.6
2 1.7 2.0 4.9 6.7
Low-power mode 3,
ILPM3,XT1LF 0 1.9 2.1 2.7 5.0 6.8 10.8 µA
crystal mode(6)(4) 1 1.9 2.1 5.1 7.0
3 V 2 2.0 2.2 5.2 7.1
3 2.0 2.2 2.9 5.4 7.3 12.6
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
LDO disabled (LDOEN = 0).
(4) Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO
setting = 1 MHz operation, DCO bias generator enabled.
LDO disabled (LDOEN = 0).
(6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
LDO disabled (LDOEN = 0).
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
–40°C 25°C 60°C 85°C
PARAMETER VCC PMMCOREVx UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
0 0.9 1.2 1.9 4.0 5.9 10.3
Low-power mode 3, 1 0.9 1.2 4.1 6.0
ILPM3, VLO mode, Watchdog 3 V µA
VLO,WDT 2 1.0 1.3 4.2 6.1
enabled(7)(4)
3 1.0 1.3 2.2 4.3 6.3 11.3
0 0.9 1.1 1.8 3.9 5.8 10
1 0.9 1.1 4.0 5.9
ILPM4 Low-power mode 4(8)(4) 3 V µA
2 1.0 1.2 4.1 6.1
3 1.0 1.2 2.1 4.2 6.2 11
Low-power mode 3.5
ILPM3.5, (LPM3.5) current with 3 V 0.5 0.8 1.4 µA
RTC,VCC active RTC into primary
supply pin DVCC (9)
Low-power mode 3.5
ILPM3.5, (LPM3.5) current with 3 V 0.6 0.8 1.4 µA
RTC,VBAT active RTC into backup
supply pin VBAT(10)
Total low-power mode
ILPM3.5, 3.5 (LPM3.5) current 3 V 1.0 1.1 1.3 1.6 2.8 µA
RTC,TOT with active RTC(11)
Low-power mode 4.5
ILPM4.5 3 V 0.2 0.3 0.6 0.7 0.9 1.4 µA
(LPM4.5)(12)
(7) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
LDO disabled (LDOEN = 0).
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
LDO disabled (LDOEN = 0).
(9) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(10) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(11) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
(12) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
0 2.3 2.7 3.1 5.4 7.4 11.5
Low-power mode 3
ILPM3, 1 2.3 2.7 5.6 7.5
(LPM3) current, LCD 4-
LCD, 3 V µA
mux mode, external 2 2.4 2.8 5.8 7.7
ext. bias biasing(3) (4) 3 2.4 2.8 3.5 5.9 7.9 13.2
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(4) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
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