Texas Instruments LMK03318EVM User manual

LMK03318EVM
User's Guide
Literature Number: SNAU186
November 2015

Contents
1 Overview............................................................................................................................. 6
2 Features.............................................................................................................................. 6
3 Modes of Operation.............................................................................................................. 7
4 Configuring the EVM ............................................................................................................ 7
4.1 Configuring the Power Supply.......................................................................................... 9
4.2 Configuring the Control Pins .......................................................................................... 11
4.3 Configuring the PLL Loop Filter....................................................................................... 15
4.4 Configuring the Reference Inputs .................................................................................... 16
4.5 Configuring the Clock Outputs........................................................................................ 17
4.6 Configuring the Status Outputs ....................................................................................... 17
4.7 Using the USB Interface Connection................................................................................. 17
5 EVM Quick Start Guide........................................................................................................ 18
6 EVM Layout ....................................................................................................................... 20
7 EVM Schematic.................................................................................................................. 33
8 EVM Bill of Materials........................................................................................................... 39
9 Recommended Test Instruments.......................................................................................... 42
10 Example Performance Measurements................................................................................... 43
11 Using TI’s USB2ANY Module for In-System Programming of LMK03318 ................................... 48
11.1 USB2ANY Board Connections........................................................................................ 48
11.2 Ordering a USB2ANY Module ........................................................................................ 52
2Table of Contents SNAU186–November 2015
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List of Figures
1 LMK03318EVM Photo....................................................................................................... 5
2 Power, Input, and Output Connections ................................................................................... 8
3 Power Terminals and Jumpers............................................................................................. 9
4 Control Pin Interfaces (Default Jumper Settings) ...................................................................... 11
5 Interfacing a 3.3-V LVCMOS Clock Input to SECREF_P............................................................. 16
6 Top Overlay................................................................................................................. 20
7 Top Solder Mask ........................................................................................................... 21
8 Layer 1 (Top Side) ......................................................................................................... 22
9 Layer 2....................................................................................................................... 23
10 Layer 3....................................................................................................................... 24
11 Layer 4....................................................................................................................... 25
12 Layer 5....................................................................................................................... 26
13 Layer 6....................................................................................................................... 27
14 Layer 7....................................................................................................................... 28
15 Layer 8 (Bottom Side, View from Top) .................................................................................. 29
16 Bottom Solder Mask ....................................................................................................... 30
17 Bottom Overlay ............................................................................................................. 31
18 Drill Drawing ................................................................................................................ 32
19 Soft Pin Mode, EEPROM Page 5, OUT0 – 156.25 MHz LVPECL (Spurs in dBc) ................................ 44
20 Soft Pin Mode, EEPROM Page 5, OUT2 – 125 MHz LVPECL (Spurs in dBc) .................................... 45
21 Soft Pin Mode, EEPROM Page 5, OUT4 – 100 MHz LVPECL (Spurs in dBc) .................................... 46
22 Soft Pin Mode, EEPROM Page 5, OUT6 – 25 MHz LVPECL (Spurs in dBc)...................................... 47
23 USB2ANY Module.......................................................................................................... 48
24 USB2ANY Board Connections ........................................................................................... 49
25 10-pin Cable Connection to J4 ........................................................................................... 50
26 10-pin Cable Pinout........................................................................................................ 50
27 USB2ANY Board Connector Pinout Diagram .......................................................................... 51
3
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List of Tables
1 Ordering Information ........................................................................................................ 6
2 Power Configurations...................................................................................................... 10
3 Control Pin Interfaces for Soft Pin Mode or Register Default Mode (JP18 HWCTRL = LO)..................... 12
4 Control Pin Interfaces for Hard Pin Mode (JP18 HWCTRL = HI).................................................... 15
5 PLL Loop Filter C2 Selection ............................................................................................. 15
6 Soft Pin Mode - EEPROM Page Configurations (Default EVM EEPROM Image)................................. 19
7 Output RMS Jitter Summary – Soft Pin Mode, EEPROM Page 5................................................... 43
8 USB2ANY Board Connector J4 and 10-pin Cable Pinouts........................................................... 51
4List of Tables SNAU186–November 2015
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User's Guide
SNAU186–November 2015
LMK03318EVM User’s Guide
Figure 1. LMK03318EVM Photo
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Overview www.ti.com
Table 1. Ordering Information
EVM ID DEVICE ID DEVICE PACKAGE
LMK03318EVM LMK03318RHS QFN-48
1 Overview
The LMK03318EVM evaluation module provides a complete clocking platform to evaluate the clock
performance, pin-/software-configuration modes and features of the Texas Instruments LMK03318 Ultra-
Low-Jitter Clock Generator with 1 PLL, 8 outputs, 2 inputs, and integrated EEPROM.
The LMK03318EVM can be used as a flexible, multi-output clock source for compliance testing,
performance evaluation, and initial system prototyping. The onboard edge-launch SMA ports provide
access to the LMK03318 clock inputs and outputs for interfacing to test equipment and reference boards
using commercially available coaxial cables, adapters, or baluns (not included). This connectivity enables
integrated system level testing between TI’s LMK03318 and third-party FPGA/ASIC/SoC reference
boards. A software graphical user interface (GUI) platform can be installed on a Host PC to access the
LMK03318 device registers and EEPROM via the on-board USB-to-I2C interface. The GUI platform can
also be used to export / import Register and EEPROM data files to facilitate factory or in-system
programming of custom device configurations.
2 Features
• High performance, flexible clock generator with 6 independent output dividers for clocking multiple
interface standards/protocols
• Outputs up to 8 pairs of Differential or 1.8-V LVCMOS clocks, or any combination of both
– 100 Ωdifferential and 50 Ωsingle-ended output drivers
• Two selectable reference inputs
– Differential / single-ended clock or crystal input (50 MHz crystal on-board)
– Automatic or pin-controlled input selection mux to PLL
– Either reference can be directly buffered on up to 4 output pairs (bypass PLL and output dividers)
• Flexible pin modes offer multiple start-up register configuration (jumper selectable)
– Soft Pin Modes: 6 pre-programmed settings in EEPROM (100+ programming cycles)
– Hard Pin Modes: 64 predefined settings in ROM
– Register Default Mode
• Clock frequency margining
– Up to ±50 ppm adjustment of output frequencies via on-board pullable crystal
• Jumper-selectable power options using direct or on-board regulator supplies:
– VDD = 3.3 V
– VDDO = 1.8, 2.5, or 3.3 V
• GUI platform for full access to device registers and EEPROM
• On-board USB-to-I2C programming interface
• LEDs indicators: Loss of Reference and Lock Detection, and USB / I2C activity
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www.ti.com Modes of Operation
3 Modes of Operation
The LMK03318 can be configured to start-up in one of three modes upon power-on/reset (POR). The
mode of operation and associated control pins determine which on-chip memory type and memory page
settings are used to initialize the active registers for configuring the Input, PLL, Output, Device Control,
and Status blocks for full operation:
1. Soft Pin Modes (EVM Default) – Loads all registers with one of the 6 page settings stored in
EEPROM. In the EVM-default EEPROM image, all 6 EEPROM pages have pre-programmed register
settings to demonstrate the various clock configurations in Soft Pin Mode using the default EVM
hardware. The EEPROM settings can be easily re-programmed by the user through the GUI platform.
2. Hard Pin Modes – Loads all registers from one of the 64 page settings stored in ROM. All 64 ROM
pages are “hard-coded” with predefined register settings by TI.
NOTE: Refer to the ROM page configurations for Hard Pin Mode in the LMK03318 datasheet. Some
ROM page settings may not operate with the default EVM configuration, and modification of
the EVM may be necessary to operate the intended mode. EVM modification areas may
include the crystal (Y1), PRIREF / SECREF input interfaces, OUT / STATUS output
interfaces, and PLL loop filter C2 capacitor selection (switch S1).
3. Register Default Mode – Loads all registers from the register default setting. The Register Default
Mode is hard-coded with predefined settings.
NOTE: Refer to the Register Default Mode in the LMK03318 datasheet. The Register Default Mode
will NOT operate using the on-board 50 MHz crystal (Y1) as the device expects a 25 MHz
reference input. To operate in Register Default Mode using a crystal input, Y1 must be
changed to a 25-MHz, 9-pF crystal (example P/N: TXC 7M25072001).
Once the LMK03318 is start-up in any of these modes, the I2C interface is enabled to provide (optional)
access to all device registers for full control of the LMK03318 settings. For convenience, a USB-to-I2C
interface is integrated on-board and can be controlled by the GUI platform.
4 Configuring the EVM
The LMK03318 is a highly-configurable clock generator with multiple power domains and input & output
clock domains. To support a wide range of evaluation use cases, the EVM was designed for maximum
flexibility so it has more functionality and peripheral circuitry than needed to implement the clock solution
in a typical customer system application.
This section describes the jumpers and connectors on the EVM, as well as how to connect, set-up, and
use the LMK03318EVM. When operating the LMK03318EVM, the power supply, clock inputs, and clock
outputs can be connected to the SMA ports shown in Figure 2. These SMA ports are labeled in the top
silkscreen layer.
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Figure 2. Power, Input, and Output Connections
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4.1 Configuring the Power Supply
The LMK03318 has four VDD (analog/digital core) supply pins that operate from 3.3V (+/- 5%) and six
VDDO (output) supply pins that operate from 1.8V to 3.3V (+/- 5%). The VDD and VDDO power planes on
the EVM can be powered from a single supply (3.3 V) or dual supplies (3.3 V and 1.8/2.5/3.3 V). Each
plane can be powered directly from an external supply or an on-board LDO regulator. Though the
LMK03318 already has integrated LDO regulators for excellent power-supply-ripple-rejection (PSRR), the
EVM’s on-board regulators (U3 & U4) allows the user to power the EVM using a higher supply voltage
(like 5 V) and enable jumper selection of the VDDO voltage. The direct external supplies or on-board
regulator supplies can be independently routed for the VDD and VDDO planes by configuring the power
terminals and jumpers shown in Figure 3.
J3 (PWR) is the main power terminal block for the EVM for connecting power and GND leads from an
external power supply. Power SMA ports EXTVDD (J1) and EXTVDDO (J3) provide an alternative
connector style to apply power using coax cables.
NOTE: Some power connections may NOT be used or required to operate the EVM.
Figure 3. Power Terminals and Jumpers
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Table 2 summarizes the EVM power configurations to connect and route power to the VDD and VDDO
supply domains of the LMK03318. Refer to Section 7 for more details.
Table 2. Power Configurations
On-board Regulators
CONNECTION NAME Direct Single Supply Direct Dual Supply
(Default)
LMK03318 VDD[x] 3.3 V 3.3 V 3.3 V
VDD pins
LMK03318 VDDO[x] 1.8 / 2.5 / 3.3 V 3.3 V 1.8 / 2.5 / 3.3 V
VDDO pins
J1 EXTVDD Alternative SMA power connection to J3 pins 1 & 3
J2 EXTVDDO Alternative SMA power connection to J3 pins 2 & 3
-Pin 1 (EXTVDD): Connect to
-Pin 1 (EXTVDD): Connect to -Pin 1 (EXTVDD): Connect to 3.3-V supply
5-V supply 3.3-V supply -Pin 2 (EXTVDDO): Connect to
J3 PWR -Pin 2: N/A -Pin 2: N/A 1.8 / 2.5 / 3.3 V supply
-Pin 3 (GND): Connect to GND -Pin 3 (GND): Connect to GND -Pin 3 (GND): Connect to GND
supply supply supply
Tie pins 2-3:
JP1(1) LDOIN Selects 5 V from EXTVDD to N/A N/A
operate regulators Tie pins 2-3: Tie pins 2-3:
Tie pins 1-2:
JP2 VDD Selects 3.3 V directly from Selects 3.3 V directly from
Selects VDD = 3.3 V from U3 EXTVDD EXTVDD
Tie pins 1-2: Tie pins 2-3:
Tie pins 2-4:
JP3 & J4(2) VDDO Selects VDDO = 1.8 / 2.5 / 3.3 Selects 1.8 / 2.5 / 3.3 V
Selects 3.3 V from VDD
V from U4 directly from EXTVDDO
-Open (JP8 Default):
Selects VDDO = 1.8 V
-Tie pins 1-2:
JP8 LDOSEL (U4) N/A N/A
Selects VDDO = 3.3 V
-Tie pins 2-3:
Selects VDDO = 2.5 V
(1) In typical configurations, the LMK03318EVM can consume more current than USB 2.0 limit of 0.5 A. Thus, it is advised to not
use the USB5V rail to power the on-board LDO regulators (i.e. do not tie pins 1-2 on JP1) unless the LMK03318 configuration
and peripheral circuitry are assured to never exceed 0.5 A current limit imposed by the TPS2553 USB switch (U10). The
LMK03318 may not initialize or operate properly when current limited.
(2) JP3 and J4 form a 3-way header where J4 is pin 4.
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4.2 Configuring the Control Pins
The LMK03318 has multiple external control pins to configure the operating mode and initial settings on
POR (see Section 3). Depending on the selected mode, some control pins will change between 2-level, 3-
level, or 8-level input scheme to increase the amount of control with a limited number of pins.
The LMK03318 control pins can be configured through the jumpers and switches shown in Figure 4.
Figure 4. Control Pin Interfaces (Default Jumper Settings)
Jumpers JP17 through JP24 can be used to configure the corresponding control pin to either high or low
state by strapping the center pin to “HI” position (tie pins 1-2) or “LO” position (tie pins 2-3), respectively.
Jumpers JP17, JP20, JP21, and JP22 can be used to configure the control pin with 3-level input scheme,
where VLO < 0.4V, VMID ~ 0.9V, VHI > 1.4V. Each of these 4 jumpers use a resistor divider network to bias
the control pin to a mid-level state of 0.9 V, when the jumper is left open (“MID” position).
The LMK03318 control pins perform different functions depending on the mode of operation.
• For Soft Pin Modes or Register Default Mode, refer to Table 3 for jumper and switch descriptions.
• For Hard Pin Modes, refer to Table 4. Jumpers not listed in Table 4 have identical functions described
in Table 3.
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Table 3. Control Pin Interfaces for Soft Pin Mode or Register Default Mode (JP18 HWCTRL = LO)
NAME
COMPONENT DESCRIPTION
(TYPE)
Hardware / Software Control (HW_SW_CTRL) pin
HWCTRL state is sampled on POR and determines the mode of operation.
HWCTRL STATE OPERATING MODE
Soft Pin Mode or Register Default Mode
LO GPIO[3:2] pins are also sampled on POR to determine the initial
HWCTRL (JP Default)
JP18 page setting loaded to registers (from EEPROM or default).
(2-level input) Hard Pin Mode
GPIO[5:0] pins are also sampled on POR to determine the initial
HI page setting loaded to registers (from ROM).
See Table 4: Control Pin Interfaces for Hard Pin Mode (JP18
HWCTRL = HI)
Reference Select (REFSEL) pin for PLL Input Mux
RSEL selects the PLL reference input when external “Pin Select” control is configured by the INSEL_PLL
register bits (R50[1:0] = 01b).
RSEL STATE (1) PLL REF INPUT
LO PRIREF
RSEL MID SECREF
JP17 (3-level input) HI Auto Select (2)
(JP Default)
(1) RSEL is ignored when INSEL_PLL bits ≠01b.
(2) In Auto Select mode, PRIREF is prioritized over SECREF when a valid signal is detected by the on-
chip reference detector logic. To use the SECREF input in Auto Select mode, the input signal to PRIREF
must be made invalid (disabled or disqualified by the reference detector).
SYNC pin (active low)
GPIO0 can be used to mute the output clocks (when asserted) and trigger output divider synchronization
(when de-asserted) if synchronization is permitted by the SYNC_MUTE and PLL_SYNC_EN register bits.
GPIO0 STATE SYNC OPERATION
GPIO0
JP19 (2-level input) LO Assert SYNC: Outputs muted, dividers in reset
HI Normal output operation
(JP Default)
SYNC can also be asserted when switch S4 is pressed.
I2C Slave Address LSB Select pin
GPIO1 is sampled on POR to configure the lower 2 bits of the 7-bit slave address. The upper 5 bits of the
slave address are initialized from EEPROM (SLAVEADR[7:3] = 10100b). By configuring GPIO1, the
composite slave address can be selected as follows:
7-BIT SLAVE ADDRESS
GPIO1 GPIO1 STATE
JP20 (excludes W/R bit)
(3-level input) LO 1010000b / 0x50
(JP Default)
MID 1010001b / 0x51
HI 1010011b / 0x53
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Table 3. Control Pin Interfaces for Soft Pin Mode or Register Default Mode (JP18 HWCTRL =
LO) (continued)
NAME
COMPONENT DESCRIPTION
(TYPE)
Page Select pins for Soft Pin Mode or Register Default Mode
With HWCTRL = LO, GPIO[3:2] pins are sampled on POR to select the EEPROM page or Register
Default settings to initialize the registers as follows:
GPIO3 STATE GPIO2 STATE DEVICE MODE / PAGE SELECT (1) (2)
LO LO Soft Pin Mode, EEPROM Page 0
LO MID Soft Pin Mode, EEPROM Page 1
LO HI Soft Pin Mode, EEPROM Page 2
GPIO2 HI LO Soft Pin Mode, EEPROM Page 3
JP21 GPIO3
JP22 (3-level HI MID Soft Pin Mode, EEPROM Page 4
inputs) HI HI Soft Pin Mode, EEPROM Page 5
(JP Default) (JP Default)
MID MID Register Default Mode
(1) Refer to Table 6 for Soft Pin Mode configurations pre-programmed to the EEPROM for EVM
demonstration purposes.
(2) Register Default Mode will not operate using the on-board 50 MHz crystal (Y1) as the device expects a
25 MHz reference input. To use Register Default Mode with a crystal input, Y1 must be changed to a 25-
MHz 9-pF crystal (example P/N: TXC 7M25072001).
XTAL Frequency Margining Enable pin
GPIO4 can be used to enable XTAL frequency margining when permitted by the MARGIN_OPTION
register setting (R86[3:2]) as follows:
XO MARGIN PIN CONTROL
GPIO4 STATE MARGIN_OPTION=00b
MARGIN_OPTION=01b (Default)
GPIO4 XO Margining enabled.
JP23 (2-level input) LO GPIO5 pin state selects XO
XO Margining enabled. Margining offset.(1)
GPIO5 pin state selects XO
Margining offset. (1)
HI XO Margining disabled.
(JP Default) GPIO5 pin is ignored. (2)
(1) See the description for JP24 (GPIO5) and switch S5 (XO MARGIN).
(2) XOOFFSET_STEP4 register setting sets the nominal XTAL frequency offset when XO margining is
disabled.
XTAL Frequency Margining Offset Select pin
GPIO5 can be used to select the one of the 8 on-chip XTAL load capacitance settings on the crystal input
(SECREF input) when XTAL frequency margining is enabled by the MARGIN_OPTION register and JP23
GPIO5 setting (GPIO4). The 8 load capacitance settings are programmable (via XOOFFSET_STEP# register
JP24 (8-level input) bits) and initialized from the selected operating mode/page setting. The 8-level input state on GPIO5 can
be configured by selecting one of the pull-down resistor values via switch S5 .
By default, JP24 is left open, so switch S5 can be used to set the frequency margining offset. See the
description for S5 (XO MARGIN).
SYNC push-button switch
S4 SYNC When pressed, the GPIO0 pin is pulled low to assert SYNC and mute the outputs. When released, the
GPIO pin is pulled high to trigger output synchronization and normal output operation.
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Table 3. Control Pin Interfaces for Soft Pin Mode or Register Default Mode (JP18 HWCTRL =
LO) (continued)
NAME
COMPONENT DESCRIPTION
(TYPE)
XTAL Frequency Margining Offset Resistor switch bank
If the XTAL input is used as the PLL reference, the PLL and its output clocks will track the frequency
offset of the XTAL.
When JP24 is open and JP23 is low, switch S5 can be used to select one of the 8 pull-down resistors
(RPD) on GPIO5 which determines the corresponding XTAL load capacitance and frequency offset state
(STEP1 to STEP8) as follows:
XOOFFSET XOOFFSET Nominal
S5 Position ON GPIO5 _STEP# _STEP#
GPIO5 RPD Frequency
(1) Voltage Register Setting (dec) Offset (2)
Control (2)
Pos. 1 0 Ω0.0 V STEP1 227 +50 ppm
XO MARGIN Pos. 2 2.32 kΩ0.2 V STEP2 306 +25 ppm
S5 (8-position
SPST switch) Pos. 3 5.62 kΩ0.4 V STEP3 345 +15 ppm
Pos. 4 10.5 kΩ0.6 V STEP4 412 0 ppm
(Default)
Pos. 5 18.7 kΩ0.8 V STEP5 494 -15 ppm
Pos. 6 34.8 kΩ1.0 V STEP6 558 -25 ppm
Pos. 7 84.5 kΩ1.2 V STEP7 676 -40 ppm
Pos. 8 open 1.4 V STEP8 778 -50 ppm
(1) Only one position should be ON at a time (all others are OFF).
(2) Applies only to Soft Pin Mode using the EVM’s default EEPROM settings optimized for a 9-pF crystal.
For Register Default Mode, refer to the datasheet for the default XOOFFSET_STEP# register settings.
PDN push-button switch
When pressed, the device PDN pin (active low) is pulled down to power-down the device. When released,
the PDN pin is pulled high to trigger the POR sequence, initialize the registers per the selected operating
mode, and begin normal operation.
PDN
S6 PDN STATE DEVICE OPERATION
(2-level input) Power-down mode
LO (Pushed) (I2C interface disabled)
HI (Released) Normal operation
USB port (Mini-B type)
Using the GUI platform, USB controller (U8) provides the USB-to-I2C interface to manage the LMK03318
device registers and EEPROM. LED D10 (USB COMM) should be lit green once USB communication is
J27 USB established with the GUI running on the Host PC.
By default, the USB port powers the LDO regulator U9 to supply 3.3 V power for the MCU and its
peripheral circuitry.
Test Point Access to I2C and Device Control pins
SDA and SCL lines are connected to 1.5 kΩpull-up resistors. LED D8 (I2C BUSY) will blink yellow during
I2C communication.
Pin 1: SDA Pin 2: SCL
J28 U2A Pin 4: Not connected Pin 3: Not connected
(not populated) Pin 5: GND Pin 6: Not connected
Pin 7: REFSEL Pin 8: HW_SW_CTRL
Pin 9: PDN Pin 10: GPIO0
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Table 4. Control Pin Interfaces for Hard Pin Mode (JP18 HWCTRL = HI)(1)(2)
NAME
COMPONENT DESCRIPTION
(TYPE)
Page Select pins for Hard Pin Mode
GPIO[5:0] pins are sampled on POR and select the ROM page
settings to initialize the registers as follows:
GPIO[5:0] STATES(3) DEVICE MODE / PAGE SELECT
000000 Hard Pin Mode, ROM Page 0
GPIO0 000001 Hard Pin Mode, ROM Page 1
JP19 GPIO1
JP20 000010 Hard Pin Mode, ROM Page 2
GPIO2
JP21 GPIO3 000011 Hard Pin Mode, ROM Page 3
JP22 GPIO4
JP23 000100 Hard Pin Mode, ROM Page 4
GPIO5
JP24 (2-level inputs) … …
111101 Hard Pin Mode, ROM Page 61
111101 Hard Pin Mode, ROM Page 61
111110 Hard Pin Mode, ROM Page 62
111111 Hard Pin Mode, ROM Page 63
S4 SYNC Not used for Hard Pin Mode.
S5 XO MARGIN Not used for Hard Pin Mode. Set all switch position to OFF.
(1) Jumpers not listed in Table 4 are identical to functions described in Table 3.
(2) Refer to the ROM page configurations for Hard Pin Mode in the LMK03318 datasheet. These settings may not operate with the default
EVM configuration, and modification of the EVM hardware may be required to operate the intended Hard Pin Mode configuration. EVM
modification areas may include the crystal (Y1), PRIREF / SECREF input interfaces, OUT / STATUS output interfaces, and PLL loop filter
C2 capacitor selection (switch S1).
(3) GPIO[5:0] values are BCD representation of the ROM Page value.
4.3 Configuring the PLL Loop Filter
The LMK03318 has configurable PLL loop bandwidth with most loop filter components integrated on-chip
(C1, R2, C3, and R3). Only one loop filter capacitor, C2, needs to be connected externally to LF (pin 34)
for PLL.
The LF pin is connected to the 3-position SPST switch (S1) to allow easy selection between one of the
three C2 values listed in Table 5. The C2 values were chosen to work well for different PLL modes / loop
bandwidths (BW).
Table 5. PLL Loop Filter C2 Selection
COMPONEN NAME DESCRIPTION
T
PLL Loop Filter C2 Capacitor Select
Only one position should be ON at a time (all others are OFF).
S1 Position ON C2 Value Intended PLL Mode (Loop BW)
S1 LF1 Pos. A 3300 pF Integer-N (Wide BW, >100 kHz)
Pos. B 0.033 uF Fractional-N (Med BW, <100 kHz)
Pos. C 22 uF Jitter Cleaner (Narrow BW, <1 kHz)
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3.3-V LVCMOS
Driver
Ro = 50 
LMK03318
375 
SECREF_P
125 
Configuring the EVM www.ti.com
4.4 Configuring the Reference Inputs
The LMK03318 has two reference input pairs, PRIREF and SECREF, which can be configured to accept
single-ended clock input, differential clock input, or crystal input (SECREF only). The input SMAs labeled
PRI_P and PRI_N are routed to the PRIREF inputs, and SMAs labeled SEC_P and SEC_N are routed to
the SECREF inputs. Both SMA input pairs are routed using 50-ohm single-ended traces to the input pins
of the chip.
The PRI_P and PRI_N input SMAs are DC-coupled on the EVM and have no on-board terminations at the
PRIREF input pins (high impedance inputs). By default, a LVCMOS clock input with 1.5V to 3.3V levels
can be connected to the PRI_P input for DC-coupling to the PRIREF_P input (assumes the LVCMOS
driver is source-terminated). The unused complementary input (PRIREF_N) can be tied to GND. If a
differential clock source is required, LMK03318 supports programmable 50 ohm input termination and
common-mode biasing options (through 200 kohm internal bias resistors) for either DC- or AC-coupled
inputs.
The SECREF input pins of the LMK03318 can accept a fundamental-mode crystal for the internal crystal
oscillator circuit. By default, R40 and R41 are installed to enable the onboard 50-MHz crystal (Y1), which
can be selected as the PLL reference input when using the Soft Pin Mode configurations listed in Table 6.
If a different crystal is required for the intended configuration (e.g. Register Default or Hard Pin mode
configurations), remove the original crystal on Y1 and install the new part. The new part should comply
with the recommended crystal characteristics specified in the LMK03318 datasheet. If using a crystal with
high load capacitance spec (e.g. 18 pF), external trim capacitors may be installed on C58 and C59 to
supplement the on-chip load capacitance.
The SECREF_P and SECREF_N input SMAs are AC-coupled on the EVM and have 100-ohm center-
tapped differential termination near the inputs. The input common-mode voltage is biased to 1.2 V when
tying pins 1-2 on JP16. If using a differential clock input to SEC_P and SEC_N, remove R40 and R41 to
disconnect the crystal input path and install 0 ohms on R36 and R37. If using a LVCMOS clock input with
1.5V to 2.5V levels to SEC_P, remove R40 and R41 to disconnect the crystal path, install 0 ohms on C51
and C52, and remove R33 and R34 to provide a DC-coupled, high-impedance path to the SECREF_P
input (assumes the LVCMOS driver is source-terminated). The unused complementary input (SECREF_N)
can be tied to GND. If using a 3.3-V LVCMOS clock input to SECREF_P, a voltage divider network is
required, like shown in Figure 5, to comply with the maximum single-ended input swing of 2.6 V. The
resistive divider can be installed on R29 and R33 with the shunt resistor connected to GND by tying pins
2-3 of JP16.
Figure 5. Interfacing a 3.3-V LVCMOS Clock Input to SECREF_P
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www.ti.com Configuring the EVM
4.5 Configuring the Clock Outputs
All eight clock output pairs of LMK03318 are routed via 50-ohm single-ended traces to SMA ports
(OUT[7:0]_P/_N) through AC coupling capacitors. These outputs have series resistor (0-Ωpopulated)
options. Each output pair supports AC-coupled Differential output levels with 400 mV (LVDS-like), 600 mV
(CML-like), and 800 mV (LVPECL-like) single-ended swing, HCSL output levels (programmable 50-Ωon-
chip termination), and 1.8-V LVCMOS output levels. Each channel divider output bank has its own VDDO
output supply pin that operates from 1.8 V to 3.3 V. The on-chip LDOs provide regulated power to the
output channel and provide excellent PSRR. The LVCMOS output is limited to an output high level of 1.8
V even with VDDO of 2.5 V or 3.3 V, since the LDOs step-down the output driver supply to 1.8 V
internally.
4.6 Configuring the Status Outputs
The STATUS0 and STATUS1 outputs of LMK03318 are configured as 3.3-V LVCMOS by default and are
routed via 50-ohm single-ended traces to SMA ports (STAT0 and STAT1) through AC coupling capacitors.
The status pins can also be connected to yellow LEDs (D6 and D7) through switch S3 (2 positions) to
enable or disable visual indication of the status output states. When the switch position is ON, the LED will
be lit when the STATUS output state is logic low.
4.7 Using the USB Interface Connection
The on-board MSP430F5529 USB microcontroller (U8) provides an I2C host interface to the LMK03318
slave device. The device registers can be controlled via USB using the GUI platform running on a Host
PC.
17
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EVM Quick Start Guide www.ti.com
5 EVM Quick Start Guide
The following guide allows the user to quickly configure the LMK03318 to evaluate any of the pre-
programmed Soft Pin Mode configurations.
1. Confirm the EVM Default power configuration is set per Table 2 /Figure 3 to power the LMK03318
using the on-board LDO regulators with VDD = 3.3 V and VDDO = 1.8 V.
2. Connect the 5-V lead to EXTVDD (J3, pin 1) and ground lead to GND (J3, pin 3) from a 1A-capable
power supply, and enable the 5-V output.
3. Set the Control Pin jumpers to select the desired Soft Pin Mode configuration in Table 6.
4. To use the on-board XTAL on SECREF as the reference input to the PLLs, set JP17 = HI and do not
connect any input clock to PRIREF SMAs.
5. Toggle the PDN push-button switch to restart the device in the selected mode.
6. Observe any active output clock on OUT[7:0] SMA ports or STAT[1:0] SMA ports.
(a) All clock and status outputs are AC-coupled to the SMAs.
(b) Use 50-ohm coax cables to connect the test equipment to the output SMA ports. If making a single-
ended measurement on a differential output, terminate the unused SMA port with a 50-ohm load.
(c) To minimize output clock switching noise from affecting jitter-sensitive measurements, terminate
any unused active output clock pair using 50-ohm SMA loads or connecting the 100-ohm
differential load resistors (R52 to R55, R72 to R75); otherwise, power-down unused output clocks
via register programming.
(d) Status LEDs, D6 & D7 (active low), can also be monitored for activity on STATUS pins when switch
S3 is in the “ON” position.
7. Refer to the Soft Pin Mode Control Interfaces descriptions in Table 3 for configuration of PLL reference
input selection (JP17), output SYNC (switch S4), and XTAL frequency margining (JP23, JP24, and
switch S5) features.
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Table 6. Soft Pin Mode - EEPROM Page Configurations (Default EVM EEPROM Image)
EEPROM Page Page 0 Page 1 Page 2 Page 3 Page 4 Page 5
HWCTRL (JP18) LO LO LO LO LO LO
Jumper Setting
GPIO3 (JP22) LO LO LO HI HI HI
Jumper Setting
GPIO2 (JP21) LO MID HI LO MID HI
Jumper Setting 50 MHz 50 MHz 50 MHz 50 MHz 50 MHz 50 MHz
PRIREF Input LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
50 MHz 50 MHz 50 MHz 50 MHz 50 MHz 50 MHz
SECREF Input XTAL on-board XTAL on-board XTAL on-board XTAL on-board XTAL on-board XTAL on-board
PLL Input Mux Pin Control (1) Pin Control (1) Pin Control (1) Pin Control (1) Pin Control (1) Pin Control (1)
Fractional mode Integer mode Integer mode Integer mode Integer mode Integer mode
PLL PFD = 100 MHz PFD = 100 MHz PFD = 100 MHz PFD = 100 MHz PFD = 100 MHz PFD = 100 MHz
Configuration VCO = 5.15625 VCO = 5 GHz VCO = 5 GHz VCO = 5 GHz VCO = 5.1 GHz VCO = 5.0 GHz
GHz
C2 Value 0.033 uF 3300 pF 3300 pF 3300 pF 3300 pF 3300 pF
(S1 Position ON) (Pos. B) (Pos. A) (Pos. A) (Pos. A) (Pos. A) (Pos. A)
100 MHz
161.1328125 MHz 156.25 MHz 156.25 MHz 156.25 MHz 156.25 MHz
OUT0 HCSL
LVPECL LVPECL LVPECL LVPECL LVPECL
(50Ωon-chip)
100 MHz
161.1328125 MHz 156.25 MHz 156.25 MHz 156.25 MHz 156.25 MHz
OUT1 HCSL
LVPECL LVPECL LVPECL LVPECL LVPECL
(50Ωon-chip)
100 MHz
161.1328125 MHz 156.25 MHz 125 MHz 156.25 MHz 125 MHz
OUT2 HCSL
LVPECL LVPECL LVPECL LVPECL LVPECL
(50Ωon-chip)
100 MHz
161.1328125 MHz 156.25 MHz 125 MHz 156.25 MHz 125 MHz
OUT3 HCSL
LVPECL LVPECL LVPECL LVPECL LVPECL
(50Ωon-chip)
161.1328125 MHz 156.25 MHz 125 MHz 25 MHz 100 MHz 100 MHz
OUT4 LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL
161.1328125 MHz 125 MHz 125 MHz 25 MHz 100 MHz 100 MHz
OUT5 LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL
161.1328125 MHz 125 MHz 125 MHz 25 MHz 100 MHz 25 MHz
OUT6 LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL
100 MHz
161.1328125 MHz 125 MHz 125 MHz 25 MHz 25 MHz
OUT7 LVCMOS(+/-)
LVPECL LVPECL LVPECL LVPECL LVPECL
1.8V
PRIREF loss of 25 MHz 25 MHz PLL loss of lock PLL loss of lock PLL loss of lock
STATUS0 signal LVCMOS 3.3V LVCMOS 3.3V (active low) (active low) (active low)
(active low) (active high) (active high)
25 MHz 25 MHz PRIREF loss of PRIREF loss of PRIREF loss of
PLL loss of lock
STATUS1 LVCMOS 3.3V LVCMOS 3.3V signal signal signal
(active low) (active low) (active low) (active low) (active low) (active low)
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EVM Layout www.ti.com
6 EVM Layout
Figure 6. Top Overlay
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