Texas Instruments TPS3703 User manual

TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and
Manual Reset
1 Features
• Input voltage range: 1.7 V to 5.5 V
• Undervoltage lockout (UVLO): 1.7 V
• Low quiescent current: 7 µA (Max)
• High threshold accuracy:
– ± 0.25% (typical)
– ± 0.7% (–40°C to +125°C)
• Fixed window threshold levels
– 50-mV steps from 500 mV to 1.3 V
– 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V 3.3 V, 5 V
– Available in UV threshold only
– Window tolerance available from ±3% to ±7%
• User adjustable voltage threshold levels
• Internal glitch immunity and hysteresis
• Fixed time delay options: 50 µs, 1 ms, 5 ms, 10
ms, 20 ms, 100 ms, 200 ms
• Programmable time delay option with a single
external capacitor
• Open-drain active low UV and OV monitor
• RESET voltage latching output mode
2 Applications
•Motor drives
•Factory automation and control
•Home theater and entertainment
•Grid infrastructure
•Data center and enterprise computing
RESET
VDD
SENSE MR
CT
GND
RESET
VCORE
Processor
OV Threshold
UV Threshold
Optional
TPS3703
1
Monitor Voltage
10k 
2
34
5
6
Integrated Overvoltage and Undervoltage
Detection
3 Description
The TPS3703 device is an integrated overvoltage
(OV) and undervoltage (UV) monitor or reset IC in
industry’s smallest 6-pin DSE package. This highly
accurate voltage supervisor is ideal for systems that
operate on low-voltage supply rails and have narrow
margin supply tolerances. Low threshold hysteresis
prevent false reset signals when the monitored
voltage supply is in its normal range of operation.
Internal glitch immunity and noise filters further
eliminate false resets resulting from erroneous
signals.
The TPS3703 does not require any external resistors
for setting overvoltage and undervoltage reset
thresholds, which further optimizes overall accuracy,
cost, solution size, and improves reliability for safety
systems. The Capacitor Time (CT) pin is used to
select between the two available reset time delays
designed into each device and also to adjust the reset
time delay by connecting a capacitor. A separate
SENSE input pin and VDD pin allow for the
redundancy sought by high-reliability systems.
This device has a low typical quiescent current
specification of 4.5 µA (typical). The TPS3703 is
suitable for industrial applications and applications
that require accurate undervoltage and overvoltage
monitoring.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPS3703 WSON (6) 1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIT+(OV) Accuracy (%)
Frequency (%)
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
0
5
10
15
20
25
30
35
D004
Typical Overvoltage Accuracy Distribution
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Timing Requirements .................................................7
7.7 Timing Diagrams ........................................................8
7.8 Typical Characteristics.............................................. 10
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................17
9 Application and Implementation.................................. 18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................27
10.1 Power Supply Guidelines........................................27
11 Layout........................................................................... 27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Device Nomenclature..............................................28
12.2 Documentation Support.......................................... 30
12.3 Receiving Notification of Documentation Updates..30
12.4 Support Resources................................................. 30
12.5 Trademarks.............................................................30
12.6 Electrostatic Discharge Caution..............................30
12.7 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2020) to Revision B (November 2020) Page
• Added Added VIT < 800 mV threshold option to Electrical Characteristics table ............................................... 6
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5 Device Comparison
Figure 5-1 shows the device nomenclature of the TPS3703. For all possible voltages, window tolerance, time
delays, and UV threshold options, see Table 12-1. Contact TI sales representatives or on TI's E2E forum for
details and availability of other options; minimum order quantities apply.
TPS 3703 X X XXX XXX
Time Delay Op

on
A: CT (open) 10 ms, CT (VDD) = 200 ms
B: CT (open) 1 ms, CT (VDD) = 20 ms
C: CT (open) 5 ms, CT (VDD) = 100 ms
D: CT (open) 50 µs, CT (VDD) = 50 µs
…
Nominal Threshold Op

on
050: 0.50V
...
500: 5.00V
Tolerance Op

on
3: UV/OV = 3%
4: UV/OV = 4%
5: UV/OV = 5%
6: UV/OV = 6%
7: UV/OV = 7%
Package
DSE: WSON (6-pin)
Figure 5-1. TPS3703 Device Nomenclature
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6 Pin Configuration and Functions
SENSE
VDD
CT RESET
MR
GND
Figure 6-1. DSE Package
6-Pin WSON
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 SENSE I
Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage
threshold or below the undervoltage threshold, the RESET pin is driven low. Connect to VDD pin if
monitoring VDD supply voltage.
2 VDD I Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to
this pin.
3 CT I
Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or
leaving it floating. Delay time can be programmed by connecting an external capacitor reference to
ground.
4 RESET O
Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally
overvoltage threshold (VIT+) or below the undervoltage threshold (VIT–). See the timing diagram in
Figure 8-2 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up
voltage.
5 GND — Ground
6 MR I
Manual reset (MR), pull this pin to a logic low (VMR_L) to assert a reset signal . After the MR pin is
deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not
in use.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage VDD –0.3 6 V
Voltage VRESET –0.3 6 V
Voltage VCT –0.3 6 V
Voltage VSENSE –0.3 6 V
Voltage VMR –0.3 6 V
Current IRESET ±40 mA
Temperature (2)
Continuous total power dissipation See the Thermal Information
Operating junction temperature, TJ-40 150 °C
Operating free-air temperature, TA-40 150 °C
Storage temperature, Tstg -65 150 °C
(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE UNIT
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(1) ±750
(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VDD Supply pin voltage 1.7 5.5 V
VSENSE Input pin voltage 0 5.5 V
VCT CT pin voltage (1) (3) VDD V
VRESET Output pin voltage 0 5.5 V
VMR MR pin Voltage (2) 0 5.5 V
IRESET Output pin current 0.3 10 mA
TJJunction temperature (free-air temperature) -40 125 ℃
(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(3) The maximum rating is VDD or 5.5 V, whichever is smaller.
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7.4 Thermal Information
THERMAL METRIC(1)
TPS3703
UNITDSE (WSON)
PINS
RθJA Junction-to-ambient thermal resistance 184.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 30.6 °C/W
RθJB Junction-to-board thermal resistance 86.4 °C/W
ΨJT Junction-to-top characterization parameter 13.4 °C/W
ΨJB Junction-to-board characterization parameter 86.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply Voltage 1.7 5.5 V
UVLO Under Voltage Lockout(3) VDD falling below 1.7 V 1.2 1.7 V
VPOR Power on reset voltage(2) VOL(max) = 0.25 V, IOUT = 15 µA 1 V
VIT+(OV) Positive- going threshold accuracy -0.7 ±0.25 0.7 %
VIT-(UV) Negative-going threshold accuracy -0.7 ±0.25 0.7 %
VHYS Hysteresis Voltage(1) 0.3 0.55 0.8 %
VIT+(OV) Positive- going threshold accuracy VIT < 800 mV -1 1 %
VIT-(UV) Negative-going threshold accuracy VIT < 800 mV -1 1 %
VHYS Hysteresis Voltage(1) VIT < 800 mV 0.2 0.7 %
IDD Supply current VDD ≤ 5.5 V 4.5 7 µA
ISENSE Input current, SENSE pin VSENSE = 5 V 1 1.5 µA
VOL Low level output voltage
VDD = 1.7 V, IOUT = 0.4 mA 250 mV
VDD = 2 V, IOUT = 3 mA 250 mV
VDD = 5 V, IOUT = 5 mA 250 mV
ILKG Open drain output leakage current VDD = VRESET = 5.5 V 300 nA
VMR_L MR logic low input 0.3 V
VMR_H MR logic high input 1.4 V
VCT_H High level CT pin voltage 1.4 V
RMR Manual reset Internal pullup resistance 100 KΩ
ICT CT pin charge current 337 375 413 nA
VCT CT pin comparator threshold voltage(4) 1.133 1.15 1.167 V
(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(2) VPOR is the minimum VDD voltage level for a controlled output state.
(3) RESET pin is driven low when VDD falls below UVLO.
(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.
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7.6 Timing Requirements
At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.
PARAMETER TEST
CONDITIONS MIN NOM MAX UNIT
tDReset time delay, TPS3703A, TPS3703E CT = Open 7 10 13 ms
tDReset time delay, TPS3703A, TPS3703E CT = 10 kΩ to VDD 140 200 260 ms
tDReset time delay, TPS3703B, TPS3703F CT = Open 0.7 1 1.3 ms
tDReset time delay, TPS3703B, TPS3703F CT = 10 kΩ to VDD 14 20 26 ms
tDReset time delay, TPS3703C, TPS3703G CT = Open 3.5 5 6.5 ms
tDReset time delay, TPS3703C, TPS3703G CT = 10 kΩ to VDD 70 100 130 ms
tDReset time delay, TPS3703D, TPS3703H CT = 10 kΩ to VDD
CT = Open 50 µs
tPD Propagation detect delay(1) (2) 15 30 µs
tROutput rise time(1) (3) 2.2 µs
tFOutput fall time(1) (3) 0.2 µs
tSD Startup delay(4) 300 µs
tGI (VIT-) Glitch Immunity undervoltage VIT-(UV), 5% Overdrive(1) 3.5 µs
tGI (VIT+) Glitch Immunity overvoltage VIT+(OV), 5% Overdrive(1) 3.5 µs
tGI (MR) Glitch Immunity MR pin 25 ns
tPD (MR) Propagation delay from MR low to assert RESET 500 ns
tMR_W MR pin pulse width duration to assert RESET 1 µs
tD (MR) MR reset time delay tDms
(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT] / VIT; Where VIT stands for VIT-(UV) or VIT+(OV)
(2) tPD measured from threhold trip point (VIT-(UV) or VIT+(OV)) to RESET VOL voltage
(3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tD before the output is in the correct state.
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7.7 Timing Diagrams
Tolerance[-3% to -7%] Tolerance[+3% to +7%]
[ -1.5% = -0.7%-0.8%) ] 0.5%
[ -1.0% = -0.7%-0.3%) ]
[ -1.25% = -0.7%-0.55%) ]
VIT+(OV)
[0.55%]
VIT+(OV) - VHYS
[-0.8%]
[-0.3%]
[-0.55%] Hys band for VIT+(OV)
[0.7%]
[0.55%] [0.55%]
[ -0.1% = 0.7%-0.8%) ]
0.5%
[ 0.4% = 0.7%-0.3%) ]
[ 0.15% = 0.7%-0.55%) ]
Overdrive[2.5%] above VIT+(OV)
[0.25%]
[-0.25%]
[0.55%]
[0.55%]
Hys band for VIT-(UV)
VIT-(UV) [ 0.1% = -0.7%+0.8%) ]
[ -0.4% = -0.7%+0.3% ]
[ -0.15% = -0.7%+0.55%) ]
[0.8%]
[0.3%]
[0.55%]
[ 1.0% = 0.7%+0.3%) ]
[ 1.25% = 0.7%+0.55%) ]
Overdrive [2.5%] below VIT-(UV)
VIT-(UV) + VHYS
0.5%
0.5%
[0.55%]
[0.7%]
Figure 7-1. Voltage Threshold and Hysteresis Accuracy
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tD
VIT
Hysteresis
Hysteresis
tD tPD
Undefined
tPD
tD
tSD
VPOR
UVLO
VDD(MIN)
VDD
SENSE
VIT+(OV)
VIT+(OV) - VHYS
VIT-(UV) + VHYS
VIT-(UV)
RESET
Figure 7-2. SENSE Timing Diagram
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7.8 Typical Characteristics
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
D001
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
Tested across multiple voltage options
Figure 7-3. Undervoltage Accuracy vs Temperature
Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
D002
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
Tested across multiple voltage options
Figure 7-4. Overvoltage Accuracy vs Temperature
VIT-(UV) Accuracy (%)
Frequency (%)
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
0
5
10
15
20
25
30
35
D003
Sample Size of 100 TPS3703A7125 units
Figure 7-5. Undervoltage Accuracy Distribution
VIT+(OV) Accuracy (%)
Frequency (%)
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
0
5
10
15
20
25
30
35
D004
Sample Size of 100 TPS3703A7125 units
Figure 7-6. Overvoltage Accuracy Distribution
Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
0.5
0.52
0.54
0.56
0.58
0.6
D005
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
Tested across multiple voltage options
Figure 7-7. Undervoltage Hysteresis Voltage Accuracy vs
Temperature
Temperature (qC)
Accuracy (%)
-50 -25 0 25 50 75 100 125
0.5
0.52
0.54
0.56
0.58
0.6
D006
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
Tested across multiple voltage options
Figure 7-8. Overvoltage Hysteresis Voltage Accuracy vs
Temperature
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