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Texas Instruments INA851EVM User manual

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User’s Guide
INA851 Evaluation Module
ABSTRACT
This user's guide contains information and support documentation for the INA851 evaluation module (EVM).
Included are the circuit description, jumper settings, required connections, printed circuit board (PCB) layout,
schematic, and bill of materials of the INA851EVM. Throughout this document, the terms evaluation board,
evaluation module, and EVM are synonymous with the INA851EVM.
www.ti.com
SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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INA851 Evaluation Module 1
Copyright © 2022 Texas Instruments Incorporated
Table of Contents
1 Overview..................................................................................................................................................................................3
1.1 Related Documentation......................................................................................................................................................3
1.2 Electrostatic Discharge Caution......................................................................................................................................... 3
1.3 Hot Surface Warning..........................................................................................................................................................3
2 EVM Circuit Description.........................................................................................................................................................4
3 Jumper Settings......................................................................................................................................................................5
4 Power-Supply Connections................................................................................................................................................... 6
5 Input and Output Connections.............................................................................................................................................. 7
6 Modifications...........................................................................................................................................................................9
7 Schematic, PCB Layout, and Bill of Materials......................................................................................................................9
7.1 Schematic.......................................................................................................................................................................... 9
7.2 PCB Layout........................................................................................................................................................................ 9
7.3 Bill of Materials.................................................................................................................................................................15
8 Revision History................................................................................................................................................................... 16
List of Figures
Figure 2-1. INA851EVM Simplified Schematic............................................................................................................................ 4
Figure 3-1. INA851EVM Default Jumper Settings....................................................................................................................... 5
Figure 4-1. INA851EVM Voltage Supply Connections.................................................................................................................6
Figure 5-1. INA851EVM Input and Output Connections..............................................................................................................7
Figure 7-1. INA851EVM Schematic.............................................................................................................................................9
Figure 7-2. Top Overlay PCB Layout.........................................................................................................................................10
Figure 7-3. Top Layer PCB Layout.............................................................................................................................................11
Figure 7-4. Ground Layer PCB Layout...................................................................................................................................... 12
Figure 7-5. Power Layer PCB Layout........................................................................................................................................ 13
Figure 7-6. Bottom Layer PCB Layout.......................................................................................................................................14
List of Tables
Table 1-1. Related Documentation.............................................................................................................................................. 3
Table 3-1. Default Jumper Configuration..................................................................................................................................... 5
Table 4-1. INA851EVM Supply-Range Specifications................................................................................................................. 6
Table 5-1. INA851EVM Input and Output Connections............................................................................................................... 8
Table 7-1. INA851EVM Bill of Materials.....................................................................................................................................15
Trademarks
All trademarks are the property of their respective owners.
Table of Contents www.ti.com
2INA851 Evaluation Module SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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Copyright © 2022 Texas Instruments Incorporated
1 Overview
The INA851 is a high-precision instrumentation amplifier with differential outputs that is optimized to drive
high-performance analog-to-digital converters (ADCs) with fully differential inputs. A single external resistor sets
any gain from 0.2 V/V to 10,000 V/V. The device features super-beta input transistors from Texas Instruments,
which provide ultra-low input offset voltage, offset drift, input bias current, input voltage noise, and current noise.
For a full list of electrical characteristics for the INA851, see the INA851 Precision, Fully Differential Output,
Instrumentation Amplifier data sheet.
1.1 Related Documentation
The following document provides information regarding Texas Instruments integrated circuits used in the
assembly of the INA851EVM. This user's guide is available from the TI website under literature number
SBOU273. Any letter appended to the literature number corresponds to the document revision that is current at
the time of the writing of this document. Newer revisions are available from the TI website at https://www.ti.com/,
or call the Texas Instruments Literature Response Center at (800) 477-8924 or the Product Information Center at
(972) 644-5580. When ordering, identify the document by both title and literature number.
Table 1-1. Related Documentation
Device Literature Number
INA851 SBOS999
1.2 Electrostatic Discharge Caution
CAUTION
Many of the components on the INA851EVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and
handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
1.3 Hot Surface Warning
WARNING
Device can become hot under high-current conditions. Take care when handling the EVM.
www.ti.com Overview
SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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INA851 Evaluation Module 3
Copyright © 2022 Texas Instruments Incorporated
2 EVM Circuit Description
This EVM provides access to the features and measures the performance of the INA851. By default, the
INA851EVM instrumentation amplifier is configured to a gain of 1 V/V. The evaluation board provides optional
footprints for gain resistors RG1 and RG2 to modify the input-stage instrumentation-amplifier gain. Optional
footprints R5 and R9 can be populated with 0-Ω jumpers to set the output stage gain to 0.2 V/V.
The INA851 incorporates features that simplify interfacing to a fully-differential ADC. The VOCM connector
sets the output common-mode voltage. If the VOCM connector is not driven, the output common-mode voltage
defaults to the INA851 midsupply value. Clamp pins are provided to limit the INA851 output voltage level,
which can be applied to the ADC inputs. The output clamp pins, VCLAMP+ and VCLAMP–, are accessible
using connector J9. Selectable jumpers J11 and J12 set the output clamp voltage level to the INA851 supplies
(default), or to external voltages using connector J9.
Revision A of the INA851EVM allows access to the FDA_IN– and FDA_IN+ pins with optional capacitors C7
and C18. These capacitors are in parallel with the INA851 output stage internal feedback resistors to implement
noise filtering. A simplified block diagram of the INA851EVM is displayed in Figure 2-1. For a full schematic of
the INA851EVM, see Figure 7-1.
U1 INA851RGT
+
3 k

+
–
3 k

+
–+
5 k

5 k

5 k

1.25 k

5 k

1.25 k

Output
Clamp
D1
36 V
SMA
Connector
J6
J3
SMA
Connector
IN–
RG–
IN+
RG+
VS+
VS– VCLAMP–
VCLAMP+
G02+
G02–
OUT+
OUT–
FDA_IN–
FDA_IN+
VCC
VEE
IN+
IN–
R11 100

R2 100

C12
C9
C15
100 pF
10pF
10pF
R5
R10 100

C13
100 pF
RG1 DNP
J5.4
J5.1
J5.3
J5.2
Output
Connector
OUT+
OUT–
DNP
R9 DNP
DNP
DNP
C7
C18
VCC C17
100 nF
VEE
VCLAMP+
VCLAMP–
100 nF
Vclamp+_ext 1
2
3
100 nF
Vclamp-_ext
J9.1
J9.2
J9.4
J9.3
VCC
VCLAMP+
J11
1
2
3
VEE
VCLAMP–
J12
C6
100 nF
C19
C20
VOCM
VCCVEE
VCC
VEE
Vclamp
Connector
J10.1
J10.2
VCC
VEE
R1
VOCM
Connector
Output
Clamp
D2
D3
1
2
3
J7
1
2
3
J4
C5
100 nF
R4 100

J1.1
J1.2
J1.3
Power Supply
Connector
VCC
VEE
C1
10 µF
C3
10 µF
C2
100 nF
C4
100 nF
–
–
100

R18
10 k

R19
10 k

FDA_IN–
FDA_IN–
FDA_IN+
FDA_IN+
Figure 2-1. INA851EVM Simplified Schematic
EVM Circuit Description www.ti.com
4INA851 Evaluation Module SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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Copyright © 2022 Texas Instruments Incorporated
3 Jumper Settings
Figure 3-1 details the default jumper settings of the INA851EVM. Table 3-1 explains the configuration for these
jumpers.
Figure 3-1. INA851EVM Default Jumper Settings
Table 3-1. Default Jumper Configuration
Jumper Function Default Position Description
J4 Positive (noninverting) input, IN+ Shunt 2-3 Shunt 2-3: Input signal to SMA connector J3
Shunt 1-2 connects IN+ to GND
J7 Negative (inverting) input, IN– Shunt 2-3 Shunt 2-3: Input signal to SMA connector J6
Shunt 1-2 connects IN– to GND
J11 VCLAMP+ connection Shunt 1-2 Shunt 1-2: Sets level of output VCLAMP+ to +VCC supply
Shunt 2-3 connects VCLAMP+ to external connector J9 pin 3
J12 VCLAMP– connection Shunt 1-2 Shunt 1-2: Sets level of output VCLAMP-to-VEE supply
Shunt 2-3 connects VCLAMP– to external connector J9 pin 1
www.ti.com Jumper Settings
SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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INA851 Evaluation Module 5
Copyright © 2022 Texas Instruments Incorporated
4 Power-Supply Connections
The power-supply connections for the INA851EVM are provided through connector J1 at the top of the EVM.
The positive power-supply connection is labeled +VCC, the negative power-supply connection is labeled –VEE,
and the ground connection is labeled GND. To connect power to the INA851EVM, insert wires into each terminal
of J1 and then tighten the screws to make the connection. Table 4-1 summarizes the pin definition for supply
connector J1 and the allowed voltage range for each supply connection.
Table 4-1. INA851EVM Supply-Range Specifications
Pin Number Supply Connection Voltage Range
J1.3 Positive supply (+VCC) Single supply, VS = (+VCC): 8 V to 36 V
Dual supply, VS = (+VCC) – (–VEE): 4 V to 18 V
J1.2 Ground 0 V
J1.1 Negative supply (–VEE) Single supply, VS = (+VCC): 0 V (GND)
Dual supply, VS = (+VCC) – (–VEE): –4 V to –18 V
Figure 4-1 shows the INA851EVM voltage supply connections.
1
3
J1
Power-Supply
Connector C1
10 µF D1
36 V
C2
100 nF
2
TP1
VCC
VCC
TP3
GND
C3
10 µF
C4
100 nF
VEE
TP2
VEE
U1 INA851RGT
+
3 k

+
–
3 k

+
–+
5 k

5 k

5 k

1.25 k

5 k

1.25 k

Output
Clamp
IN–
RG–
IN+
RG+
VS+
VS– VCLAMP–
VCLAMP+
G02+
G02–
OUT+
OUT–
FDA_IN–
VCC C17
100 nF
C6
100 nF
VOCM
Output
Clamp
–
–
VEE
FDA_IN+
Figure 4-1. INA851EVM Voltage Supply Connections
Power-Supply Connections www.ti.com
6INA851 Evaluation Module SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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Copyright © 2022 Texas Instruments Incorporated
5 Input and Output Connections
The instrumentation amplifier input signal connections for the INA851EVM are provided through the use of SMA
connectors J3, J6, and test points TP5, TP7, located at the left of the EVM. The VOCM input is provided through
screw-terminal connector J10, located on the left of the board.
By default, the output clamp voltage levels, VCLAMP+ and VCLAMP–, are set to the INA851 positive (+VCC)
and negative (–VEE) supplies, respectively. The VCLAMP+ pin is connected to +VCC through jumper J11 1-2,
and the VCLAMP– pin is connected to –VEE through J12 1-2. Screw terminal connector J9 provides access to
the output clamp pins. To set the voltage level of the clamps with an external supply, shunt jumper J11 2-3 to
access the VCLAMP+ using connector J9.1. In a similar fashion, shunt jumper J12 2-3 to access the VCLAMP–
pin using connector J9.3.
The differential output amplifier connections are provided through screw-terminal connector J5, SMA connectors
J2 and J8, and test points TP6 and TP8, located at the right side of the EVM. A simplified diagram of the
INA851EVM input and output connections is displayed in Figure 5-1.
U1 INA851RGT
+
–
3 k

+
–
3 k

+
–+
–
5 k

5 k

5 k

1.25 k

Output
Clamp
SMA
Connector
J6
J3
SMA
Connector
IN–
RG–
IN+
RG+
VS+
VS– VCLAMP–
VCLAMP+
G02+
G02–
OUT+
OUT–
IN+
IN–
C12
100 pF
R5
R9
C13
100pF
RG1 DNP
J5.4
J5.1
J5.3
J5.2
Output
Connector
OUT+
OUT–
DNP
DNP
VCC
C17
100 nF
VEE
VCLAMP+
VCLAMP–
100 nF
Vclamp+_ext 1
2
3
100 nF
Vclamp– _ext
J9.1
J9.2
J9.4
J9.3
VCC
VCLAMP+
J11
C6
100 nF
C19
C20
VOCM
VCCVEE
VCC
VEE
Vclamp
Connector
J10.1
J10.2
VCC
VEE
100 nF
R1
VOCM
Connector
Output
Clamp
TP7
TP5
J2
SMA
Output
Connector
TP6
J8
SMA
Output
Connector
TP8
OUT+
OUT–
TP11
1
2
3
VEE
VCLAMP–
J12
VCLAMP+
TP12
VCLAMP–
TP4
GND
TP9
GND
TP13
TP10
C5
D2
D3
R2
100 Ω
R11
100 Ω
1.25 kΩ
5 kΩ
R4 100 Ω
R10 100 Ω
R19
10 kΩ
R18
10 kΩ
100 Ω
DNP
C7
FDA_IN–
DNP
C18
FDA_IN+
FDA_IN+
FDA_IN–
FDA_IN–
FDA_IN+
C9
10pF
C15
10pF
Figure 5-1. INA851EVM Input and Output Connections
www.ti.com Input and Output Connections
SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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INA851 Evaluation Module 7
Copyright © 2022 Texas Instruments Incorporated
Table 5-1 summarizes the input and output connectors and corresponding test points.
Table 5-1. INA851EVM Input and Output Connections
Connector
Designator Signal Comment Test Point
J3 IN+ SMA TP5
J6 IN– SMA TP7
J2 OUT+ SMA TP6
J8 OUT– SMA TP8
J5.4 OUT+ Screw terminal TP6
J5.3 GND Screw terminal TP4
J5.2 GND Screw terminal TP9
J5.1 OUT– Screw terminal TP8
J10.1 VOCM Screw terminal TP13
J10.2 GND Screw terminal N/A
J9.1 VCLAMP+ external Screw terminal N/A
J9.2 GND Screw terminal N/A
J9.3 VCLAMP– external Screw terminal N/A
J9.4 GND Screw terminal N/A
Input and Output Connections www.ti.com
8INA851 Evaluation Module SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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Copyright © 2022 Texas Instruments Incorporated
6 Modifications
By default, the INA851EVM is populated with the INA851 device configured in gain of 1 V/V. However, for
flexibility, the PCB layout has additional unpopulated, passive component footprints for gain resistors RG1 and
RG2 to set the front-end amplifier gain. Optional footprints for jumper resistors R5 and R6 are provided to set
the output stage to gain of 0.2 V/V. In addition, the evaluation board provides footprints R3, R12, C10, C8, and
C14 for optional input low-pass filters, and footprints for load resistors R6 and R13. These additional component
footprints in the layout allow the user to customize the evaluation circuit. For a full schematic of the INA851EVM,
see Figure 7-1.
7 Schematic, PCB Layout, and Bill of Materials
This section contains the schematic, PCB layout, and bill of materials for the INA851EVM.
7.1 Schematic
Figure 7-1 illustrates the EVM schematic.
GND
GND
TP6
OUT+
TP8
OUT-
GND
GND
Gain 0.2 (+)
Gain 0.2 (-)
0R15
0R17
VClamp+_ext
VClamp-_ext
GND GND
Note: R6, R13, are not populated, for flexibility
1
2
3
4
5
J3
1
2
3
4
5
J6
TP5
IN+
1
2
3
J4
GND
1
2
3
J7
GND
0R3
0R12
10uF
C1
100nF
C2
GND
1
2
3
J1
10uF
C3
100nF
C4
VCC
VEE
TP9
GND
GND
TP4
GND
GND
1
2
3
4
5
J2
GND
1
2
3
4
5
J8
GND
TP13
VOCM 10.0k
R18
10.0k
R19
VEE
VCC
VOCM1
2
J10
GND
VEE
VCC
GND
GND
GND
TP11
Vclmp+
TP12
Vclmp-
100nF
C19
GND
100nF
C20
GND
VCC
VEE
TP1
VCC
TP2
VEE
VEE
100
R4
100
R10
100
R2
100
R11
1.00k
R13
1.00k
R6
GNDGND
0R5
0
RG2
0
RG1
C0G/NP0
100pF
C7
C0G/NP0
100pF
C18
TP7
IN- 0R9
100nF
50V
C6
100nF
50V
C17
GND
100nF
50V
C5
100
R1
VOCM
VCC
VEE
36V
D1
Note: RG1, RG2, R5, R9 are not populated, for flexibility
Note: C7, C8, C10, C14, C18 are not populated, for flexibility
TP10
GND
GND
TP3
GND
GND
50V
10pF
50V
10pF
C15
50V
10pF
C8
50V
10pF
C14
100V
100pF
C13
50V
10pF
C11
50V
10pF
C16
100V
100pF
C10
100V
100pF
C12
1
2
3
J11
Vclamp- to Vee
Vclamp- to Ext
Vclamp+ to Ext
Vclamp+ to Vcc
0R14
VEE
1
2
3
J12
0R16
4
1
10
147
RG-
2
RG+
3
13
11
+
-
-
VOCM
12
9
INA851RGT
U1A
Vclamp+
16
Vclamp-
5FDA_IN+ 6
NC 8
FDA_IN- 15
EP 17
INA851RGT
U1B
1
2
3
4
1
2
3
4
J5
1
2
3
4
1
2
3
4
J9
1 2
3
D2
VCC
VEE
1 2
3
D3
VCC
DNP
DNP
DNP DNP
DNP
DNP
DNP
DNP
DNP
FDA_IN+
FDA_IN-
FDA_IN-
C9
DNP
DNP
FDA_IN+
Note: Rev A, Final Release
CDSOD323-T36S
BAT853SWF
BAT853SWF
Note: DNP components are not populated.
Figure 7-1. INA851EVM Schematic
7.2 PCB Layout
The INA851EVM is a four-layer PCB design. Figure 7-2 to Figure 7-6 show the PCB layer illustrations. The
top layer consists of all signal path traces, and is poured with a solid ground plane. A symmetrical board
layout is used at the differential inputs and outputs to keep good performance matching and improve common-
mode noise rejection. Route traces as symmetrically as possible for both positive and negative pathways.
Gain resistors RG1 and RG2 are placed on the top layer in close proximity to the device to reduce parasitic
capacitance. Capacitor C5 is placed in close proximity to VOCM to avoid injecting common-mode noise.
Decoupling capacitors C6, and C17 are positioned on the top layer as close as possible to the power-supply
pins of the device. The second internal layer is a dedicated solid GND plane. Independent vias are placed at the
ground connection of every component to provide a low-impedance path to ground. The third internal layer and
bottom layer route the power supplies and the VCLAMP+ and VCLAMP– connections.
www.ti.com Modifications
SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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INA851 Evaluation Module 9
Copyright © 2022 Texas Instruments Incorporated
Figure 7-2. Top Overlay PCB Layout
Schematic, PCB Layout, and Bill of Materials www.ti.com
10 INA851 Evaluation Module SBOU273A – FEBRUARY 2022 – REVISED NOVEMBER 2022
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Copyright © 2022 Texas Instruments Incorporated