Toshiba TX39 Series User manual

Users Manual
32bit RISC Microprocessor
TX39 family
TMPR3904F
Rev.2.0
Jan. 12. 1998

1INTRODUCTION ..........................................................................................................................................1
1.1 Overview..............................................................................................................................................1
1.2 Notation used in this manual ................................................................................................................2
1.3 Kind of accessing by the TX3904..............................................................................................3
1.4 Precautions in the TMPR3904F specification.......................................................................4
2FEATURES..................................................................................................................................................7
3CONFIGURATION......................................................................................................................................9
4PINS ...........................................................................................................................................................11
4.1 Positions of Pins...........................................................................................................................11
4.2 Functions of Pins.........................................................................................................................13
5ADDRESS MAPS......................................................................................................................................17
5.1 Memory Map..................................................................................................................................17
5.2 Register Map..................................................................................................................................18
5.3 Chip Configuration Register.....................................................................................................21
5.3.1 DMA transfer of SIO .........................................................................................................21
5.3.2 PIO2 and PIO1....................................................................................................................22
5.3.3 Error processing...................................................................................................................23
5.3.4 Connection of external bus master.............................................................................................24
5.3.5 INT[7:0] active status clear.............................................................................................24
5.3.6 INT[7:0] active status set-up..........................................................................................25
6 CLOCK.........................................................................................................................................................26
6.1 Clock Generator.................................................................................................................................27
6.2 Operation Modes of TX3904.............................................................................................................27
6.2.1 Normal mode .............................................................................................................................27
6.2.2 Halt mode...................................................................................................................................27
6.2.3 Doze mode.................................................................................................................................28
6.2.4 RF (Reduced Frequency) mode .................................................................................................28
6.3 Status Shifting....................................................................................................................................29
6.4 Operations of each block in the each modes......................................................................................30
7BUS OPERATIONS.....................................................................................................................................31
7.1 Basic Bus Operations.........................................................................................................................31
7.1.1 System chip select.....................................................................................................................31
7.1.2 Single read operation .................................................................................................................35
7.1.3 Burst read operation..................................................................................................................37
7.1.4 Single write operation...............................................................................................................39
7.2 Bus Error............................................................................................................................................41
7.2.1 BUSERR* signal ......................................................................................................................41

7.2.2 Absence register access.............................................................................................................41
7.2.3 Time-out error...........................................................................................................................41
7.3 16-bit Bus Mode.................................................................................................................................43
7.4 Half Speed Bus Mode........................................................................................................................45
7.5 Bus Arbitration...................................................................................................................................46
7.5.1 Bus ownership granted..............................................................................................................46
7.5.2 Release of bus ownership..........................................................................................................47
7.5.3 Kinds of bus ownership ............................................................................................................48
7.5.4 Snoop function...........................................................................................................................49
7.6 Interrupts...........................................................................................................................................50
7.6.1 INT[7:0]....................................................................................................................................50
7.6.2 NMI*.........................................................................................................................................50
7.7 Reset...................................................................................................................................................50
8DRAM CONTROLLER (DRAMC).............................................................................................................51
8.1 Features..............................................................................................................................................51
8.2 Block Diagrams..................................................................................................................................52
8.3 Registers.............................................................................................................................................53
8.4 Explanations of Registers...................................................................................................................54
8.4.1 Channel control register 0 (DCCR0) .........................................................................................54
8.4.2 Base address mask register 0 (DBMR0)....................................................................................56
8.4.3 Wait register 0 (DWR0).............................................................................................................57
8.4.4 Channel control register 1 (DCCR1) .........................................................................................59
8.4.5 Base address mask register 1 (DBMR1)....................................................................................61
8.4.6 Wait register 1 (DWR1).............................................................................................................62
8.4.7 Refresh control register (DREFC).............................................................................................64
8.5 Operations..........................................................................................................................................65
8.5.1 Channel select............................................................................................................................65
8.5.2 Address multiplex......................................................................................................................66
8.5.3 Operation modes........................................................................................................................67
8.5.4 32/16-bit static bus sizing ..........................................................................................................68
8.5.5 Support for external bus master.................................................................................................68
8.5.6 Support for half speed bus .........................................................................................................68
8.5.7 Page mode support and page hit detection................................................................................69
8.5.8 Column address counter.............................................................................................................69
8.5.9 Timing control ..........................................................................................................................69
8.5.10 Refresh timing..........................................................................................................................69
8.5.11 Arbiter......................................................................................................................................70

8.5.12 Operations at the time of reset.................................................................................................70
8.6 Timing Diagrams...............................................................................................................................71
8.6.1 32-bit bus single read operation.................................................................................................71
8.6.2 32-bit word single read operation with 16-bit bus.....................................................................74
8.6.3 32-bit bus fast page mode read (Burst mode)............................................................................75
8.6.4 16-bit bus fast page mode word read (Burst read).....................................................................75
8.6.5 32-bit bus fast page mode read (Burst read) page hit miss ........................................................76
8.6.6 32-bit bus hyper page mode read (Burst read)...........................................................................77
8.6.7 32-bit bus hyper page mode read (Page hit miss)......................................................................77
8.6.8 32-bit bus single write (Early write)..........................................................................................78
8.6.9 32-bit bus fast page mode write (Early write)............................................................................81
8.6.10 32-bit bus hyper page mode write (Early write)......................................................................81
8.6.11 CBR refresh.............................................................................................................................82
8.7 External Circuit Connections.............................................................................................................83
9ROM CONTROLLER (ROMC)...................................................................................................................85
9.1 Features..............................................................................................................................................85
9.2 Block Diagrams..................................................................................................................................86
9.3 Registers.............................................................................................................................................87
9.3.1 Channel control register 0..........................................................................................................88
9.3.2 Channel control register 1..........................................................................................................90
9.3.3 Base address mask register 0 .....................................................................................................92
9.3.4 Base address mask register 1 .....................................................................................................93
9.4 Operations..........................................................................................................................................94
9.4.1 Channel select............................................................................................................................94
9.4.2 Operation Modes........................................................................................................................96
9.4.3 32/16-bit Static Bus Sizing ........................................................................................................97
9.4.4 16-bit Bus Access ......................................................................................................................97
9.4.5 Access by External Bus Master .................................................................................................97
9.4.6 Page mode support.....................................................................................................................97
9.5 Timing Diagrams...............................................................................................................................98
9.5.1 32-bit bus single read operation (ROM/SRAM)........................................................................98
9.5.2 16-bit bus single read (32-bit word) operation (ROM/SRAM)................................................101
9.5.3 16-bit bus single read (half word) operation (ROM/SRAM)...................................................102
9.5.4 32-bit bus single write operation (SRAM/Flush).....................................................................102
9.5.5 16-bit bus single write (word) operation (SRAM/Flush).........................................................104
9.5.6 16-bit bus single write (half word) operation (SRAM/Flush)..................................................104
9.5.7 32-bit bus normal mode burst read operation (ROM/SRAM) ................................................105

9.5.8 32-bit bus page mode burst read operation (Page mode MROM) ...........................................106
9.5.9 16-bit bus word normal mode burst read operation (ROM/SRAM)........................................107
9.5.10 16-bit bus page mode burst read (word) operation (Page mode MROM) .............................108
9.5.11 32-bit bus normal mode burst write (SRAM)........................................................................109
9.5.12 16-bit bus normal mode burst write (word) (SRAM; WE control write)...............................110
9.5.13 16-bit bus normal mode burst write (half word) (SRAM; WE control).................................111
9.6 Examples of MROM/EPROM Usage..............................................................................................112
9.7 Examples of SRAM Usage..............................................................................................................114
10 DMA CONTROLLER (DMAC)................................................................................................................116
10.1 Features............................................................................................................................................116
10.2 Configuration...................................................................................................................................117
10.2.1TX3904 internal connection .............................................................................................................117
10.2.2DMAC internal blocks......................................................................................................................118
10.2.3 Priority between modules.................................................................................................................118
10.3 Registers...........................................................................................................................................120
10.3.1 DMA control register (DCR).................................................................................................121
10.3.2 Channel control register (CCRn)...........................................................................................122
10.3.3 Channel status register (CSRn)..............................................................................................126
10.3.4 Source address register (SARn).............................................................................................129
10.3.5 Destination address register (DARn).....................................................................................130
10.3.6 Byte count register (BCR0n) .................................................................................................131
10.3.7 Next byte count register (NCR0/1)........................................................................................132
10.3.8 Data holding register (DHR) .................................................................................................133
10.4 Functions..........................................................................................................................................134
10.4.1 Overview................................................................................................................................134
10.4.2 Transfer requests....................................................................................................................138
10.4.3 Address modes.......................................................................................................................142
10.4.4 Burst transfer .........................................................................................................................147
10.4.5 Continue mode.......................................................................................................................147
10.4.6 Channel operation..................................................................................................................148
10.4.7 Endian switch function ..........................................................................................................152
10.5 Operations........................................................................................................................................153
10.5.1 Dual address mode.................................................................................................................153
10.5.2 Single address mode ..............................................................................................................156
10.5.3 Input of DONE* signal..........................................................................................................159
10.5.4 Output of DONE* signal .......................................................................................................160
10.5.5 Note for DRAM refresh during DMA...................................................................................160

11 INTERRUPTS ............................................................................................................................................162
11.1 Features............................................................................................................................................162
11.2 Configuration...................................................................................................................................163
11.3 Functions..........................................................................................................................................164
11.3.1 Interrupt sources ....................................................................................................................164
11.3.2 Interrupt detection..................................................................................................................165
11.3.3 Interrupt priority arbitration process......................................................................................165
11.4 Registers...........................................................................................................................................166
11.4.1 Register map..........................................................................................................................166
11.4.2 Interrupt status register (ISR) ................................................................................................167
11.4.3 Interrupt level registers (ILR3-ILR0) ....................................................................................168
11.4.4 Interrupt mask register (IMR)................................................................................................169
12 SERIAL PORTS (SIO)...............................................................................................................................170
12.1 Features............................................................................................................................................170
12.2 Block Diagrams................................................................................................................................170
12.3 Registers...........................................................................................................................................172
12.3.1 Line control register (SLCRn)...............................................................................................173
12.3.2 Line status register (SLSRn)..................................................................................................175
12.3.3 DMA/Interrupt control register (SDICRn) ............................................................................176
12.3.4 DMA/Interrupt status register (SDISRn)...............................................................................178
12.3.5 FIFO control register (SFCRn).............................................................................................180
12.3.6 Baudrate control register (SBGRn)........................................................................................181
12.3.7 Transmit FIFO buffer (TFIFOn)............................................................................................182
12.3.8 Receive FIFO buffer (SFIFOn)..............................................................................................182
12.4 Operations........................................................................................................................................183
12.4.1 Overview................................................................................................................................183
12.4.2 Data format............................................................................................................................183
12.4.3 Serial clock generator............................................................................................................185
12.4.4 Baudrate generator.................................................................................................................185
12.4.5 Receiver Controller................................................................................................................187
12.4.6 Receiver shift register............................................................................................................187
12.4.7 Receiver read buffer...............................................................................................................187
12.4.8 Transmitter controller............................................................................................................187
12.4.9 Transmitter shift register........................................................................................................187
12.4.10 Host I/F................................................................................................................................187
12.4.11 Hand shake function ............................................................................................................188
12.4.12 Parity control........................................................................................................................189

12.4.13 Error flag..............................................................................................................................189
12.4.14 Multi-controller system........................................................................................................189
12.5 Timing Explanations........................................................................................................................191
12.5.1 Operation at the time of receiving (7 and 8 bit data length) ..................................................191
12.5.2 Timing of SDMAREQ*/SMAACK* at the time of DMA I/F (at DMA level 4)..................191
12.5.3 Operation at the time of receiving (8 and 9 bit length multi-controller system;....................192
12.5.4 Operation at the time of receiving (8 and 9 bit length multi-controller system;....................192
12.5.5 Operation at the time of receiving (8 and 9 bit length multi-controller system;....................193
12.5.6 Operation at the time of transmitting.....................................................................................193
12.5.7 Transmit halt timing by CTS*...............................................................................................194
13 TIMERS/COUNTERS................................................................................................................................196
13.1 Features...........................................................................................................................................196
13.2 Block Diagrams...............................................................................................................................196
13.3 Registers...........................................................................................................................................198
13.3.1 Timer control registers 2, 1, and 0 (TCR2, 1, 0)....................................................................200
13.3.2 Interval timer mode registers 0, 1, and 2 (ITMR2, 1, 0)........................................................202
13.3.3 Divider registers 2, 1, and 0 (CCDR2, 1, 0) ..........................................................................203
13.3.4 Pulse generator mode registers 2 and 1 (PGMR2, 1).............................................................204
13.3.5 Watchdog timer mode register 2 (WTMR2)..........................................................................205
13.3.6 Timer interrupt status registers 2, 1 and 0 (TISR2, 1, 0) .......................................................206
13.3.7 Compare registers A 2, 1 and 0 (CPRA2, 1, 0)......................................................................208
13.3.8 Compare registers B 2, 1 and 0 (CPRB2, 1, 0)......................................................................208
13.3.9 Timer read registers 2, 1 and 0 (TRR2, 1, 0).........................................................................209
13.4 Operations........................................................................................................................................210
13.4.1 Interval timer mode................................................................................................................210
13.4.2 Pulse generator mode.............................................................................................................213
13.4.3 Watchdog timer mode............................................................................................................215
13.5 Timing Explanations........................................................................................................................216
13.5.1 Interval timer mode interrupt timing......................................................................................216
13.5.2 Pulse generator mode F/F output timing................................................................................217
13.5.3 Watchdog timer mode interrupt timing..................................................................................217
14 IO PORTS (PIO).........................................................................................................................................218
14.1 Set-Up of the Shared PIO’s..............................................................................................................218
14.2 Functions..........................................................................................................................................218
14.3 Registers...........................................................................................................................................219
14.3.1 PIO data registers (PDR2, 1, 0).............................................................................................220
14.3.2 PIO direction registers (POR2, 1, 0).....................................................................................221

Users Manual
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1INTRODUCTION
1.1 Overview
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1.2 Notation used in this manual
Mathematical notation
Data notation
Signal notation
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1.3 Kind of accessing by the TX3904

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1.4 Precautions in the TMPR3904F specification
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Do not use

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2 FEATURES
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3 CONFIGURATION
DMAC0(2ch.)
DMAC1(2ch.)
DRAMC
ROMC
IRC
SIO0
SIO1
G to IM Bridge
G Bus
CG
EBIF
WBU DSU
TX39 processor core
R3900 I-Cache
D-Cache
PIO
G-Bus I/F
IM Bus
INT[7:0]
DREQ[1:0]
DACK[1:0]
DREQ[3:2]/PIO1[7:6]
DACK[3:2]/PIO1[5:4]
PIO0[7:0]
XIN
XOUT
A[31:24]/PIO2[7:0]
BE[3:0]*
D[31:0]
R/W*
BSTART*
HAVEIT*/PIO1[2]
ACK*
BUSERR*
BUSREL*/PIO1[3]
BUSREQ*/PIO1[1]
BUSGNT*/PIO1[0]
SYSCLK
TMR0
NMI*
TEST2*
HALF*
SCS[3:0]*
TEST*
CLKEN
PLLOFF*
Debug Interface
SIN0
SOUT0
CTS0*
SIN1
SOUT1
CTS1*
RAS1,0[3:0]*
CAS[3:0]*
WE*
OE[1:0]*
CE1,0[1:0]*
SWE*[1:0]
SCLKIN
TMR1
TMR2
TIMOUT1
TIMOUT2
TIMIN2
TIMIN1
DONE*
RESET*
BOOT16
A[23:1]
LAST*
RTS1*
RTS0*
Fig. 3-1 TX3904 Block Diagram

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4PINS
4.1 Positions of Pins

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