Toshiba TX49 TMPR4937 User manual

64-Bit TX System RISC
TX49 Family
TMPR4937
Rev. 2.0

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© 2005 TOSHIBA CORPORATION
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Preface
Thank you for new or continued patronage of TOSHIBA semiconductor products. This is the 2005
edition of the user’s manual for the TMPR4937 64-bit RISC microprocessor.
This databook is written so as to be accessible to engineers who may be designing a TOSHIBA
microprocessor into their products for the first time. No prior knowledge of this device is assumed. What
we offer here is basic information about the microprocessor, a discussion of the application fields in
which the microprocessor is utilized, and an overview of design methods. On the other hand, the more
experienced designer will find complete technical specifications for this product.
Toshiba continually updates its technical information. Your comments and suggestions concerning this
and other Toshiba documents are sincerely appreciated and may be utilized in subsequent editions. For
updating of the data in this manual, or for additional information about the product appearing in it, please
contact your nearest Toshiba office or authorized Toshiba dealer.
March 2005

Table of Contents
i
Table of Contents
Handling precautions
TMPR4937
1. Overview and Features ........................................................................................................................................... 1-1
1.1 Overview........................................................................................................................................................ 1-1
1.2 Features.......................................................................................................................................................... 1-1
1.2.1 Features of the TX49/H3 core.............................................................................................................. 1-2
1.2.2 Features of TX4937 peripheral functions ............................................................................................ 1-2
2. Configuration.......................................................................................................................................................... 2-1
2.1 TX4937 block diagram .................................................................................................................................. 2-1
3. Signals ............................................................................................................................................................. 3-1
3.1 Pin Signal Description ................................................................................................................................... 3-1
3.1.1 Signals Common to SDRAM and External Bus Interfaces.................................................................. 3-1
3.1.2 SDRAM Interface Signals ................................................................................................................... 3-2
3.1.3 External Interface Signals.................................................................................................................... 3-3
3.1.4 DMA Interface Signals ........................................................................................................................ 3-4
3.1.5 PCI Interface Signals........................................................................................................................... 3-4
3.1.6 Serial I/O Interface Signals.................................................................................................................. 3-6
3.1.7 Timer Interface Signals........................................................................................................................ 3-6
3.1.8 Parallel I/O Interface Signals............................................................................................................... 3-6
3.1.9 AC-link Interface Signals .................................................................................................................... 3-7
3.1.10 Interrupt Signals................................................................................................................................... 3-7
3.1.11 Extended EJTAG Interface Signals...................................................................................................... 3-8
3.1.12 Clock Signals....................................................................................................................................... 3-8
3.1.13 Initialization Signal.............................................................................................................................. 3-9
3.1.14 Test Signals.......................................................................................................................................... 3-9
3.1.15 Power Supply Pins............................................................................................................................... 3-9
3.2 Boot Configuration ...................................................................................................................................... 3-10
3.3 Pin multiplex................................................................................................................................................ 3-14
4. Address Mapping.................................................................................................................................................... 4-1
4.1 TX4937 Physical Address Map...................................................................................................................... 4-1
4.2 Register Map.................................................................................................................................................. 4-2
4.2.1 Addressing........................................................................................................................................... 4-2
4.2.2 Ways toAccess to Internal Registers................................................................................................... 4-2
4.2.3 Register Map........................................................................................................................................ 4-3
5. Configuration Registers.......................................................................................................................................... 5-1
5.1 Detailed Description ...................................................................................................................................... 5-1
5.1.1 Detecting G-Bus Timeout.................................................................................................................... 5-1
5.2 Registers......................................................................................................................................................... 5-2
5.2.1 Chip Configuration Register (CCFG) 0xE000..................................................................................... 5-3
5.2.2 Chip Revision ID Register (REVID) 0xE008......................................................................................5-6
5.2.3 Pin Configuration Register (PCFG) 0xE010 ....................................................................................... 5-7
5.2.4 Timeout Error Access Address Register (TOEA) 0xE018................................................................ 5-10
5.2.5 Clock Control Register (CLKCTR) 0xE020...................................................................................... 5-11
5.2.6 G-BusArbiter Control Register (GARBC) 0xE030...........................................................................5-13
5.2.7 Register Address Mapping Register (RAMP) 0xE048 ...................................................................... 5-14
6. Clocks ............................................................................................................................................................. 6-1
6.1 TX4937 Clock Signals................................................................................................................................... 6-1
6.2 Power-Down Mode........................................................................................................................................ 6-5
6.2.1 Halt Mode and Doze Mode.................................................................................................................. 6-5

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ii
6.2.2 Power Reduction for Peripheral Modules............................................................................................ 6-5
6.3 Power-On Sequence....................................................................................................................................... 6-6
7. External Bus Controller.......................................................................................................................................... 7-1
7.1 Features.......................................................................................................................................................... 7-1
7.2 Block Diagram............................................................................................................................................... 7-2
7.3 Detailed Explanation...................................................................................................................................... 7-3
7.3.1 External Bus Control Register............................................................................................................. 7-3
7.3.2 Global/Boot-up Options....................................................................................................................... 7-4
7.3.3 Address Mapping................................................................................................................................. 7-5
7.3.4 External Address Output...................................................................................................................... 7-6
7.3.5 Data Bus Size....................................................................................................................................... 7-7
7.3.6 Access Mode........................................................................................................................................ 7-9
7.3.7 Access Timing ................................................................................................................................... 7-13
7.3.8 Clock Options.................................................................................................................................... 7-19
7.4 Register........................................................................................................................................................ 7-20
7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1)
0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7)...... 7-21
7.5 Timing Diagrams ......................................................................................................................................... 7-24
7.5.1 ACE* Signal...................................................................................................................................... 7-25
7.5.2 Normal mode access (Single, 32-bit Bus).......................................................................................... 7-27
7.5.3 Normal mode access (Burst, 32-bit Bus)........................................................................................... 7-31
7.5.4 Normal Mode Access (Single, 16-bit bus).........................................................................................7-33
7.5.5 Normal Mode Access (Burst, 16-bit Bus)..........................................................................................7-37
7.5.6 Normal Mode Access (Single, 8-bit Bus) ..........................................................................................7-39
7.5.7 Normal Mode Access (Burst, 8-bit Bus)............................................................................................ 7-42
7.5.8 Page Mode Access (Burst, 32-bit Bus).............................................................................................. 7-44
7.5.9 External ACK Mode Access (32-bit Bus).......................................................................................... 7-46
7.5.10 READY Mode Access (32-bit Bus)................................................................................................... 7-52
7.6 Flash ROM, SRAM Usage Example ........................................................................................................... 7-54
8. DMA Controller...................................................................................................................................................... 8-1
8.1 Features.......................................................................................................................................................... 8-1
8.2 Block Diagram............................................................................................................................................... 8-2
8.3 Detailed Explanation...................................................................................................................................... 8-4
8.3.1 Transfer Mode...................................................................................................................................... 8-4
8.3.2 On-chip Registers ................................................................................................................................ 8-5
8.3.3 External I/O DMATransfer Mode....................................................................................................... 8-5
8.3.4 Internal I/O DMATransfer Mode........................................................................................................8-8
8.3.5 Memory-Memory Copy Mode............................................................................................................. 8-9
8.3.6 Memory Fill Transfer Mode ................................................................................................................ 8-9
8.3.7 Single Address Transfer....................................................................................................................... 8-9
8.3.8 Dual Address Transfer ....................................................................................................................... 8-12
8.3.9 DMATransfer.................................................................................................................................... 8-17
8.3.10 Chain DMA Transfer ......................................................................................................................... 8-18
8.3.11 Dynamic Chain Operation ................................................................................................................. 8-20
8.3.12 Interrupts............................................................................................................................................ 8-21
8.3.13 Transfer Stall Detection Function...................................................................................................... 8-21
8.3.14 Arbitration Among DMA Channels................................................................................................... 8-22
8.3.15 Restrictions in Access to PCI Bus...................................................................................................... 8-22
8.4 DMA Controller Registers........................................................................................................................... 8-23
8.4.1 DMA Master Control Register (DM0MCR, DM1MCR)...................................................................8-25
8.4.2 DMA Channel Control Register (DM0CCRn, DM1CCRn).............................................................. 8-27
8.4.3 DMA Channel Status Register (DM0CSRn, DM1CSRn)) ................................................................8-31
8.4.4 DMA Source Address Register (DM0SARn, DM1SARn) ................................................................ 8-33
8.4.5 DMA Destination Address Register (DM0DARn, DM1DARn)........................................................ 8-34
8.4.6 DMA Chain Address Register (DM0CHARn, DM1CHARn)........................................................... 8-35
8.4.7 DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)............................................. 8-36

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8.4.8 DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn)....................................8-37
8.4.9 DMA Count Register (DM0CNTRn, DM1CNTRn).......................................................................... 8-38
8.4.10 DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) ........................................................ 8-39
8.5 Timing Diagrams ......................................................................................................................................... 8-40
8.5.1 Single Address Single Transfer from Memory to I/O (32-bit ROM).................................................8-40
8.5.2 Single Address Single Transfer from Memory to I/O (16-bit ROM).................................................8-41
8.5.3 Single Address Single Transfer from I/O to Memory (32-bit SRAM)............................................... 8-42
8.5.4 Single Address Burst Transfer from Memory to I/O (32-bit ROM) ..................................................8-43
8.5.5 Single Address Burst Transfer from I/O to Memory (32-bit SRAM) ................................................ 8-44
8.5.6 Single Address Single Transfer from Memory to I/O (16-bit ROM).................................................8-46
8.5.7 Single Address Single Transfer from I/O to Memory (16-bit SRAM)............................................... 8-47
8.5.8 Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM).............................. 8-48
8.5.9 Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM)............................8-49
8.5.10 Single Address Single Transfer from Memory to I/O (64-bit SRAM)............................................... 8-50
8.5.11 SingleAddress Single Transfer from I/O to Memory (64-bit SDRAM)............................................8-51
8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle
when DMADONE* Signal is Set to Output ...................................................................................... 8-52
8.5.13 Single Address Single Transfer from Memory to I/O (32-bit SDRAM)............................................8-53
8.5.14 Single Address Single Transfer from I/O to Memory (32-bit SDRAM)............................................8-54
8.5.15 External I/O Device – SRAM Dual Address Transfer ....................................................................... 8-55
8.5.16 External I/O Device – SDRAM DualAddress Transfer .................................................................... 8-57
8.5.17 External I/O Device (Non-burst) – SDRAM Dual Address Transfer................................................. 8-59
9. SDRAM Controller................................................................................................................................................. 9-1
9.1 Characteristics................................................................................................................................................ 9-1
9.2 Block Diagram............................................................................................................................................... 9-2
9.3 Detailed Explanation...................................................................................................................................... 9-3
9.3.1 Supported SDRAM configurations...................................................................................................... 9-3
9.3.2 Address Mapping................................................................................................................................. 9-4
9.3.3 Initialization of SDRAM ..................................................................................................................... 9-9
9.3.4 Initialization of Memory Data, ECC/Parity.......................................................................................9-10
9.3.5 Low Power Consumption Function................................................................................................... 9-11
9.3.6 Bus Errors.......................................................................................................................................... 9-12
9.3.7 Memory Read and Memory Write..................................................................................................... 9-12
9.3.8 Slow Write Burst................................................................................................................................ 9-12
9.3.9 Clock Feedback ................................................................................................................................. 9-12
9.3.10 ECC ................................................................................................................................................... 9-13
9.4 Registers....................................................................................................................................................... 9-17
9.4.1 SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0) 0x8008 (ch. 1) 0x8010 (ch. 2)
0x8018 (ch. 3).................................................................................................................................... 9-18
9.4.2 SDRAM Timing Register (SDCTR) 0x8040..................................................................................... 9-20
9.4.3 SDRAM Command Register (SDCCMD) 0x8058............................................................................ 9-22
9.4.4 ECC Control Register (ECCCR) 0xA000.......................................................................................... 9-23
9.4.5 ECC Status Register (ECCSR) 0xA008............................................................................................. 9-25
9.5 Timing Diagrams ......................................................................................................................................... 9-26
9.5.1 Single Read (64-bit Bus).................................................................................................................... 9-26
9.5.2 Single Write (64-bit Bus)................................................................................................................... 9-28
9.5.3 Burst Read (64-bit Bus)..................................................................................................................... 9-30
9.5.4 Burst Write (64-bit Bus) .................................................................................................................... 9-31
9.5.5 Burst Write (64-bit Bus, Slow Write Burst)....................................................................................... 9-32
9.5.6 Single Read (32-bit Bus).................................................................................................................... 9-33
9.5.7 Single Write (32-bit Bus)................................................................................................................... 9-35
9.5.8 Low Power Consumption and Power Down Mode ...........................................................................9-37
9.6 SDRAM Usage Example............................................................................................................................. 9-42
10. PCI Controller....................................................................................................................................................... 10-1
10.1 Features........................................................................................................................................................ 10-1
10.1.1 Overall............................................................................................................................................... 10-1

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iv
10.1.2 Initiator Function............................................................................................................................... 10-1
10.1.3 Target Function.................................................................................................................................. 10-2
10.1.4 PCI Arbiter......................................................................................................................................... 10-2
10.1.5 PDMAC (PCI DMA Controller)........................................................................................................ 10-2
10.2 Block Diagram............................................................................................................................................. 10-3
10.3 Detailed Explanation.................................................................................................................................... 10-4
10.3.1 Terminology Explanation .................................................................................................................. 10-4
10.3.2 On-chip Register................................................................................................................................ 10-4
10.3.3 Supported PCI Bus Commands ......................................................................................................... 10-6
10.3.4 Initiator Access (G-Bus →PCI Bus Address Conversion)................................................................ 10-8
10.3.5 Target Access (PCI Bus →G-Bus Address Conversion)................................................................. 10-10
10.3.6 Post Write Function ......................................................................................................................... 10-12
10.3.7 Endian Switching Function.............................................................................................................. 10-12
10.3.8 66 MHz Operation Mode................................................................................................................. 10-13
10.3.9 Power Management......................................................................................................................... 10-14
10.3.10 PDMAC (PCI DMA Controller)...................................................................................................... 10-15
10.3.11 Error Detection, Interrupt Reporting................................................................................................ 10-18
10.3.12 PCI Bus Arbiter................................................................................................................................ 10-20
10.3.13 PCI Boot .......................................................................................................................................... 10-22
10.3.14 Set Configuration Space .................................................................................................................. 10-23
10.3.15 PCI Clock ........................................................................................................................................ 10-23
10.4 PCI Controller Control Register................................................................................................................. 10-24
10.4.1 ID Register (PCIID) 0xD000........................................................................................................... 10-26
10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004.................................................................. 10-27
10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008............................................................... 10-30
10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C......................................................................... 10-31
10.4.5 P2G Memory Space 0 PCI Lower Base Address Register (P2GM0PLBASE) 0xD010................ 10-32
10.4.6 P2G Memory Space 0 PCI Upper BaseAddress Register (P2GM0PUBASE) 0xD014................ 10-33
10.4.7 P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0xD018................ 10-33
10.4.8 P2G Memory Space 1 PCI Upper BaseAddress Register (P2GM1PUBASE) 0xD01C ................ 10-34
10.4.9 P2G Memory Space 2 PCI BaseAddress Register (P2GM2PBASE) 0xD020......................... 10-34
10.4.10 P2G I/O Space PCI BaseAddress Register (P2GIOPBASE) 0xD024 ...................................... 10-35
10.4.11 Subsystem ID Register (PCISID) 0xD02C...................................................................................... 10-36
10.4.12 Capabilities Pointer Register (PCICAPPTR) 0xD034..................................................................... 10-37
10.4.13 PCI Configuration 2 Register (PCICFG2) 0xD03C......................................................................... 10-38
10.4.14 G2P Timeout Count Register (G2PTOCNT) 0xD040 .................................................................... 10-39
10.4.15 G2P Status Register (G2PSTATUS) 0xD080................................................................................... 10-40
10.4.16 G2P Interrupt Mask Register (G2PMASK) 0xD084 ....................................................................... 10-41
10.4.17 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088.................................................... 10-42
10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C.............................................................. 10-43
10.4.19 P2G Configuration Register (P2GCFG) 0xD090 ............................................................................ 10-44
10.4.20 P2G Status Register (P2GSTATUS) 0xD094 .................................................................................. 10-46
10.4.21 P2G Interrupt Mask Register (P2GMASK) 0xD098....................................................................... 10-47
10.4.22 P2G Current Command Register (P2GCCMD) 0xD09C ................................................................ 10-48
10.4.23 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100........................................... 10-49
10.4.24 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104 ................................................... 10-51
10.4.25 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108 ............................................................... 10-52
10.4.26 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0xD10C ............................................. 10-53
10.4.27 PCI Bus Arbiter Broken Master Register (PBABM) 0xD110 ................................................... 10-54
10.4.28 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114............................................. 10-55
10.4.29 PCI Bus Arbiter Current Grant Register (PBACGNT) 0xD118 ................................................ 10-56
10.4.30 PCI Bus Arbiter Current State Register (PBACSTATE) 0xD11C ............................................. 10-57
10.4.31 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0xD120..................... 10-59
10.4.32 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0xD128..................... 10-60
10.4.33 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0xD130..................... 10-61
10.4.34 G2P I/O Space G-Bus BaseAddress Register (G2PIOGBASE) 0xD138.................................. 10-62
10.4.35 G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0xD140................................. 10-63
10.4.36 G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0xD144................................. 10-64

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10.4.37 G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0xD148................................. 10-65
10.4.38 G2P I/O SpaceAddress Mask Register (G2PIOMASK) 0xD14C............................................. 10-66
10.4.39 G2P Memory Space 0 PCI BaseAddress Register (G2PM0PBASE) 0xD150.......................... 10-67
10.4.40 G2P Memory Space 1 PCI BaseAddress Register (G2PM1PBASE) 0xD158.......................... 10-68
10.4.41 G2P Memory Space 2 PCI BaseAddress Register (G2PM2PBASE) 0xD160.......................... 10-69
10.4.42 G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0xD168....................................... 10-70
10.4.43 PCI Controller Configuration Register (PCICCFG) 0xD170.................................................... 10-71
10.4.44 PCI Controller Status Register (PCICSTATUS) 0xD174 ................................................................ 10-74
10.4.45 PCI Controller Interrupt Mask Register (PCICMASK) 0xD178............................................... 10-76
10.4.46 P2G Memory Space 0 G-Bus BaseAddress Register (P2GM0GBASE) 0xD180..................... 10-77
10.4.47 P2G Memory Space 1 G-Bus BaseAddress Register (P2GM1GBASE) 0xD188..................... 10-78
10.4.48 P2G Memory Space 2 G-Bus BaseAddress Register (P2GM2GBASE) 0xD190..................... 10-79
10.4.49 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0xD198.................................. 10-80
10.4.50 G2P Configuration Address Register(G2PCFGADRS) 0xD1A0 .............................................. 10-81
10.4.51 G2P Configuration Data Register (G2PCFGDATA) 0xD1A4................................................... 10-82
10.4.52 G2P Interrupt Acknowledge Data Register (G2PINTACK) 0xD1C8........................................ 10-83
10.4.53 G2P Special Cycle Data Register (G2PSPC) 0xD1CC.................................................................... 10-84
10.4.54 Configuration Data 0 Register (PCICDATA0) 0xD1D0.................................................................. 10-85
10.4.55 Configuration Data 1 Register (PCICDATA1) 0xD1D4.................................................................. 10-86
10.4.56 Configuration Data 2 Register (PCICDATA2) 0xD1D8.................................................................. 10-87
10.4.57 Configuration Data 3 Register (PCICDATA3) 0xD1DC................................................................. 10-88
10.4.58 PDMAC Chain Address Register (PDMCA) 0xD200.................................................................... 10-89
10.4.59 PDMAC G-BusAddress Register (PDMGA) 0xD208.................................................................... 10-90
10.4.60 PDMAC PCI Bus Address Register (PDMPA) 0xD210.................................................................. 10-91
10.4.61 PDMAC Count Register (PDMCTR) 0xD218 ................................................................................ 10-92
10.4.62 PDMAC Configuration Register (PDMCFG) 0xD220.................................................................... 10-93
10.4.63 PDMAC Status Register (PDMSTATUS) 0xD228........................................................................ 10-95
10.5 PCI Configuration Space Register............................................................................................................. 10-98
10.5.1 Capability ID Register (Cap_ID) 0xDC .......................................................................................... 10-99
10.5.2 Next Item Pointer Register (Next_Item_Ptr) 0xDD...................................................................... 10-100
10.5.3 Power Management Capability Register (PMC) 0xDE ................................................................. 10-101
10.5.4 Power Management Control/Status Register (PMCSR) 0xE0................................................. 10-102
11. Serial I/O Port....................................................................................................................................................... 11-1
11.1 Features........................................................................................................................................................ 11-1
11.2 Block Diagram............................................................................................................................................. 11-2
11.3 Detailed Explanation.................................................................................................................................... 11-3
11.3.1 Overview ........................................................................................................................................... 11-3
11.3.2 Data Format....................................................................................................................................... 11-3
11.3.3 Serial Clock Generator....................................................................................................................... 11-5
11.3.4 Data Reception................................................................................................................................... 11-7
11.3.5 Data Transmission ............................................................................................................................. 11-7
11.3.6 DMA Transfer.................................................................................................................................... 11-7
11.3.7 Flow Control...................................................................................................................................... 11-8
11.3.8 Reception Data Status........................................................................................................................ 11-8
11.3.9 Reception Time Out........................................................................................................................... 11-9
11.3.10 Software Reset................................................................................................................................... 11-9
11.3.11 Error Detection/Interrupt Signaling..................................................................................................11-10
11.3.12 Multi-Controller System...................................................................................................................11-11
11.4 Registers......................................................................................................................................................11-12
11.4.1 Line Control Register 0 (SILCR0) 0xF300 (Ch. 0)
Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) ..........................................................................11-13
11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0)
DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch. 1)........................................................11-15
11.4.3 DMA/Interrupt Status Register 0 (SIDISR0) 0xF308 (Ch. 0)
DMA/Interrupt Status Register 1 (SIDISR1) 0xF408 (Ch. 1) ..........................................................11-17
11.4.4 Status Change Interrupt Status Register 0 (SISCISR0) 0xF30C (Ch. 0)
Status Change Interrupt Status Register 1 (SISCISR1) 0xF40C (Ch. 1) .......................................11-19

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11.4.5 FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0)
FIFO Control Register 1 (SIFCR1) 0xF410 (Ch. 1) .........................................................................11-20
11.4.6 Flow Control Register 0 (SIFLCR0) 0xF314 (Ch. 0)
Flow Control Register 1 (SIFLCR1) 0xF414 (Ch. 1).......................................................................11-21
11.4.7 Baud Rate Control Register 0 (SIBGR0) 0xF318 (Ch. 0)
Baud Rate Control Register 1 (SIBGR1) 0xF418 (Ch. 1) ................................................................11-22
11.4.8 Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0)
Transmit FIFO Register 1 (SITFIFO1) 0xF41C (Ch. 1)...................................................................11-23
11.4.9 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0)
Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1).....................................................................11-24
12. Timer/Counter....................................................................................................................................................... 12-1
12.1 Features........................................................................................................................................................ 12-1
12.2 Block Diagram............................................................................................................................................. 12-2
12.3 Detailed Explanation.................................................................................................................................... 12-3
12.3.1 Overview ........................................................................................................................................... 12-3
12.3.2 Counter Clock.................................................................................................................................... 12-3
12.3.3 Counter .............................................................................................................................................. 12-4
12.3.4 Interval Timer Mode.......................................................................................................................... 12-4
12.3.5 Pulse Generator Mode ....................................................................................................................... 12-6
12.3.6 Watchdog Timer Mode ...................................................................................................................... 12-7
12.4 Registers....................................................................................................................................................... 12-9
12.4.1 Timer Control Register n(TMTCRn) TMTCR0 0xF000 TMTCR1 0xF100 TMTCR2 0xF200... 12-10
12.4.2 Timer Interrupt Status Register n(TMTISRn) TMTISR0 0xF004 TMTISR1 0xF104
TMTISR2 0xF204 ............................................................................................................................12-11
12.4.3 Compare Register An (TMCPRAn) TMCPRA0 0xF008 TMCPRA1 0xF108
TMCPRA2 0xF208.......................................................................................................................... 12-12
12.4.4 Compare Register Bn (TMCPRBn) TMCPRB0 0xF00C TMCPRB1 0xF10C .............................. 12-13
12.4.5 Interval Timer Mode Register n(TMITMRn) TMITMR0 0xF010 TMITMR1 0xF110
TMITMR2 0xF210.......................................................................................................................... 12-14
12.4.6 Divide Register n(TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220 .. 12-15
12.4.7 Pulse Generator Mode Register n(TMPGMRn) TMPGMR0 0xF000 TMPGMR1 0xF130........ 12-16
12.4.8 Watchdog Timer Mode Register n(TMWTMRn) TMWTMR2 0xF240....................................... 12-17
12.4.9 Timer Read Register n(TMTRRn) 0xF0F0 TMTRR0 0xF0F0 TMTRR1 0xF1F0
TMTRR2 0xF2F0............................................................................................................................ 12-18
13. Parallel I/O Port.................................................................................................................................................... 13-1
13.1 Characteristics.............................................................................................................................................. 13-1
13.2 Block Diagram............................................................................................................................................. 13-1
13.3 Detailed Description .................................................................................................................................... 13-2
13.3.1 Selecting PIO Pins............................................................................................................................. 13-2
13.3.2 General-purpose Parallel Port............................................................................................................ 13-2
13.4 Registers....................................................................................................................................................... 13-2
13.4.1 PIO Output Data Register (PIODO) 0xF500..................................................................................... 13-3
13.4.2 PIO Input Data Register (PIODI) 0xF504 ......................................................................................... 13-3
13.4.3 PIO Direction Control Register (PIODIR) 0xF508 ........................................................................... 13-4
13.4.4 PIO Open Drain Control Register (XPIOOD) 0xF50C ..................................................................... 13-4
14. AC-link Controller................................................................................................................................................ 14-1
14.1 Features........................................................................................................................................................ 14-1
14.2 Configuration............................................................................................................................................... 14-2
14.3 Functional Description................................................................................................................................. 14-3
14.3.1 CODEC Connection .......................................................................................................................... 14-3
14.3.2 Boot Configuration............................................................................................................................ 14-4
14.3.3 Usage Flow........................................................................................................................................ 14-5
14.3.4 AC-link Start Up................................................................................................................................ 14-7
14.3.5 CODEC Register Access ................................................................................................................... 14-8
14.3.6 Sample-data Transmission and Reception ......................................................................................... 14-9

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vii
14.3.7 GPIO Operation............................................................................................................................... 14-14
14.3.8 Interrupt........................................................................................................................................... 14-15
14.3.9 AC-link Low-power Mode .............................................................................................................. 14-15
14.4 Registers..................................................................................................................................................... 14-16
14.4.1 ACLC Control Enable Register 0xF700......................................................................................... 14-17
14.4.2 ACLC Control Disable Register 0xF704........................................................................................ 14-20
14.4.3 ACLC CODEC Register Access Register 0xF708 .......................................................................... 14-22
14.4.4 ACLC Interrupt Status Register 0xF710......................................................................................... 14-23
14.4.5 ACLC Interrupt Masked Status Register 0xF714............................................................................ 14-25
14.4.6 ACLC Interrupt Enable Register 0xF718 ........................................................................................ 14-25
14.4.7 ACLC Interrupt Disable Register 0xF71C....................................................................................... 14-25
14.4.8 ACLC Semaphore Register 0xF720 .............................................................................................. 14-26
14.4.9 ACLC GPI Data Register 0xF740 ................................................................................................. 14-27
14.4.10 ACLC GPO Data Register 0xF744................................................................................................ 14-28
14.4.11 ACLC Slot Enable Register 0xF748.............................................................................................. 14-29
14.4.12 ACLC Slot Disable Register 0xF74C............................................................................................ 14-31
14.4.13 ACLC FIFO Status Register 0xF750............................................................................................. 14-32
14.4.14 ACLC DMARequest Status Register 0xF780................................................................................ 14-34
14.4.15 ACLC DMAChannel Selection Register 0xF784........................................................................... 14-35
14.4.16 ACLC Audio PCM Output Data Register 0xF7A0.......................................................................... 14-36
14.4.17 ACLC Center Data Register 0xF7A8 ............................................................................................ 14-37
14.4.18 ACLC Audio PCM Input Data Register 0xF7B0............................................................................ 14-38
14.4.19 ACLC Modem Input Data Register 0xF7BC.................................................................................. 14-39
14.4.20 ACLC Revision ID Register 0xF7FC............................................................................................ 14-40
15. Interrupt Controller............................................................................................................................................... 15-1
15.1 Characteristics.............................................................................................................................................. 15-1
15.2 Block Diagram............................................................................................................................................. 15-2
15.3 Detailed Explanation.................................................................................................................................... 15-4
15.3.1 Interrupt sources ................................................................................................................................ 15-4
15.3.2 Interrupt request detection ................................................................................................................. 15-5
15.3.3 Interrupt level assigning..................................................................................................................... 15-5
15.3.4 Interrupt priority assigning ................................................................................................................ 15-6
15.3.5 Interrupt notification.......................................................................................................................... 15-7
15.3.6 Clearing interrupt requests................................................................................................................. 15-7
15.3.7 Interrupt requests............................................................................................................................... 15-8
15.4 Registers..................................................................................................................................................... 15-10
15.4.1 Interrupt Detection Enable Register (IRDEN) 0xF600.....................................................................15-11
15.4.2 Interrupt Detection Mode Register 0 (IRDM0) 0xF604.................................................................. 15-12
15.4.3 Interrupt Detection Mode Register 1 (IRDM1) 0xF608.................................................................. 15-14
15.4.4 Interrupt Level Register 0 (IRLVL0) 0xF610.................................................................................. 15-17
15.4.5 Interrupt Level Register (IRLVL1) 0xF614..................................................................................... 15-19
15.4.6 Interrupt Level Register 2 (IRLVL2) 0xF618.................................................................................. 15-21
15.4.7 Interrupt Level Register 3 (IRLVL3) 0xF61C ................................................................................. 15-22
15.4.8 Interrupt Level Register 4 (IRLVL4) 0xF620.................................................................................. 15-24
15.4.9 Interrupt Level Register 5 (IRLVL5) 0xF624................................................................................ 15-26
15.4.10 Interrupt Level Register 6 (IRLVL6) 0xF628.................................................................................. 15-28
15.4.11 Interrupt Level Register 7 (IRLVL7) 0xF62C ................................................................................. 15-30
15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640............................................................................ 15-32
15.4.13 Interrupt Edge Detection Clear Register (IREDC) 0xF660............................................................. 15-33
15.4.14 Interrupt Pending Register (IRPND) 0xF680 .................................................................................. 15-34
15.4.15 Interrupt Current Status Register (IRCS) 0xF6A0........................................................................... 15-37
15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510................................................................... 15-39
15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514................................................................... 15-40
15.4.18 Interrupt Request Polarity Control Register (IRPOL) 0xF518 ........................................................ 15-41
15.4.19 Interrupt Request Control Register (IRRCNT) 0xF51C.................................................................. 15-42
15.4.20 Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xF520 .................................. 15-43
15.4.21 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524................................ 15-44

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viii
16. Removed ........................................................................................................................................................... 16-1
17. Removed ........................................................................................................................................................... 17-1
18. Removed ........................................................................................................................................................... 18-1
19. Removed ........................................................................................................................................................... 19-1
20. Extended EJTAG Interface................................................................................................................................... 20-1
20.1 Extended EJTAG Interface .......................................................................................................................... 20-1
20.2 JTAG Boundary Scan Test .......................................................................................................................... 20-2
20.2.1 JTAG Controller and Register ........................................................................................................... 20-2
20.2.2 Instruction Register............................................................................................................................ 20-3
20.2.3 Boundary Scan Register..................................................................................................................... 20-3
20.2.4 Device ID Register ............................................................................................................................ 20-6
20.3 Initializing the Extended EJTAG Interface.................................................................................................. 20-7
21. Electrical Characteristics ...................................................................................................................................... 21-1
21.1 Absolute maximum rating (*1).................................................................................................................... 21-1
21.2 Recommended operating conditions............................................................................................................ 21-1
21.3 DC characteristics........................................................................................................................................ 21-2
21.3.1 DC characteristics of pins other than PCI Interface pins................................................................... 21-2
21.3.2 DC characteristics of PCI Interface pins............................................................................................ 21-3
21.4 PLL power.................................................................................................................................................... 21-4
21.4.1 PLL power connection example ........................................................................................................ 21-4
21.5 AC characteristics........................................................................................................................................ 21-5
21.5.1 MASTERCLKAC characteristics..................................................................................................... 21-5
21.5.2 Power on AC characteristics.............................................................................................................. 21-5
21.5.3 SDRAM Interface AC characteristics................................................................................................ 21-6
21.5.4 External Bus InterfaceAC characteristics ......................................................................................... 21-8
21.5.5 PCI Interface AC characteristics (66 MHz).......................................................................................21-9
21.5.6 PCI Interface AC characteristics (33 MHz).......................................................................................21-9
21.5.7 PCI EEPROM Interface AC characteristics......................................................................................21-11
21.5.8 DMA Interface AC characteristics....................................................................................................21-11
21.5.9 Interrupt Interface AC characteristics .............................................................................................. 21-12
21.5.10 SIO Interface AC characteristics...................................................................................................... 21-13
21.5.11 Timer Interface AC characteristics .................................................................................................. 21-13
21.5.12 PIO Interface AC characteristics...................................................................................................... 21-14
21.5.13 AC-link Interface AC characteristics............................................................................................... 21-14
22. Pinout and Package Information........................................................................................................................... 22-1
22.1 Pinout Diagram............................................................................................................................................ 22-1
22.2 Package Dimensions.................................................................................................................................... 22-9
23. Notes on Use of TMPR4937................................................................................................................................. 23-1
23.1 Notes on TX49/H3 Core .............................................................................................................................. 23-1
23.2 Notes on External Bus Controller................................................................................................................ 23-3
23.3 Notes on DMA Controller............................................................................................................................ 23-3
23.4 Note on PCI Controller................................................................................................................................ 23-6
23.5 Notes on Serial I/O Port............................................................................................................................. 23-10
24. Parts Number when Ordering............................................................................................................................... 24-1
Appendix A TX49/H3 Core Supplement ................................................................................................................ A-1
A.1 Processor ID.................................................................................................................................................. A-1
A.2 Interrupts....................................................................................................................................................... A-1
A.3 Bus Snoop..................................................................................................................................................... A-1
A.4 Halt/Doze mode............................................................................................................................................ A-1
A.5 Memory access order.................................................................................................................................... A-1

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ix
TMPR4937 Revision History............................................................................................................................................1

Table of Contents
x

Handling Precautions

1 Using Toshiba Semiconductors Safely
1-1
1. Using Toshiba Semiconductors Safely
TOSHIBA are continually working to improve the quality and the reliability of their products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity
and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to
observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product
could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set
forth in the TOSHIBA Semiconductor Reliability Handbook.
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that
requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion
control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer’s own risk.

1 Using Toshiba Semiconductors Safely
1-2

2 Safety Precautions
2-1
2. Safety Precautions
This section lists important precautions which users of semiconductor devices (and anyone else) should observe
in order to avoid injury and damage to property, and to ensure safe and correct use of devices.
Please be sure that you understand the meanings of the labels and the graphic symbol described below before
you move on to the detailed descriptions of the precautions.
[Explanation of labels]
Indicates an imminently hazardous situation which will result in death or serious
injury if you do not follow instructions.
Indicates a potentially hazardous situation which could result in death or serious injury
if you do not follow instructions.
Indicates a potentially hazardous situation which if not avoided, may result in minor
injury or moderate injury.
[Explanation of graphic symbol]
Graphic symbol Meaning
Indicates that caution is required (laser beam is dangerous to eyes).

2 Safety Precautions
2-2
2.1 General Precautions regarding Semiconductor Devices
Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or
temperature).
This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury.
Do not insert devices in the wrong orientation.
Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum
current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it
to catch fire or explode and resulting in injury.
When power to a device is on, do not touch the device’s heat sink.
Heat sinks become hot, so you may burn your hand.
Do not touch the tips of device leads.
Because some types of device have leads with pointed tips, you may prick your finger.
When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to
the pins of the device under test before powering it on.
Otherwise, you may receive an electric shock causing injury.
Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it.
Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock.
Always wear protective glasses when cutting the leads of a device with clippers or a similar tool.
If you do not, small bits of metal flying off the cut ends may damage your eyes.