Toshiba Preliminary TB6560AHQ User manual

TB6560AHQ/AFG
2007-05-24
1V1.0.3
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TB6560AHQ,TB6560AFG
PWM Chopper-Type bipolar
Stepping Motor Driver IC
The TB6560AHQ/AFG is a PWM chopper-type sinusoidal
micro-step bipolar stepping motor driver IC.
It supports both 2-phase/1-2-phase/2W1-2-phase/4W1-2-phase
excitation mode and forward/reverse mode and is capable of
low-vibration, high-performance drive of 2-phase bipolar type
stepping motors using only a clock signal.
Features
•Single-chip bipolar sinusoidal micro-step stepping motor
driver
•Uses high withstand voltage BiCD process:
Ron (upper lower) =0.6 Ω(typ.)
•Forward and reverse rotation control available
•Selectable phase drive (2, 1-2, 2W1-2, and 4W1-2)
•High output withstand voltage: VDSS =40 V
•High output current: IOUT =HQ: 3.5 A (peak)
FG: 2.5 A (peak)
•Packages: HZIP25-P-1.27/HQFP64-P-1010-0.50
•Built-in input pull-down resistor: 100 kΩ(typ.)
•Output monitor pin equipped: MO current (IMO (max) =1 mA)
•Equipped with reset and enable pins
•Built-in overheat protection circuit
*: Since this product has a MOS structure, it is sensitive to electrostatic discharge. These ICs are highly sensitive to
electrostatic discharge. When handling them, please be careful of electrostatic discharge, temperature and
humidity conditions.
TB6560AHQ
TB6560AFG
Weight:
HZIP25-P-1.27: 9.86 g (typ.)
HQFP64-P-1010-0.50: 0.26 g (typ.)
Preliminar
y
The TB6560AHQ/AFG is a Pb-free product.
The following conditions apply to solderability:
*Solderability
1. Use of Sn-37Pb solder bath
*solder bath temperature =230°C
*dipping time =5 seconds
*number of times =once
*use of R-type flux
2. Use of Sn-3.0Ag-0.5Cu solder bath
*solder bath temperature =245°C
*dipping time =5 seconds
*the number of times =once
*use of R-type flux

TB6560AHQ/AFG
2007-05-24
2V1.0.3
Block Diagram
M1
M2
CW/CCW
CLK
RESET
ENABLE
DCY1
DCY2
OSC
Input
circuit
OSC
VDD
Maximum current
setting circuit
Current selector
circuit B
Overheat protection
circuit
Protect MO
+
+
Bridge
driver A
Decode
r
VMA
OUT_AP
OUT_AM
NFA
VMB
Bridge
driver B B
Decode
r
OUT_BP
OUT_BM
NFB
TQ1 TQ2
SGND PGNDA PGNDB
Current selector
circuit A
10/641/422/43
11/2, 4
9/61, 62
12/6, 7
8/55, 56
14/13, 14
13/10, 11
16/19, 20
18/25, 2617/2319/2820/30, 31
23/36
22/35
21/33
3/45
5/48
4/47
25/39
24/38
7/53
15/166/50, 51
TB6560AHQ/TB6560AFG

TB6560AHQ/AFG
2007-05-24
3V1.0.3
Pin Functions
Pin No.
AHQ AFG
I/O Symbol Functional Description
1 42 Input TQ2 Torque setting input (current setting) (built-in pull-down resistor)
2 43 Input TQ1 Torque setting input (current setting) (built-in pull-down resistor)
3 45 Input CLK Step transition, clock input (built-in pull-down resistor)
4 47 Input ENABLE H: Enable; L: All output OFF (built-in pull-down resistor)
5 48 Input RESET L: Reset (output is reset to its initial state) (built-in pull-down resistor)
6 50/51 ⎯SGND Signal ground (control side) (Note 1)
7 53 ⎯OSC Connects to and oscillates CR. Output chopping.
8 55/56 Input VMB Motor side power pin (B phase side) (Note 1)
9 61/62 Output OUT_BM OUT_B output (Note 1)
10 64(*) ⎯PGNDB Power ground
11 2/4(*) ⎯N
FB B channel output current detection pin (resistor connection).
Short the two pins for FG. (Note 1)
12 6/7 Output OUT_BP OUT_B output (Note 1)
13 10/11 Output OUT_AM OUT_A output (Note 1)
14 13/14(*) ⎯N
FA A channel output current detection pin (resistor connection).
Short the two pins for FG. (Note 1)
15 16 ⎯PGNDA Power ground
16 19/20 Output OUT_AP OUT_A output (Note 1)
17 23 Output MOInitial state detection output. ON when in initial state (open drain).
18 25/26 Input VMA Motor side power pin (A phase side) (Note 1)
19 28 Output Protect When TSD, ON (open drain). Normal Z.
20 30/31 Input VDD Control side power pin. (Note 1)
21 33 Input CW/CCW
Forward/Reverse toggle pin. L: Forward; H: Reverse
(built-in pull-down resistor)
22 35 Input M2 Excitation mode setting input (built-in pull-down resistor)
23 36 Input M1 Excitation mode setting input (built-in pull-down resistor)
24 38 Input DCY2 Current Decay mode setting input (built-in pull-down resistor)
25 39 Input DCY1 Current Decay mode setting input (built-in pull-down resistor)
(*) : Pin assignment of TB6560AFG is different from that of TB6560FG.
AHQ : No Non-connection (NC)
AFG : Other than the above pins, all are NC
(Since NC pins are not connected to the internal circuit, a potential can be applied to those pins.)
All control input pins: Pull-down resistor 100 kΩ(typ.)
Note 1: If the FG pin number column indicates more than one pin, the indicated pins should be tied to each other at
a position as close to the pins as possible.
(The electrical characteristics of the relevant pins in this document refer to those when they are handled in
that way.)
<Terminal circuits>
Input pins
(M1, M2, CLK, CW/CCW,
ENABLE and RESET)
Output ins
(MO, PROTECT)
VDD
100 kΩ
100 Ω
100 Ω

TB6560AHQ/AFG
2007-05-24
4V1.0.3
Absolute Maximum Ratings (Ta =25°C)
Characteristic Symbol Rating Unit
VDD 6
Power supply voltage
VMA/B 40
V
HQ 3.5
Output current Peak
FG
IO (PEAK)
2.5
A/phase
MO drain current I (MO) 1 mA
Input voltage VIN 5.5 V
5 (Note 1)
HQ
43 (Note 2)
1.7 (Note 3)
Power dissipation
FG
PD
4.2 (Note 4)
W
Operating temperature Topr −30 to 85 °C
Storage temperature Tstg −55 to 150 °C
Note 1: Ta =25°C, No heat sink.
Note 2: Ta =25°C, with infinite heat sink (HZIP25).
Note 3: Ta =25°C, with soldered leads.
Note 4: Ta =25°C, when mounted on the board (4-layer board).
Susceptible to the board layout and the mounting conditions.
Operating Range (Ta =−30 to 85°C)
Characteristic Symbol Test Condition Min Typ. Max Unit
VDD ⎯4.5 5.0 5.5 V
Power supply voltage
VMA/B VMA/B
>
=
VDD 4.5 ⎯(34) V
HQ ⎯⎯⎯3
Output current
FG
IOUT
⎯⎯1.5
A
Input voltage VIN ⎯0 ⎯5.5 V
Clock frequency fCLK ⎯⎯⎯15 kHz
OSC frequency fOSC ⎯⎯⎯600 kHz

TB6560AHQ/AFG
2007-05-24
5V1.0.3
Electrical Characteristics (Ta =25°C, VDD =5 V, VM=24 V)
Characteristic Symbol
Test
Circuit Test Condition Min Typ. Max Unit
High VIN (H) 2.0 ⎯V
DD
Input voltage
Low VIN (L)
1
−0.2 ⎯0.8
V
Input hysteresis voltage VH1
M1, M2, CW/CCW, CLK, RESET ,
ENABLE, DECAY, TQ1, TQ2, ISD
⎯400 ⎯mV
IIN (H)
M1, M2, CW/CCW, CLK, RESET ,
ENABLE, DECAY, TQ1, TQ2, ISD
VIN =5.0 V
Built-in pull-down resistor
30 55 80
Input current
IIN (L)
1
VIN =0 V ⎯⎯1
μA
IDD1
Output open,
RESET : H, ENABLE: H
(2, 1-2 phase excitation)
⎯3 5
IDD2
Output open,
RESET : H, ENABLE: H
(W1−2, 2W1-2 phase excitation)
⎯3 5
IDD3 RESET : L, ENABLE: L ⎯2 5
Consumption current VDD pin
IDD4
1
RESET : H, ENABLE: L ⎯2 5
mA
IM1 RESET : H/L, ENABLE: L ⎯ 0.5 1
Consumption current VMpin
IM2
1
RESET : H/L, ENABLE: H ⎯ 0.7 2
mA
Output channel margin of error ΔVO⎯B/A, COSC =0.0033 μF −5 ⎯5 %
VNFHH TQ1 =H, TQ2 =H 10 20 30
VNFHL TQ1 =L, TQ2 =H 47 50 55
VNFLH TQ1 =H, TQ2 =L 70 75 80
VNF level
Level differential
VNFLL
⎯
TQ1 =L, TQ2 =L 100
%
Minimum clock pulse width tW (CLK) ⎯C =330 pF ⎯7.7 ⎯μs
MO output residual voltage VOL MO ⎯I
OL =1 mA ⎯⎯0.5 V
TSD TSD ⎯(Design target value) ⎯170 ⎯°C
TSD hysteresis TSDhys ⎯(Design target value) ⎯20 ⎯°C
Oscillating frequency fOSC ⎯C =330 pF 60 130 200 kHz

TB6560AHQ/AFG
2007-05-24
6V1.0.3
Electrical Characteristics (Ta =25°C, VDD =5 V, VM=24 V)
Output Block
Characteristic Symbol
Test
Circuit Test Condition Min Typ. Max Unit
Ron U1H ⎯0.3 0.4
AHQ
Ron L1H
IOUT =1.5 A
⎯0.3 0.4
Ron U1F ⎯0.35 0.5
Output ON resistor
AFG
Ron L1F
4
IOUT =1.5 A
⎯0.35 0.5
Ω
2W1-2-
phase
excitation
1-2-
phase
excitation
θ=0 ⎯100 ⎯
⎯⎯θ=1/16 ⎯100 ⎯
2W1-2-
phase
excitation
⎯θ=2/16 93 98 100
⎯⎯θ=3/16 91 96 100
2W1-2-
phase
excitation
⎯θ=4/16 87 92 97
⎯⎯θ=5/16 83 88 93
2W1-2-
phase
excitation
⎯θ=6/16 78 83 88
⎯⎯θ=7/16 72 77 82
2W1-2-
phase
excitation
1-2-
phase
excitation
θ=8/16 66 71 76
⎯⎯θ=9/16 58 63 68
2W1-2-
phase
excitation
⎯θ=10/16 51 56 61
⎯⎯θ=11/16 42 47 52
2W1-2-
phase
excitation
⎯θ=12/16 33 38 43
⎯⎯θ=13/16 24 29 34
2W1-2-
phase
excitation
⎯θ=14/16 15 20 25
4W1-2-
phase
excitation
⎯⎯θ=15/16 5 10 15
A-B chopping current (Note)
2-phase excitation
Vector ⎯
⎯
TQ1 =L, TQ2 =L
⎯100 ⎯
%
Reference voltage VNF ⎯TQ1, TQ2 =L (100%)
OSC =100 kHz 450 500 550 mV
tr⎯0.1 ⎯
Output transistor switching
characteristics tf
RL=2 Ω, VNF =0 V,
CL=15 pF ⎯0.1 ⎯
tpLH RESET to output ⎯0.1 ⎯
tpLH ⎯0.3 ⎯
Delay time
tpHL
7
ENABLE to output
⎯0.2 ⎯
μs
Upper side ILH ⎯―1
Output leakage current
Lower side ILL
6 VM=40 V
⎯―1
μA
Note: Maximum current (θ=0): 100%

TB6560AHQ/AFG
2007-05-24
7V1.0.3
Description of Functions
1. Excitation Settings
You can use the M1 and M2 pin settings to configure four different excitation settings. (The default is
2-phase excitation using the internal pull-down.)
Input
M2 M1
Mode
(Excitation)
L L 2-phase
L H 1-2-phase
H L 4W1-2-phase
H H 2W1-2-phase
2. Function
When the ENABLE signal goes Low level, it sets an OFF on the output. The output changes to the Initial
mode shown in the table below when the RESET signal goes Low level. In this mode, the status of the
CLK and CW/CCW pins are irrelevant.
Input
CLK CW/CCW RESET ENABLE
Output Mode
L H H CW
H H H CCW
X X L H Initial mode
X X X L Z
X: Don’t care
3. Initial Mode
When RESET is used, the phase currents are as follows. In this instance, the MO pin is L (connected to
open drain).
Excitation Mode A Phase Current B Phase Current
2-phase 100% −100%
1-2-phase 100% 0%
W1-2-phase 100% 0%
2W1-2-phase 100% 0%
4. Current Decay Settings
Output is generated by four PWM blasts; 25% decay is created by inducing decay during the last blast in
Fast mode; 50% decay is created by inducing decay during the last two blasts in Fast mode; and 100%
decay is created by inducing all four blasts in Fast mode.
If there is no input with the pull-down resistor connection then the setting is Normal.
Dcy2 Dcy1 Current Decay Setting
L L Normal 0%
L H 25% Decay
H L 50% Decay
H H 100% Decay

TB6560AHQ/AFG
2007-05-24
8V1.0.3
5. Torque Settings (Current Value)
The current ratio used in actual operations is determined in regard to the current setting due to resistance.
Configure this for extremely low torque scenarios such as when Weak Excitation mode is stopped.
If there is no input with the pull-down resistor connection then the setting is 100% torque.
TQ2 TQ1 Current Ratio
L L 100%
L H 75%
H L 50%
H H 20%
(weak excitation)
6. Protect and MO (Output Pins)
You can configure settings from the receiving side by using an open-drain connection for the output pins
and making the pull-up voltage variable.
When a given pin is in its designated state it will go ON and output at Low level.
Pin State Protect MO
Low Overheat protection operation Initial state
Z Normal operation Other than initial state
7. OSC
Output chopping waves are generated by connecting the condenser and having the CR oscillate.
The values are as shown below (roughly: ±30% margin of error).
Condenser Oscillating Frequency
1000 pF 44 kHz
330 pF 130 kHz
100 pF 400 kHz
Open-drain connection

TB6560AHQ/AFG
2007-05-24
9V1.0.3
Relationship between Enable, RESET and Output (OUT and MO)
Ex-1: ENABLE 1-2-Phase Excitation (M1: H, M2: L)
The ENABLE signal at Low level disables only the output signals. Internal logic functions proceed in
accordance with input clock signals and without regard to the ENABLE signal. Therefore output current is
initiated by the timing of the internal logic circuit after release of disable mode.
Ex-2: RESET 1-2-Phase Excitation (M1: H, M2: L)
When the RESET signal goes Low level, output goes Initial state and the MO output goes Low level (Initial
state: A Channel output current is 100%).
Once the RESET signal returns to High level, output continues from the next state after Initial from the
next raise in the Clock signal.
CLK
ENABLE
RESET
MO
100
(%)
0
−100
t0t1t2t3t7t8t9t10 t11 t12OFF
71
−71
IA
CW
CLK
ENABLE
RESET
MO
100
(%)
0
−100
t0t1t
2t 3t7t 8t4t5
t2t3
71
−71
t6
IA
CW

TB6560AHQ/AFG
2007-05-24
10 V1.0.3
2-Phase Excitation (M1: L, M2: L, CW Mode)
1-2-Phase Excitation (M1: H, M2: L, CW Mode)
CLK
MO
100
(%)
0
−100
t0t
1t 2t 3t 7
t4t
5t6
IA
CW
100
(%)
0
−100
IB
CLK
MO
100
(%)
0
−100
t0t
1t 2t 3t 7t8
t4t
5t6
71
−71
IA
100
(%)
0
−100
71
−71
IB
CW

TB6560AHQ/AFG
2007-05-24
11 V1.0.3
4W1-2-Phase Excitation (M1: L, M2: H, CW Mode)
−100 STE
−98
0
−96
−88
−92
−77
−71
−56
−63
−47
−38
−29
−20
−10
−83
10
20
29
38
47
56
63
71
77
83
88
92
96
98
100
[
%
]
A
相
B
相

TB6560AHQ/AFG
2007-05-24
12 V1.0.3
2W1-2-Phase Excitation (M1: H, M2: H, CW Mode)
IB
IA
CLK
t0t
1t 2t 3t 7t 8t4t5t 12 t13
t6
CW
MO
100
(%)
98
92
83
71
56
38
20
0
−20
−38
−56
−71
−83
−92
−98
−100
100
(%)
98
92
83
71
56
38
20
0
−20
−38
−56
−71
−83
−92
−98
−100
t9t
10 t11 t14 t17 t18
t15 t16 t19 t20 t21 t22 t23 t27 t28t24 t25 t26 t
29 t30 t31 t32

TB6560AHQ/AFG
2007-05-24
13 V1.0.3
<Input Signal Example>
It is recommended that M1 and M2 signals be changed after setting the RESET signal Low during the Initial
state (MO is Low). Even when the MO is Low, changing the RESET signal without setting the RESET signal
Low may cause the discontinuity in the current waveform.
CK
MO
M2
100
(%)
0
1-2-phase excitation
91
IA
71.4
40
−40
−71.4
−91
−100
M1
RESET
W1-2-phase excitation

TB6560AHQ/AFG
2007-05-24
14 V1.0.3
1. Current Waveform and Settings of Mixed Decay Mode
You can configure the points of the current’s shaped width (current’s pulsating flow) using 1-bit input in
Decay mode for constant-current control.
“NF” refers to the point at which the output current reaches its setting current value and “RNF” refers to
the monitoring timing of the setting current.
The smaller the MDT value, the smaller the current ripple (current wave peak), and the current’s decay
capability will fall.
NF
Normal
Mode RNF
Setting Current Value
OSC Pin
Internal
Waveform
fchop
NF
25%
Decay
Mode
RNF
MDT
Setting Current Value
NF
50%
Decay
Mode
RNF
MDT
Setting Current Value
NF
100%
Decay
Mode
RNF
Setting Current Value
Charge mode →NF: Setting current value reached →Slow mode
→Current monitoring →(When setting current value >Output
current) Charge mode
Charge mode →NF: Setting current value reached →Slow
mode →Mixed decay timing →Fast mode →Current monitoring
→(When setting current value >Output current) Charge mode
Charge mode →NF: Setting current value reached →Slow
mode →Mixed decay timing →Fast mode →Current monitoring
→(When setting current value >Output current) Charge mode
Charge mode →NF: Setting current value reached →Fast mode
→Current monitoring →(When setting current value >Output
current) Charge mode

TB6560AHQ/AFG
2007-05-24
15 V1.0.3
2. Current Control Modes (Decay Mode effect)
•Direction in which current value increases (sine wave)
•Direction in which sine wave decreases
(when a high decay ratio (MDT%) is used in Mixed Decay mode)
•Direction in which sine wave decreases
(when a low decay ratio (MDT%) is used in Mixed Decay mode)
During Mixed Decay mode and Fast Decay mode, if the setting current value < output current at RNF:
current monitoring point, the Charge mode at the next chopping cycle will disappear and the pattern will
change to Slow Fast Mode (Slow →Fast occurs at MDT). (In reality, a charge is applied momentarily to
confirm the current.)
Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show
transient response curves.
Slow Slow
Slow Slow
Fast Fast
Charge
Charge
FastCharge
FastCharge
Setting
Current
Value
Setting
Current
Value
Slow Slow
Fast
Charge
Fast
Charge
Slow
Fast
Slow
Fast
Charge
Since the current’s rate of decay is fast, its compliance
with the setting current value is also fast.
Setting
Current
Value
Setting
Current
Value
Slow
Fast
Charge
Slow
Fast
Charge
Fast
Slow
Fast
Slow
Since the current’s rate of decay is slow, its
compliance with the setting current value takes a
long time (or may not follow at all).
Setting
Current
Value
Setting
Current
Value

TB6560AHQ/AFG
2007-05-24
16 V1.0.3
3. Mixed Decay Mode Waveform (Current Waveform)
•When the NF points come after mixed decay timing
•When the output current value > Setting current value in mixed decay mode
*: Even if the output current rises above the setting current at the RNF point, a charge is applied momentarily to
confirm the current.
NF
NF
25%
Mixed
Decay
Mode
OSC Pin
Internal
Waveform
IOUT
fchop fchop
Setting
Current
Value
Setting Current
Value
RNF
MDT (Mixed Decay Timing) Points
NF
NF
25%
Mixed
Decay
Mode
IOUT
fchop fchop
Setting
Current
Value
Setting current value
RNF
MDT (Mixed Decay Timing) Points
CLK Signal Input
Switches to Fast mode after Charge mode
RNF
NF
NF
25%
MIXED
DECAY
MODE
IOUT
fchop fchop
Setting
Current
Value
CLK Signal Input
fchop
MDT (Mixed Decay Timing) Points
Setting Current
Value
RNF
RNF

TB6560AHQ/AFG
2007-05-24
17 V1.0.3
4. Fast Decay Mode Waveform
After the current value set by RNF, torque or other means is attained, the output current to load will
make the transition to full regenerative mode.
fchop
CLK Signal Input
Fast
Decay
Mode
(100%
Decay
Mode)
Setting
Current
Value
IOUT
NF
Since the setting current value > output
current, charge mode →NF →Fast Decay
mode transition will take place at even the
next cycle.
RNF
RNF
RNF
Setting
Current
Value
Transition to Charge mode for a brief moment

TB6560AHQ/AFG
2007-05-24
18 V1.0.3
5. CLK Signal and Internal CR CK Output Current Waveform
(when the CLK signal is input in the middle of Slow mode)
When the CLK signal is input, the Chopping Counter (OSC Counter) is forcibly reset at the timing of the
OSC.
As a result, the response to input data is fast in comparison to methods that don’t reset the counter.
The delay time is one OSC cycle: 10 μs @100 kHz Chopping using the Logic Block logic value.
After the OSC Counter is reset by CLK signal input, the transition is invariably made to Charge mode
for a brief moment to compare the current.
Note: Even in Fast Decay Mode, the transition is invariably made to Charge mode for a brief moment to
compare the current.
25% Mixed Decay Mode
CLK Signal Input
Setting
Current
Value
IOUT
RNF
Setting
Current
Value
fchop
OSC Pin
Internal
Waveform
Transition to Charge mode for a brief moment
The CR counter is reset here.
NF
RNF
MDT
NF
MDT
fchop fchop

TB6560AHQ/AFG
2007-05-24
19 V1.0.3
6. CLK Signal and Internal OSC Output Current Waveform
(when the CLK signal is input in the middle of Charge mode)
25% Mixed Decay Mode
CLK Signal Input
Setting
Current
Value
IOUT
RNF
Setting
Current
Value
fchop
OSC Pin
Internal
Waveform
Transition to Charge mode for a brief moment
The OSC Counter is reset here.
NF
RNF
MDT
MDT
fchop fchop

TB6560AHQ/AFG
2007-05-24
20 V1.0.3
7. CLK Signal AND Internal OSC Output Current Waveform
(when the CLK signal is input in the middle of Fast mode)
NF
25% Mixed Decay Mode
CLK Signal Input
Setting
Current
Value
IOUT
RNF
Setting
Current
Value
fchop
OSC Pin
Internal
Waveform
Transition to Charge mode for a brief moment
The OSC Counter is reset here.
fchop fchop
MDT
NF
RNF
MDT