Ublox NORA-B1 Series Quick setup guide

UBX-20027617 - R02
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NORA-B1 series
Stand-alone dual-core Bluetooth 5 low energy and IEEE
802.15.4 module
System integration manual

Abstract
This document describes the system integration of the NORA-B1 series stand-alone Bluetooth® 5.2
Low Energy and IEEE 802.15.4 modules.

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Document information
Title NORA-B1 series
Subtitle Stand-alone dual-core Bluetooth 5 low energy and IEEE 802.15.4 module
Document type System integration manual
Document number UBX-20027617
Revision and date R02 4-Feb-2021
Disclosure restriction C1-Public
Document status descriptions
Draft For functional testing. Revised and supplementary data will be published later.
Objective specification Target values. Revised and supplementary data will be published later.
Advance information Data based on early testing. Revised and supplementary data will be published later.
Early production information Data from product verification. Revised and supplementary data may be published later.
Production information Document contains the final product specification.
This document applies to the following products:
Product name Document status
NORA-B100 Advance information
NORA-B101 Advance information
NORA-B106 Advance information
☞For information about the related hardware, software, and status of listed product types, refer to
the NORA-B1 data sheet [1].
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only
permitted with the express written permission
of u-blox.
The information contained herein is provided “as is” and u
-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited
to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u
-blox at any time without notice. For the most recent
documents, visit www.u
-blox.com.
Copyright © u
-blox AG.
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only
permitted with the
express written permission of u-blox.
The information contained herein is provided “as is” and u
-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited
to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u
-blox at any time without notice. For the most recent
documents, visit www.u
-blox.com.
Copyright © u
-blox AG.

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Contents
Document information .............................................................................................................................2
Contents .......................................................................................................................................................3
1System description ............................................................................................................................7
1.1 Overview........................................................................................................................................................7
1.2 Applications .................................................................................................................................................7
1.3 Architecture .................................................................................................................................................8
1.3.1 Block diagram......................................................................................................................................8
1.3.2 Hardware options ...............................................................................................................................8
1.3.3 Software options ................................................................................................................................8
1.4 Pin assignments..........................................................................................................................................8
1.5 Supply interfaces ........................................................................................................................................8
1.5.1 Main supply input ...............................................................................................................................8
1.5.2 Digital I/O interfaces reference voltage .......................................................................................10
1.5.3 USB supply input...............................................................................................................................10
1.5.4 VDD/VDDH application circuits .....................................................................................................10
1.6 System function interfaces ....................................................................................................................10
1.6.1 Module reset ......................................................................................................................................10
1.6.2 Internal temperature sensor ..........................................................................................................11
1.7 Debug...........................................................................................................................................................11
1.7.1 Serial Wire Debug (SWD) ................................................................................................................11
1.8 GPIO pins.....................................................................................................................................................11
1.9 Analog interfaces......................................................................................................................................12
1.9.1 ADC......................................................................................................................................................12
1.9.2 Comparator........................................................................................................................................12
1.9.3 Low power comparator....................................................................................................................12
1.9.4 Analog pin options............................................................................................................................13
1.10Serial interfaces ........................................................................................................................................13
1.10.1 Universal Asynchronous Receiver/Transmitter (UART)...........................................................13
1.10.2 Serial Peripheral Interface (SPI).....................................................................................................13
1.10.3 Quad Serial Peripheral Interface (QSPI) .......................................................................................14
1.10.4 Inter-Integrated Circuit (I2C) interface ........................................................................................14
1.10.5 Pulse width modulation (PWM) interface....................................................................................15
1.10.6 Inter-IC Sound (I2S) Interface ........................................................................................................15
1.10.7 Pulse density modulation (PDM) Interface..................................................................................15
1.10.8 USB 2.0 device interface .................................................................................................................15
1.11Antenna interface.....................................................................................................................................15
1.11.1 U.FL connector – NORA-B100........................................................................................................15
1.11.2 Antenna pin – NORA-B101 .............................................................................................................16
1.11.3 Integrated antenna – NORA-B106 ................................................................................................16
1.11.4 NFC antenna......................................................................................................................................16

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1.12Reserved pins (RSVD) ..............................................................................................................................16
1.13GND pins .....................................................................................................................................................16
2Software ............................................................................................................................................. 17
2.1 Nordic Semiconductor nRF Connect SDK............................................................................................17
2.1.1 Toolchain Manager...........................................................................................................................17
2.1.2 Documentation – nRF Connect SDK.............................................................................................17
2.1.3 Support – Nordic Semiconductor DevZone development forum............................................18
2.1.4 Example code.....................................................................................................................................18
2.2 Bluetooth device (MAC) address and other production data ..........................................................19
3Flashing open CPU software......................................................................................................... 20
3.1 SWD flashing .............................................................................................................................................20
3.1.1 Flashing the software,.....................................................................................................................20
4Design-in............................................................................................................................................. 21
4.1 Overview......................................................................................................................................................21
4.2 Design for NORA family ...........................................................................................................................21
4.3 Antenna interface .....................................................................................................................................21
4.3.1 RF transmission line design (NORA-B101 only).........................................................................22
4.3.2 Antenna design (NORA-B101 only)...............................................................................................24
4.3.3 On-board antenna (NORA-B106 only)..........................................................................................27
4.4 Supply interfaces ......................................................................................................................................28
4.4.1 Module supply design ......................................................................................................................28
4.5 Debug interface .........................................................................................................................................28
4.6 Serial interfaces ........................................................................................................................................29
4.6.1 UART ...................................................................................................................................................29
4.6.2 USB ......................................................................................................................................................29
4.6.3 SPI, QSPI, I2C, I2S, PDM ..................................................................................................................30
4.7 NFC interface.............................................................................................................................................30
4.8 General high-speed layout guidelines...................................................................................................31
4.8.1 General considerations for schematic design and PCB floor-planning.................................31
4.8.2 Module placement ............................................................................................................................32
4.8.3 Layout and manufacturing.............................................................................................................33
4.9 Module footprint and paste mask .........................................................................................................33
4.10Thermal guidelines ...................................................................................................................................33
4.11ESD guidelines...........................................................................................................................................33
5Handling and soldering................................................................................................................... 35
5.1 Packaging, shipping, storage, and moisture preconditioning .........................................................35
5.2 Handling......................................................................................................................................................35
5.3 Soldering .....................................................................................................................................................35
5.3.1 Reflow soldering process ................................................................................................................35
5.3.2 Cleaning ..............................................................................................................................................36
5.3.3 Other remarks ...................................................................................................................................37
6Regulatory information and requirements............................................................................... 38

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6.1 ETSI – European market ..........................................................................................................................38
6.1.1 Compliance statement....................................................................................................................38
6.1.2 NORA-B1 software security considerations ...............................................................................38
6.1.3 Output power limitation ..................................................................................................................38
6.1.4Safety Compliance ...........................................................................................................................39
6.2 FCC/ISED – US/Canadian markets ........................................................................................................39
6.2.1 Compliance statements..................................................................................................................39
6.2.2 RF Exposure .......................................................................................................................................40
6.2.3 Antenna selection.............................................................................................................................40
6.2.4 IEEE 802.15.4 channel map limitation.........................................................................................40
6.2.5 End-product verification requirements .......................................................................................40
6.2.6 End-product labelling requirements.............................................................................................41
6.3 MIC - Japanese market............................................................................................................................42
6.3.1 Compliance statement....................................................................................................................42
6.3.2 48-bit address requirement ...........................................................................................................42
6.3.3 End-product labelling requirement...............................................................................................43
6.3.4 End-product user manual requirement........................................................................................43
6.4 NCC – Taiwanese market ........................................................................................................................43
6.4.1 Compliance statements..................................................................................................................43
6.4.2 End-product labelling requirement...............................................................................................43
6.5 KCC – South Korean market ...................................................................................................................44
6.5.1 Compliance statement....................................................................................................................44
6.5.2 End-product labeling requirements..............................................................................................44
6.5.3 End-product user manual requirements .....................................................................................45
6.6 ANATEL Brazil compliance .....................................................................................................................45
6.7 Australia and New Zealand regulatory compliance ...........................................................................45
6.8 South Africa regulatory compliance .....................................................................................................46
6.9 Integration checklist ................................................................................................................................47
6.10Pre-approved antennas list.....................................................................................................................48
6.10.1 Antenna accessories........................................................................................................................48
6.10.2 Single band antennas ......................................................................................................................48
7Technology standards compliance............................................................................................. 50
7.1 Bluetooth SIG .............................................................................................................................................50
7.2 Thread .........................................................................................................................................................50
7.3 Zigbee..........................................................................................................................................................50
7.4 USB...............................................................................................................................................................50
8Product testing................................................................................................................................. 51
8.1 u-blox in-series production test .............................................................................................................51
8.2 OEM manufacturer production test .....................................................................................................51
8.2.1 “Go/No go” tests for integrated devices ......................................................................................52
Appendix .................................................................................................................................................... 53
AGlossary .............................................................................................................................................. 53

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BAntenna reference designs ........................................................................................................... 54
Related documents ................................................................................................................................ 56
Revision history ....................................................................................................................................... 57
Contact....................................................................................................................................................... 58

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1System description
1.1 Overview
The NORA-B1 series of small stand-alone, open CPU module types support Bluetooth 5.2 device
connectivity and operate in temperatures of up to 105 °C. The modules are built on the Nordic
nRF5340 System on a Chip as an open CPU solution, where customer applications run on two Arm®
Cortex®-M33 processor cores with integrated flash and RAM memory.
The application core implements TrustZone® technology that includes an Arm Cortex-M33
processor, Digital Signal Processing (DSP) extension, Floating-point Unit (FPU), and CryptoCell™-312
with roots-of-trust and other security mechanisms for IoT and high-performance applications. The
processor is clocked at either 128 or 64 Mhz.
The network core includes an Arm® Cortex®-M33 processor with integrated 2.4 GHz radio capable of
handling Bluetooth Low Energy (LE), 802.15.4 for Thread and Zigbee, and Nordic proprietary
protocols. The processor is clocked at 64 Mhz.
With features like Direction finding (Angle-of-Arrival and Angle-of-Departure), Bluetooth long range,
and Bluetooth Low Energy (LE) Audio, NORA-B1 series modules support Bluetooth LE services such
as serial port communication, GATT, beacons, and mesh along with a range of wired interfaces,
including UART, QSPI, SPI, I2C, I2S, USB, QDEC, PDM, PWM, and ADC.
NORA-B1 series modules support multiple power supply configurations and several available
antenna options: U.FL connector (NORA B100), antenna pin (NORA-B101), and on-board PCB trace
antenna (NORA-B106).
1.2 Applications
NORA-B1 modules are suitable for a broad range of performance-oriented applications, including:
•Professional lighting
•Industrial automation
•Advanced wearables
•Smart buildings and cities
•Low power sensors
•Wireless-connected and configurable equipment
•Point-of-sale
•Medical and health devices
•Real-time location services (RTLS)
•Indoor positioning
•Asset tracking

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1.3 Architecture
1.3.1 Block diagram
Figure 1: NORA-B1 series block diagram
1.3.2 Hardware options
NORA-B1 series modules use an identical hardware configuration except for the different antenna
solutions. An external 32.768 kHz low-frequency crystal can be used if LFCLK accuracy better than
+/-250 ppm is required. DC-DC converters are integrated to provide higher efficiency across operating
modes.
1.3.3 Software options
NORA-B1 series modules are open CPU solutions that allow custom applications to be developed with
the Nordic Semiconductor nRF Connect SDK, which includes the Zephyr Real Time Operating System
(RTOS), MCUboot bootloader, and nrfxdrv drivers for optimizing connected peripheral performance.
1.4 Pin assignments
For information about the function, configuration, and characteristics of module pins, see the
NORA-B1 series data sheet [1].
1.5 Supply interfaces
1.5.1 Main supply input
NORA-B1 utilizes three power inputs, VDDH, VDD, and VBUS. These inputs connect to internal
regulators that provide the application and network core operating voltages, USB subsystem power,
and GPIO voltage references.
In normal voltage mode, a single power source is connected to both VDDH and VDD. This bypasses
the high voltage regulator (VREGH). The GPIO voltage is equal to the external power source voltage.

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Figure 2: NORA-B1 normal voltage power connection
In high voltage mode, a single power source is connected only to VDDH. The high voltage regulator
(VREGH) then generates VDD, which can be configured between 1.8 and 3.3 VDC through
VREGHVOUT in the user information configuration register (UICR) of the application core.
Figure 3: NORA-B1 high voltage power connection
The high voltage, radio voltage, and main voltage regulators have both a low drop-out regulator (LDO)
and DC-DC converter. No additional components are required to use the DC-DC converters. Once the
DC-DC converters are enabled by the application, switching between the LDO and DC-DC converter is
automatic based on the required current.
☞In high voltage mode, VDD can provide a maximum external current of 7 mA (via VDD and GPIO
pins) when VREGMAIN and VREGRADIO are in DC-DC mode and a maximum of 1 mA when they
are in mode LDO or during System OFF.

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1.5.2 Digital I/O interfaces reference voltage
The digital I/O pins operating voltage is equal to VDD, regardless of whether it is connected to an
external source or generated from the high voltage regulator. As noted above, when in high voltage
mode, VDD voltage is configured through the VREGHVOUT register in the application core UICR.
1.5.3 USB supply input
If used by the application, apply the VBUS power from the upstream USB host port to the VBUS pin.
The USB voltage regulator is an 3.3V LDO regulator used to power the USB subsystem and provide a
reference voltage for the USB_DP and USB_DM signals.
1.5.4 VDD/VDDH application circuits
The power for NORA-B1 series modules is provided through the VDD and VDDH pins. The power can
be taken from any of the following sources:
•Switching Mode Power Supply (SMPS)
•Low Drop Out (LDO) regulator
•Battery
An SMPS is the ideal choice when the available primary supply source has a higher value than the
operating supply voltage of the NORA-B1 series modules. The use of SMPS provides the best power
efficiency for the overall application and minimizes the current drawn from the main supply source.
⚠When using an SMPS source, ensure that the AC voltage ripple at the switching frequency is kept
as low as possible. The layout must be implemented to minimize impact of high frequency ringing.
The use of an LDO linear regulator is convenient for a primary supply with a relatively low voltage
where the typical 85-90% efficiency of the switching regulator leads to minimal current saving. Linear
regulators are not recommended for high voltage step-down, as they dissipate a considerable amount
of energy.
DC-DC efficiency should be evaluated as a tradeoff between active and idle duty cycles of the specific
application. Although some DC-DC conversion can be efficient for extremely light loads, DC-DC
conversion efficiency quickly degrades as the idle current drops below a few milliamps (mA), which
significantly reduces the battery life.
Due to the low current consumption and wide voltage range of NORA-B1, a battery can be used as a
main supply. The capacity of the battery should be selected to match the application. Care should be
taken to ensure that the battery can deliver the peak current required by the module. See the
NORA-B1 series data sheet [1] for the electrical specifications.
Although it is best practice to include decoupling capacitors on the supply rails close to the NORA-B1
series module, the need for additional capacitance is normally dependent on the design of the power
routing in the host system.
1.6 System function interfaces
1.6.1 Module reset
You can reset NORA-B1 by applying a low level on the nRESET input pin, which is internally pulled high
to VDD. This causes an “external” or “hardware” reset of the module. The current parameter settings
are not saved in the non-volatile memory of the module and a proper network detach is not performed.

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1.6.2 Internal temperature sensor
The radio chip in the NORA-B1 contains a temperature sensor used to monitor the temperature of the
die.
⚠The temperature sensor is located inside the radio chip and should not be used if an accurate
temperature reading of the surrounding environment is required.
1.7 Debug
1.7.1 Serial Wire Debug (SWD)
The primary interface for debugging is the SWD interface. NORA-B1 supports an SWD interface for
flashing and debugging. The two pins SWDIO and SWDCLK should be made accessible on header pins
or test points for production-line programming. Both cores use the same SWD interface.
1.8 GPIO pins
☞The code running on the application core determines the pin mapping for both application and
network cores.
In an un-configured state, NORA-B1 has 48 GPIO pins and no analog or digital interfaces. All interfaces
or functions must be allocated to a GPIO pin before use. Eight of the 48 GPIO pins are analog enabled,
meaning that they can have an analog function allocated to them. Table 1 shows the digital and
analog functions that can be assigned to a GPIO pin.
Function Description Default
NORA-B1 pin
Configurable
GPIOs
General purpose input Digital input with configurable pull-up, pull-down, edge detection
and interrupt generation
Any
General purpose output Digital output with configurable drive strength, push-pull, or
open drain output
Any
Pin disabled Pin is disconnected from the input and output buffers. All
unconfigured
Any
Timer/ counter High precision time measurement between two pulses/ pulse
counting with interrupt/event generation
Any
Interrupt/ Event trigger Interrupt/event trigger to software application/ Wake-up event Any
HIGH/LOW/Toggle on event Programmable digital level triggered by internal or external
events without CPU involvement
Any
ADC input 8/10/12/14-bit analog to digital converter Any analog
Analog comparator input Compare two voltages, capable of generating wake-up events
and interrupts
Any analog
PWM output Output simple or complex pulse width modulation waveforms Any
Serial interfaces See section 1.10, below for pin assignment restrictions Any
Table 1: GPIO custom functions configuration

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1.9 Analog interfaces
Eight of the 48 digital GPIOs can be multiplexed with the following analog functions:
•1x 8-channel ADC
•1x analog comparator*
•1x low-power analog comparator*
*Only one of the comparators can be used simultaneously.
1.9.1 ADC
The Analog-to-Digital Converter (ADC) can sample up to 200 kHz using different inputs as sample
triggers. Both one-shot conversion and continuous sampling are supported. Table 2 shows the
sample speed in correlation to the maximum source impedance. It supports 8/10/12-bit resolution.
The ADC includes 14-bit resolution if oversampling is used. Any of the eight analog inputs or VDD can
be used either as single-ended inputs or differential pairs for measuring the voltage between them.
The ADC supports the full 0 V to VDD input range. If the sampled signal level is much lower than VDD,
it is possible to lower the input range of the ADC to encompass the desired signal and obtain a higher
effective resolution. Continuous sampling can be chosen for a configurable time interval, or actively
triggered for different internal or external events – with any CPU involvement.
Table 2: Acquisition versus source impedance
1.9.2 Comparator
The comparator compares voltages from any analog pin with different references, as shown in Table
3. It supports the full 0 V to VDD input range and can generate different software events to the rest
of the system. The comparator can operate in one of the following two modes:
•Single-ended Mode: A single reference level or an upper and lower hysteresis selectable from a
64-level reference ladder with a range from 0 V to VREF, as described in Table 3.
•Differential Mode: Two analog pin voltage levels are compared, optionally with a ~35 mV
hysteresis.
1.9.3 Low power comparator
The low-power comparator operates in the same way as the normal comparator, with reduced
functionality. It can be used during system OFF modes as a wake-up source.
ACQ [us] Maximum source resistance [kΩ]
3 10
5 40
10 100
15 200
20 400
40 800

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1.9.4 Analog pin options
Table 3 shows the supported connections of the analog functions.
☞An analog pin may not be simultaneously connected to multiple functions.
Symbol Analog function Connects to
ADCP ADC single-ended or differential positive input Any analog pin or VDD
ADCN ADC differential negative input Any analog pin or VDD
VIN+ Comparator input Any analog pin
VREF Comparator single-ended mode reference
ladder input
Any analog pin, VDD, 1.2 V, 1.8V or 2.4V
VIN- Comparator differential mode negative input Any analog pin
LP_VIN+ Low-power comparator IN+ Any analog pin
LP_VIN- Low-power comparator IN- GPIO_16 or GPIO_18, 1/16 to 15/16 VDD in steps of 1/16 VDD
Table 3: Possible uses of the analog pin
1.10 Serial interfaces
1.10.1 Universal Asynchronous Receiver/Transmitter (UART)
NORA-B1 series modules support up to five UART ports for data communication. Four are available
through the application core. One is available through the network core.
The following UART signals are available:
•Data lines (RXD as input, TXD as output)
•Hardware flow control lines (CTS as input, RTS as output)
The UART can be used as either a 4-wire UART with hardware flow control or a 2-wire UART with only
TXD and RXD.
Depending on the MCUboot bootloader configuration, one of the UART interfaces on the application
core can be used for software upgrades. See section 5 for more information. It is recommended that
this UART is connected to a header for software upgrades or made available for test points.
The I/O level of the UART follows the VDD voltage and it can thus be in the range of 1.7 V and 3.6 V. A
level shifter should be used if connecting NORA-B1 to a host with any other voltage on the UART
interface.
1.10.2 Serial Peripheral Interface (SPI)
NORA-B1 supports up to six SPI ports that can operate with a maximum serial clock frequency of
8 MHz in either controller (master) or peripheral (slave) mode. Five are available through the
application core. One is available through the network core. The SPI interfaces use the following
signals:
•SCLK
•MOSI
•MISO
•CS
•DCX (Data/Command signal) - This signal is optional but is sometimes used by the SPI slaves to
distinguish between SPI commands and data.
When using the SPI interface in controller mode, it is possible to use GPIOs as additional Chip Select
(CS) signals to allow the addressing of multiple slaves.

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The application core has one high-speed SPI controller (SPIM4) that can run at up to 32 Mbps. For the
fastest SPI mode, the pins shown in Table 4 must be used.
Signal Pin name Pin number Direction Pin drive setting Description
SCK P0.08 E2 O H0H1 Serial clock, up to 32 MHz
MOSI P0.09 C2 O H0H1 Serial output data
MISO P0.10 C1 I H0H1 Serial input data
CSN P0.11 B3 O H0H1 Chip select, active low
DCX P0.12 A2 O H0H1 Data/command signal (optional)
Table 4: High-speed SPI dedicated pin assignments (SPIM4)
1.10.3 Quad Serial Peripheral Interface (QSPI)
To increase the memory size for application programs, external memory can be connected to
NORA-B1 module through the Quad Serial Peripheral port.
The QSPI is available through the application core and uses dedicated pins for the interface, as shown
in Table 5.
Signal Pin name Pin number Direction Pin drive setting Description
IO0 P0.13 D2 I/O H0H1 MOSI serial output data in single mode
Data I/O bit 0 in dual/quad mode
IO1 P0.14 E2 I/O H0H1 MISO serial input data in single mode
Data I/O bit 1 in dual/quad mode
IO2 P0.15 D1 I/O H0H1 Data I/O bit 2 in quad mode
IO3 P0.16 F2 I/O H0H1 Data I/O bit 3 in quad mode
SCK P0.17 F1 O H0H1 Serial clock, up to 96 MHz
CSN P0.18 E1 O H0H1 Chip select, active low
Table 5: QSPI dedicated pin assignments
1.10.4 Inter-Integrated Circuit (I2C) interface
NORA-B1 supports up to five I2C ports that can operate in either controller or peripheral modes. Four
ports are available through the application core. One port is available through the network core.
The I2C interfaces can be used to transfer or receive data on a 2-wire bus network. NORA-B1 can
operate at 100 kbps (standard), 250 kbps, and 400 kbps (fast) transmission speeds. The interface
uses the SCL signal to clock instructions and transfers data on the SDA signal.
External pull-up resistors are required for the I2C interface. The value of the pull-up resistor should be
selected depending on the speed and capacitance of the bus. See Electrical specifications in the
NORA-B1 series data sheet [1] for recommended resistor values.
One of the application port I2C interfaces can be used in a high-speed mode at 1 Mbps. Dedicated pins
are required for this speed.
Signal Pin name Pin number Direction Pin drive setting Description
SCL or SDA P1.02 B4 I/0 E0E1 Either SCL or SDA may be assigned to this pin
SCL or SDA P1.03 A3 I/O E0E1 Either SCL or SDA may be assigned to this pin
Table 6: High-speed TWI dedicated pin assignments
☞Set the pin drive to the S0D1 setting when assigning a I2C port to other pins.

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1.10.5 Pulse width modulation (PWM) interface
NORA-B1 supports up to four PWM instances, each with four channels. All four instances are available
through the application core. The PWM module enables the generation of pulse width modulated
signals on GPIO. The module implements an up or up-and-down counter with four PWM channels that
drive assigned GPIOs.
1.10.6 Inter-IC Sound (I2S) Interface
NORA-B1 supports a single I2S port available on the application core. The I2S module, supports the
original two-channel I2S format, and left- or right-aligned formats.
1.10.7 Pulse density modulation (PDM) Interface
NORA-B1 supports a single PDM interface available through the application core. The PDM module
enables input of pulse density modulated signals from external audio frontends, for example, digital
microphones. The PDM module generates the PDM clock and supports single-channel or dual-channel
(left and right) data input.
1.10.8 USB 2.0 device interface
NORA-B1 supports a single, full-speed (12 Mbps) USB device (peripheral) compliant with version 2.0
of the USB specification. The USB device port is available through the application core.
The pin configuration of the USB interface is as follows:
•VBUS, 5 V supply input, required to use the interface
•USB_DP, USB_DM, differential data pair
The USB interface has a dedicated power supply that requires a 5 V supply voltage for the VBUS pin.
This allows the USB interface to be used even though the rest of the module might be battery powered
or supplied by a 1.8 V supply.
1.11 Antenna interface
☞The antenna interface is different for each module variant in the NORA-B1 series.
1.11.1 U.FL connector – NORA-B100
NORA-B100 is equipped with a U.FL connector to accommodate an external antenna. The antenna
must have a characteristic impedance of 50 Ω and be designed for the 2.4 GHz band. Some external
antennas plug directly to the U.FL connector, while others use an SMA or reversed polarity SMA (RP-
SMA) connector through a short U.FL to SMA or RP-SMA adapter cable.
Antennas with an RP-SMA connector or U.FL connector are generally included in FCC, ISED, R&TTE
and MIC radio tests. Antennas with SMA connectors are included in R&TTE and MIC radio tests, but
due to FCC/ISED regulations are not included in FCC or ISED tests.
The list of approved antennas can be found in section 6.10.
NORA-B100 can be integrated with other antennas. In this instance, OEM designers must certify the
both the host system and integrated antenna with the respective regulatory agencies.

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1.11.2 Antenna pin – NORA-B101
NORA-B101 is equipped with an RF ANT pin. The ANT pin has a nominal characteristic impedance of
50 Ω and must be connected to the antenna through a 50 Ω transmission line to allow transmission
and reception of radio frequency (RF) signals in the 2.4 GHz frequency band.
Choose an antenna with optimal radiating characteristics for the best electrical performance and
overall module functionality. An internal antenna integrated on the application board, or an external
antenna that is connected to the application board through a proper 50 Ω connector, can be used.
When using an external antenna, the PCB-to-RF-cable transition must be implemented using either
a suitable 50 Ω connector, or an RF-signal solder pad (including GND) that is optimized for a 50 Ω
characteristic impedance.
1.11.2.1 Approved antenna designs
NORA-B101 comes with a pre-certified design that can save time and reduce cost during the
certification process. To leverage this benefit, customers must implement the antenna layout
specified in the u-blox reference and shown in Appendix B.
Designers integrating u-blox reference designs into an end-product are solely responsible for any
unintentional emissions produced in the end-product.
NORA-B101 can be integrated with other antennas. In these instances, OEM designers must certify
the host board design with the applicable regulatory agencies.
1.11.3 Integrated antenna – NORA-B106
NORA-B106 is equipped with an integrated antenna. This simplifies the integration, as there is no
need to do an RF trace design on the host PCB. This also means that the pre-certification of NORA-B1,
with the antenna, is even valid for the finished product design. Less time in the test lab reduces the
development overhead and allows for a quicker time to market. NORA-B106 modules include PCB
trace antennas with technology licensed from Proant AB.
1.11.4 NFC antenna
NORA-B1 series modules include a Near Field Communication (NFC) interface, capable of operating
as a 13.56 MHz NFC tag at a bit rate of 106 kbps. As an NFC tag, data can be read from or written to
NORA-B1 modules using an NFC reader; however, NORA-B1 modules are not capable of reading other
tags or initiating NFC communications. Two pins are available for connecting to an external NFC
antenna: NFC1 and NFC2.
1.12 Reserved pins (RSVD)
Do not connect reserved (RSVD) pins. The reserved pins are allocated for future interfaces and
functionality.
1.13 GND pins
Good connection of the module GND pins, using a solid ground layer in the host application board, is
necessary for correct RF performance. Proper grounding provides a thermal heat sink for the module
and reduces the possibility of EMC issues.
See the Module footprint and paste mask and Thermal guidelines sections for information about
ground plane design.

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2Software
NORA-B1 series modules are used as open CPU modules in which applications developed with the
Nordic Semiconductor nRF Connect SDK can be run. The most recent application development
guidelines are found at the nRF Connect SDK documentation for application development [17] and
working with the nRF53 [18]. These sections provide details about Zephyr, MCUboot, and the nRF53
in NORA-B1.
2.1 Nordic Semiconductor nRF Connect SDK
With a broad selection of drivers and libraries, the Nordic Semiconductor nRF Connect SDK provides
a rich development environment for various devices and applications. The software development kit
(SDK) is delivered through the nRF Connect for Desktop application provided by Nordic
Semiconductor.
nRF Connect SDK includes the SEGGER Embedded Studio IDE, Zephyr Project RTOS, MCUboot
secure bootloader, and nrfxdrv libraries for the peripherals provided within the nRF5340 chip. The
SDK can be downloaded from Nordic Semiconductor’s website [15]
After installing the main program, select the following software modules for installation:
•Bluetooth Low Energy – general tool for development and testing with Bluetooth Low Energy
•Toolchain Manager – install and manage tools to develop with the nRF Connect SDK
Other software modules in nRF Connect for Desktop can be useful but are not required for application
development.
2.1.1 Toolchain Manager
Application development is done using the suite of tools installed by the Toolchain Manager.
1. Open the Toolchain Manager. Several versions of the nRF Connect SDK are offered. If this is a
new install, select the latest one for installation.
2. Select an installation folder. If the default is not used, ensure that no spaces are included in the
given folder path.
3. The installation can take several minutes to download and several more to install the SEGGER
Embedded Studio IDE, git tools, bash shell, a fork of the Zephyr RTOS source code, Nordic’s
custom source code (nrfxdrv), and MCUboot. While waiting, check the information at the “First
steps to build” button. The displayed information is customized to the installation folder selected
above. If the EVK-NORA-B1 development board is used for development, the examples given for
the nRF5340 DK (pca_10095) can be used without modification.
4. Once the install is complete, open the IDE.
5. From this point, follow the “First steps to build” instructions presented by the Toolchain Manager
and nRF Connect SDK online documentation.
☞Nordic Semiconductor provides a free, unlimited commercial license for SEGGER Embedded
Studio.
2.1.2 Documentation – nRF Connect SDK
Full documentation for the nRF Connect SDK is continually updated on the dedicated nRF Connect
SDK documentation website [16].

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2.1.3 Support – Nordic Semiconductor DevZone development forum
For support with questions about the development of software using the nRF Connect SDK, refer to
the Nordic Semiconductor DevZone support site [19]. Public discussions and private tickets are
available on the site, where the Nordic engineers and forum members respond to all contributions.
2.1.4 Example code
The EVK-NORA-B10x evaluation kits are compatible with most nRF Connect SDK projects that
support the nRF5340 DK without any changes required. See the EVK-NORA-B1 user guide [3] for
information about installing and using the development tools.

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2.2 Bluetooth device (MAC) address and other production data
NORA-B1 modules are programmed from the factory with a unique, public Bluetooth device address
stored in the OTP[0] and OTP[1] registers of the User Information Configuration Registers (UICR) in
the application core. The device addresses are duplicated in the CUSTOMER[0] and CUSTOMER[1]
registers in the UICR of the network core.
The Bluetooth device address consists of the IEEE Organizationally Unique Identifier (OUI) combined
with the hexadecimal digits that are printed within a 2D data matrix, as described in the Labeling and
ordering section of the product data sheet [1]. The Bluetooth device address is stored in little-endian
format. The two most significant bytes of the OTP[1] and CUSTOMER[1] registers are unused and
assigned the value 0xFF to complete the 32-bit register.
UICR Register in application core Address Description Remarks
OTP[0] 0x00FF8100 0xAA = Bluetooth_addr [5] IEEE OUIError! Bookmark not defined.
OTP[0] 0x00FF8101 0xBB = Bluetooth_addr [4] IEEE OUIError! Bookmark not defined.
OTP[0] 0x00FF8102 0xCC = Bluetooth_addr [3] IEEE OUIError! Bookmark not defined.
OTP[0] 0x00FF8103 0xDD = Bluetooth_addr [2] Example - actual value printed on label
OTP[1] 0x00FF8104 0xEE = Bluetooth_addr [1] Example - actual value printed on label
OTP[1] 0x00FF8105 0xFF = Bluetooth_addr [0] Example - actual value printed on label
OTP[1] 0x00FF8106 0xFF Unused
OTP[1] 0x00FF8107 0xFF Unused
Table 7: Bluetooth device address in application core
UICR Register in network core Address Description Remarks
CUSTOMER[0] 0x01FF8300 0xAA = Bluetooth_addr [5] IEEE OUIError! Bookmark not defined.
CUSTOMER[0] 0x01FF8301 0xBB = Bluetooth_addr [4] IEEE OUIError! Bookmark not defined.
CUSTOMER[0] 0x01FF8302 0xCC = Bluetooth_addr [3] IEEE OUIError! Bookmark not defined.
CUSTOMER[0] 0x01FF8303 0xDD = Bluetooth_addr [2] Example - actual value printed on label
CUSTOMER[1] 0x01FF8304 0xEE = Bluetooth_addr [1] Example - actual value printed on label
CUSTOMER[1] 0x01FF8305 0xFF = Bluetooth_addr [0] Example - actual value printed on label
CUSTOMER[1] 0x01FF8306 0xFF Unused
CUSTOMER[1] 0x01FF8307 0xFF Unused
Table 8: Bluetooth device address in network core
If write-protection is not enabled, the address can be read and written through the nRF Connect SDK
utilities. See also reference [16].
$ nrfjprog.exe --memrd 0x10001080 --n 8
The memory area can be saved and, if the flash is erased, written back later using the savebin and
loadbin utilities in the SEGGER J-link tool suite.
The entire UICR memory area can hold other valuable information. Use the following commands to
save the entire UCIR memory area:
$ nrfjprog.exe --readuicr uicr.hex
...
$ nrfjprog.exe --program uicr.hex
For additional information and instructions on saving and using the public Bluetooth device address,
see reference [7].

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3Flashing open CPU software
Both the application and network cores of the NORA-B1 modules are flashed over a common SWD
interface.
3.1 SWD flashing
A SEGGER J-Link programmer is required to program the NORA-B1 module flash over the SWD port.
☞The EVK-NORA-B10x evaluation kit includes a J-LINK-OB that is used to program and debug
the on-board NORA-B1 as well as the target hardware for ANNA-B1, BMD-3, NINA-B1,
NINA-B3, NINA-B4, and NORA-B1 modules.
SEGGER Embedded Studio can be used to interactively program and debug application core and
network core code.
At the command line, the west tool provided by the nRF Connect SDK provides a simple method of
programming both cores of the NORA-B1 module in one step. After building the project, open a
command prompt or terminal window, navigate to the build folder and enter:
west flash
An alternate method is to use the nRF Command Line Tools [20]. Open a command prompt and
execute the following commands to erase the NORA-B1:
nrfjprog -f NRF53 --coprocessor CP_NETWORK --eraseall
nrfjprog -f NRF53 --eraseall
Navigate to the build folder of the network sample and execute the following command to program
the network core:
nrfjprog -f NRF53 --coprocessor CP_NETWORK --program zephyr/zephyr.hex
Then navigate to the build folder of the application sample and enter the following command to
program the application core:
nrfjprog -f NRF53 --program zephyr/zephyr.hex
Finally, reset the NORA-B1 module with:
nrfjprog --pinreset
☞External SEGGER J-Link debuggers work with NORA-B1 modules.
☞The EVK-NORA-B1 evaluation kit incorporates an onboard debugger and can therefore be
flashed without any external debugger.
☞The EVK-NORA-B1 evaluation kit onboard debugger can also be used to program custom
hardware with Nordic Semiconductor-based u-blox modules during development. The
debugger is not intended for use in production environments.
3.1.1 Flashing the software,
⚠Flashing the software erases the Bluetooth device address, which must be rewritten to the module
after flashing. This is done manually or with the use of a script. Ensure that you make a note of
your Bluetooth device address before continuing with the flashing procedure. See section 2.2 for
additional information.