Ublox LARA-R2 series Quick setup guide

LARA-R2 series
LTE Cat 1 / EGPRS modules
System Integration Manual
Abstract
This document describes the features and the system integration of
LARA-R2 series multi-mode cellular modules.
These modules are a complete, cost efficient and performance
optimized LTE Cat 1 / 2G multi-mode solution covering up to three
LTE bands and up to two 2G GSM/EGPRS bands in the very small
and compact LARA form factor.
.
www.u-blox.com
UBX-16010573 - R02

LARA-R2 series - System Integration Manual
UBX-16010573 - R02
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Document Information
Title
LARA-R2 series
Subtitle
LTE Cat 1 / EGPRS modules
Document type
System Integration Manual
Document number
UBX-16010573
Revision, date
R02
03-Oct-2016
Document status
Objective Specification
Document status explanation
Objective Specification
Document contains target values. Revised and supplementary data will be published later.
Advance Information
Document contains data based on early testing. Revised and supplementary data will be published later.
Early Production Information
Document contains data from product verification. Revised and supplementary data may be published later.
Production Information
Document contains the final product specification.
This document applies to the following products:
Name
Type number
Modem version
Application version
SDN / IN / PCN
LARA-R204
LARA-R204-02B-00
TBD
TBD
TBD
LARA-R211
LARA-R211-02B-00
30.17
A01.00
UBX-16024242
u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in
whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or
any part thereof without the express permission of u-blox is strictly prohibited.
The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either
express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose
of the information. This document may be revised by u-blox at any time. For most recent documents, please visit www.u-blox.com.
Copyright © 2016, u-blox AG
u-blox®is a registered trademark of u-blox Holding AG in the EU and other countries. Microsoft and Windows are either registered
trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or
trademarks mentioned in this document are property of their respective owners.

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Preface
u-blox Technical Documentation
As part of our commitment to customer support, u-blox maintains an extensive volume of technical
documentation for our products. In addition to our product-specific technical data sheets, the following manuals
are available to assist u-blox customers in product design and development.
AT Commands Manual: This document provides the description of the AT commands supported by the
u-blox cellular modules.
System Integration Manual: This document provides the description of u-blox cellular modules’ system
from the hardware and the software point of view, it provides hardware design guidelines for the optimal
integration of the cellular modules in the application device and it provides information on how to set up
production and final product tests on application devices integrating the cellular modules.
Application Notes: These documents provide guidelines and information on specific hardware and/or
software topics on u-blox cellular modules. See Related documents for a list of application notes related to
your cellular module.
How to use this Manual
The LARA-R2 series System Integration Manual provides the necessary information to successfully design in and
configure these u-blox cellular modules.
This manual has a modular structure. It is not necessary to read it from the beginning to the end.
The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to module integration and performance.
A warning symbol indicates actions that could negatively impact or damage the module.
Questions
If you have any questions about u-blox cellular Integration:
Read this manual carefully.
Contact our information service on the homepage http://www.u-blox.com
Technical Support
Worldwide Web
Our website (http://www.u-blox.com) is a rich pool of information. Product information and technical documents
can be accessed 24h a day.
By E-mail
If you have technical problems or cannot find the required information in the provided documents, contact the
closest Technical Support office. To ensure that we process your request as soon as possible, use our service pool
email addresses rather than personal staff email addresses. Contact details are at the end of the document.
Helpful Information when Contacting Technical Support
When contacting Technical Support, have the following information ready:
Module type (e.g. LARA-R204) and firmware version
Module configuration
Clear description of your question or the problem
A short description of the application
Your complete contact details

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Contents
Preface ................................................................................................................................3
Contents..............................................................................................................................4
1System description.......................................................................................................7
1.1 Overview .............................................................................................................................................. 7
1.2 Architecture.......................................................................................................................................... 9
1.3 Pin-out ............................................................................................................................................... 11
1.4 Operating modes................................................................................................................................ 16
1.5 Supply interfaces ................................................................................................................................ 18
1.5.1 Module supply input (VCC) ......................................................................................................... 18
1.5.2 RTC supply input/output (V_BCKP) .............................................................................................. 25
1.5.3 Generic digital interfaces supply output (V_INT)........................................................................... 26
1.6 System function interfaces.................................................................................................................. 27
1.6.1 Module power-on ....................................................................................................................... 27
1.6.2 Module power-off ....................................................................................................................... 29
1.6.3 Module reset ............................................................................................................................... 31
1.6.4 Module / host configuration selection ......................................................................................... 31
1.7 Antenna interface............................................................................................................................... 32
1.7.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 32
1.7.2 Antenna detection interface (ANT_DET) ...................................................................................... 34
1.8 SIM interface ...................................................................................................................................... 34
1.8.1 SIM card interface ....................................................................................................................... 34
1.8.2 SIM card detection interface (SIM_DET) ....................................................................................... 34
1.9 Data communication interfaces .......................................................................................................... 35
1.9.1 UART interface ............................................................................................................................ 35
1.9.2 USB interface............................................................................................................................... 46
1.9.3 HSIC interface ............................................................................................................................. 49
1.9.4 DDC (I2C) interface ...................................................................................................................... 50
1.9.5 SDIO interface ............................................................................................................................. 51
1.10 Audio interface ............................................................................................................................... 52
1.10.1 Digital audio interface ................................................................................................................. 52
1.11 Clock output................................................................................................................................... 53
1.12 General Purpose Input/Output (GPIO) ............................................................................................. 53
1.13 Reserved pins (RSVD) ...................................................................................................................... 53
1.14 System features............................................................................................................................... 54
1.14.1 Network indication ...................................................................................................................... 54
1.14.2 Antenna detection ...................................................................................................................... 54
1.14.3 Jamming detection ...................................................................................................................... 54
1.14.4 Dual stack IPv4/IPv6 ..................................................................................................................... 55
1.14.5 TCP/IP and UDP/IP ....................................................................................................................... 55
1.14.6 FTP .............................................................................................................................................. 55
1.14.7 HTTP ........................................................................................................................................... 55

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1.14.8 SSL/TLS........................................................................................................................................ 56
1.14.9 Bearer Independent Protocol ....................................................................................................... 57
1.14.10 AssistNow clients and GNSS integration................................................................................... 57
1.14.11 Hybrid positioning and CellLocate®.......................................................................................... 58
1.14.12 Wi-Fi integration ...................................................................................................................... 60
1.14.13 Firmware upgrade Over AT (FOAT) .......................................................................................... 60
1.14.14 Firmware update Over The Air (FOTA)...................................................................................... 60
1.14.15 Smart temperature management ............................................................................................. 61
1.14.16 Power Saving ........................................................................................................................... 63
2Design-in.....................................................................................................................64
2.1 Overview ............................................................................................................................................ 64
2.2 Supply interfaces ................................................................................................................................ 65
2.2.1 Module supply (VCC) .................................................................................................................. 65
2.2.2 RTC supply (V_BCKP)................................................................................................................... 79
2.2.3 Interface supply (V_INT)............................................................................................................... 81
2.3 System functions interfaces ................................................................................................................ 82
2.3.1 Module power-on (PWR_ON) ...................................................................................................... 82
2.3.2 Module reset (RESET_N) .............................................................................................................. 83
2.3.3 Module / host configuration selection ......................................................................................... 84
2.4 Antenna interface............................................................................................................................... 85
2.4.1 Antenna RF interface (ANT1 / ANT2) ........................................................................................... 85
2.4.2 Antenna detection interface (ANT_DET) ...................................................................................... 92
2.5 SIM interface ...................................................................................................................................... 94
2.6 Data communication interfaces ........................................................................................................ 100
2.6.1 UART interface .......................................................................................................................... 100
2.6.2 USB interface............................................................................................................................. 105
2.6.3 HSIC interface ........................................................................................................................... 107
2.6.4 DDC (I2C) interface .................................................................................................................... 109
2.6.5 SDIO interface ........................................................................................................................... 113
2.7 Audio interface................................................................................................................................. 114
2.7.1 Digital audio interface ............................................................................................................... 114
2.8 General Purpose Input/Output (GPIO) ............................................................................................... 118
2.9 Reserved pins (RSVD) ........................................................................................................................ 119
2.10 Module placement ........................................................................................................................ 119
2.11 Module footprint and paste mask ................................................................................................. 120
2.12 Thermal guidelines ........................................................................................................................ 121
2.13 ESD guidelines .............................................................................................................................. 122
2.13.1 ESD immunity test overview ...................................................................................................... 122
2.14 Schematic for LARA-R2 series module integration ......................................................................... 123
2.15 Design-in checklist ........................................................................................................................ 124
2.15.1 Schematic checklist ................................................................................................................... 124
2.15.2 Layout checklist ......................................................................................................................... 125
2.15.3 Antenna checklist ...................................................................................................................... 125

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3Handling and soldering ...........................................................................................126
3.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 126
3.2 Handling........................................................................................................................................... 126
3.3 Soldering .......................................................................................................................................... 127
3.3.1 Soldering paste.......................................................................................................................... 127
3.3.2 Reflow soldering ....................................................................................................................... 127
3.3.3 Optical inspection...................................................................................................................... 128
3.3.4 Cleaning.................................................................................................................................... 128
3.3.5 Repeated reflow soldering......................................................................................................... 129
3.3.6 Wave soldering.......................................................................................................................... 129
3.3.7 Hand soldering .......................................................................................................................... 129
3.3.8 Rework...................................................................................................................................... 129
3.3.9 Conformal coating .................................................................................................................... 129
3.3.10 Casting...................................................................................................................................... 129
3.3.11 Grounding metal covers ............................................................................................................ 129
3.3.12 Use of ultrasonic processes........................................................................................................ 129
4Approvals..................................................................................................................130
4.1 Product certification approval overview............................................................................................. 130
4.2 US Federal Communications Commission notice............................................................................... 131
4.2.1 Safety warnings review the structure ......................................................................................... 131
4.2.2 Declaration of conformity.......................................................................................................... 131
4.2.3 Modifications ............................................................................................................................ 131
4.3 Industry Canada notice ..................................................................................................................... 132
4.3.1Declaration of Conformity ......................................................................................................... 132
4.3.2 Modifications ............................................................................................................................ 132
4.4 R&TTED / RED and European Conformance CE mark ........................................................................ 134
5Product testing .........................................................................................................135
5.1 u-blox in-series production test......................................................................................................... 135
5.2 Test parameters for OEM manufacturer ............................................................................................ 136
5.2.1 “Go/No go” tests for integrated devices.................................................................................... 136
5.2.2 Functional tests providing RF operation ..................................................................................... 136
Appendix ........................................................................................................................138
AMigration between SARA-U2 and LARA-R2 ...........................................................138
A.1 Overview .......................................................................................................................................... 138
A.2 Pin-out comparison between SARA-U2 and LARA-R2 ....................................................................... 141
A.3 Schematic for SARA-U2 and LARA-R2 integration............................................................................. 143
BGlossary ....................................................................................................................144
Related documents.........................................................................................................146
Revision history..............................................................................................................147
Contact............................................................................................................................148

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1System description
1.1 Overview
The LARA-R2 series comprises LTE Cat 1 / 2G multi-mode modules supporting up to three LTE bands and up to
two 2G GSM/(E)GPRS bands for voice and/or data transmission in the very small LARA LGA form-factor (26.0 x
24.0 mm), easy to integrate in compact designs:
LARA-R204 is designed primarily for operation in North America (on Verizon network)
LARA-R211 is designed primarily for operation in Europe, Asia and other countries
LARA-R2 series modules are form-factor compatible with u-blox SARA, LISA and TOBY cellular module families:
this facilitates easy migration from u-blox GSM/GPRS, CDMA, UMTS/HSPA, and LTE high data rate modules,
maximizes the investments of customers, simplifies logistics, and enables very short time-to-market.
The modules are ideal for applications that are transitioning to LTE from 2G and 3G, due to the long term
availability and scalability of LTE networks.
With a range of interface options and an integrated IP stack, the modules are designed to support a wide range
of data-centric applications. The unique combination of performance and flexibility make these modules ideally
suited for medium speed M2M applications, such as smart energy gateways, remote access video cameras,
digital signage, telehealth and telematics.
LARA-R2 series modules support Voice over LTE (VoLTE) and voice service over 2G (CSFB) for applications that
require voice, such as security and surveillance systems.
Table 1 summarizes the main features and interfaces of LARA-R2 series modules.
Model
Region
Radio Access Technology
Positioning
Interfaces
Audio
Features
Grade
LTE Bands
GSM Bands
GNSS via modem
Assist Now Software
CellLocate®
UART
USB 2.0
HSIC
SDIO
DDC (I2C)
GPIOs
Analog audio
Digital audio
Network indication
Antenna supervisor
Rx Diversity
Jamming detection
Embedded TCP/UDP stack
Embedded HTTP,FTP,SSL
FOTA
eCall / ERA GLONASS
Dual stack IPv4/IPv6
Standard
Professional
Automotive
LARA-R204
North
America
4,13
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
LARA-R211
Europe,
APAC
3,7,20
900,1800
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Table 1: LARA-R2 series main features summary

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Table 2 reports a summary of cellular radio access technologies characteristics of LARA-R2 series modules.
4G LTE
2G GSM/GPRS/EDGE
3GPP Release 9
Long Term Evolution (LTE)
Evolved Uni.Terrestrial Radio Access (E-UTRA)
Frequency Division Duplex (FDD)
DL Rx diversity
3GPP Release 9
Enhanced Data rate GSM Evolution (EDGE)
GSM EGPRS Radio Access (GERA)
Time Division Multiple Access (TDMA)
DL Advanced Rx Performance
Band support1:
LARA-R204:
Band 13 (750 MHz)
Band 4 (1700 MHz)
LARA-R211:
Band 20 (800 MHz)
Band 3 (1800 MHz)
Band 7 (2600 MHz)
Band support:
LARA-R211:
E-GSM 900 MHz
DCS 1800 MHz
LTE Power Class
Power Class 3 (23 dBm)
GSM/GPRS (GMSK) Power Class
Power Class 4 (33 dBm) for E-GSM band
Power Class 1 (30 dBm) for DCS band
EDGE (8-PSK) Power Class
Power Class E2 (27 dBm) for E-GSM band
Power Class E2 (26 dBm) for DCS band
Data rate
LTE category 1:
up to 10.3 Mb/s DL, 5.2 Mb/s UL
Data Rate2
GPRS multi-slot class 123, CS1-CS4,
up to 85.6 kb/s DL/UL
EDGE multi-slot class 123, MCS1-MCS9,
up to 236.8 kb/s DL/UL
Table 2: LARA-R2 series LTE and 2G characteristics
LARA-R2 modules provide Voice over LTE (VoLTE) as well as Circuit-Switched-Fall-Back (CSFB) audio capability
4
.
1
LARA-R2 series modules support all the E-UTRA channel bandwidths for each operating band according to 3GPP TS 36.521-1 .
2
GPRS/EDGE multi-slot class determines the number of timeslots available for upload and download and thus the speed at which data can
be transmitted and received, with higher classes typically allowing faster data transfer rates.
3
GPRS/EDGE multi-slot class 12 implies a maximum of 4 slots in DL (reception) and 4 slots in UL (transmission) with 5 slots in total.
4
Not supported by LARA-R204 module “02” product version.

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1.2 Architecture
Figure 1 summarizes the internal architecture of LARA-R2 series modules.
Cellular
Base-band
processor
Memory
Power Management Unit
26 MHz
32.768 kHz
ANT1
RF
transceiver
ANT2
V_INT (I/O)
V_BCKP (RTC)
VCC (Supply)
SIM
USB
HSIC
Power On
External Reset
PAs
LNAs Filters
Filters
Duplexer
Filters
PAs
LNAs Filters
Filters
Duplexer
Filters
LNAs FiltersFilters
LNAs FiltersFilters
Switch
Switch
DDC(I2C)
SDIO
UART
ANT_DET
Host Select
GPIO
Digital audio (I2S)
Figure 1: LARA-R2 series modules simplified block diagram
LARA-R2 series modules internally consists of the RF, Baseband and Power Management sections here described
with more details than the simplified block diagrams of Figure 1.
RF section
The RF section is composed of RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and RF switches.
Tx signal is pre-amplified by RF transceiver, then output to the primary antenna input/output port (ANT1) of the
module via power amplifier (PA), SAW band pass filters band, specific duplexer and antenna switch.
Dual receiving paths are implemented according to LTE Receiver Diversity radio technology supported by the
modules as LTE category 1 User Equipments: incoming signal is received through the primary (ANT1) and the
secondary (ANT2) antenna input ports which are connected to the RF transceiver via specific antenna switch,
diplexer, duplexer, LNA, SAW band pass filters.
RF transceiver performs modulation, up-conversion of the baseband I/Q signals for Tx, down-conversion and
demodulation of the dual RF signals for Rx. The RF transceiver contains:
Single chain high linearity receivers with integrated LNAs for multi band multi mode operation,
Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM,
RF synthesizer,
VCO.
Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver
RF switches connect primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx path
SAW duplexers and band pass filters separate the Tx and Rx signal paths and provide RF filtering
26 MHz voltage-controlled temperature-controlled crystal oscillator generates the clock reference in
active-mode or connected-mode.

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Baseband and power management section
The Baseband and Power Management section is composed of the following main elements:
A mixed signal ASIC, which integrates
Microprocessor for control functions
DSP core for cellular Layer 1 and digital processing of Rx and Tx signal paths
Memory interface controller
Dedicated peripheral blocks for control of the USB, SIM and generic digital interfaces
Interfaces to RF transceiver ASIC
Memory system, which includes NAND flash and LPDDR2 RAM
Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC
Voltage sources for external use: V_BCKP and V_INT
Hardware power on
Hardware reset
Low power idle-mode support
32.768 kHz crystal oscillator to provide the clock reference in the low power idle-mode, which can be set by
enable power saving configuration using the AT+UPSV command.

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1.3 Pin-out
Table 3 lists the pin-out of the LARA-R2 series modules, with pins grouped by function.
Function
Pin Name
Pin No
I/O
Description
Remarks
Power
VCC
51, 52, 53
I
Module supply input
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for description and requirements.
See section 2.2.1 for external circuit design-in.
GND
1, 3, 5, 14, 20,
22, 30, 32, 43,
50, 54, 55, 57,
58, 60, 61, 63,
64, 65-96
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
V_BCKP
2
I/O
RTC supply
input/output
V_BCKP = 1.8 V (typical) generated by internal regulator
when valid VCC supply is present.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
V_INT
4
O
Generic Digital
Interfaces supply
output
V_INT = 1.8 V (typical), generated by internal DC/DC
regulator when the module is switched on.
Test-Point for diagnostic access is recommended.
See section 1.5.3 for functional description.
See section 2.2.3 for external circuit design-in.
System
PWR_ON
15
I
Power-on input
Internal 10 kpull-up resistor to V_BCKP.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
18
I
External reset input
Internal 10 kpull-up resistor to V_BCKP.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
HOST_SELECT
21
I/O
Selection of module /
host configuration
Not supported by “02” product versions.
Pin available to select, enable, connect, disconnect and
subsequently re-connect the HSIC interface.
Test-Point for diagnostic access is recommended.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.
Antenna
ANT1
56
I/O
Primary antenna
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and compliance
of the device integrating the module with applicable
required certification schemes.
See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ANT2
62
I
Secondary antenna
Rx only for Rx diversity.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and compliance
of the device integrating the module with applicable
required certification schemes.
See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ANT_DET
59
I
Input for antenna
detection
ADC for antenna presence detection function.
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
SIM
VSIM
41
O
SIM supply output
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
39
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 kpull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
38
O
SIM clock
3.25 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
40
O
SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UART
RXD
13
O
UART data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW update
by u-blox EasyFlash tool and diagnostic.
Test-Point and series 0 for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
12
I
UART data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT commands, data communication, FOAT, FW update
by u-blox EasyFlash tool and diagnostic.
Internal active pull-up to V_INT.
Test-Point and series 0 for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
11
O
UART clear to send
output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10
I
UART ready to send
input
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR
6
O
UART data set ready
output
1.8 V output, Circuit 107 (DSR) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI
7
O
UART ring indicator
output
1.8 V output, Circuit 125 (RI) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DTR
9
I
UART data terminal
ready input
1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to V_INT.
Test-Point and series 0 for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DCD
8
O
UART data carrier
detect output
1.8 V input, Circuit 109 (DCD) in ITU-T V.24.
Test-Point and series 0 for diagnostic access recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
USB
VUSB_DET
17
I
USB detect input
VBUS (5 V typical) USB supply generated by the host must
be connected to this input pin to enable the USB interface.
If the USB interface is not used by the Application Processor,
Test-Point for diagnostic / FW update access is recommended
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
USB_D-
28
I/O
USB Data Line D-
USB interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [9] are part of the
USB pin driver and need not be provided externally.
If the USB interface is not used by the Application Processor,
Test-Point for diagnostic / FW update access is recommended
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
USB_D+
29
I/O
USB Data Line D+
USB interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [9] are part of the
USB pin driver and need not be provided externally.
If the USB interface is not used by the Application Processor,
Test-Point for diagnostic / FW update access is recommended
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
HSIC
HSIC_DATA
99
I/O
HSIC USB data line
Not supported by “02” product versions.
USB High-Speed Inter-Chip compliant interface for AT
commands, data communication, FOAT, FW update by u-
blox EasyFlash tool and diagnostic.
50 nominal characteristic impedance.
Test-Point for diagnostic / FW update access is recommended.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
HSIC_STRB
100
I/O
HSIC USB strobe line
Not supported by “02” product versions.
HSIC interface for AT commands, data communication,
FOAT, FW update by u-blox EasyFlash tool and diagnostic.
50 nominal characteristic impedance.
Test-Point for diagnostic / FW update access is recommended.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
DDC
SCL
27
O
I2C bus clock line
1.8 V open drain, for communication with I2C-slave devices.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDA
26
I/O
I2C bus data line
1.8 V open drain, for communication with I2C-slave devices.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
SDIO
SDIO_D0
47
I/O
SDIO serial data [0]
Not supported by “02” product versions.
SDIO interface for communication with u-blox Wi-Fi module
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D1
49
I/O
SDIO serial data [1]
Not supported by “02” product versions.
SDIO interface for communication with u-blox Wi-Fi module
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D2
44
I/O
SDIO serial data [2]
Not supported by “02” product versions.
SDIO interface for communication with u-blox Wi-Fi module
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D3
48
I/O
SDIO serial data [3]
Not supported by “02” product versions.
SDIO interface for communication with u-blox Wi-Fi module
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_CLK
45
O
SDIO serial clock
Not supported by “02” product versions.
SDIO interface for communication with u-blox Wi-Fi module
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_CMD
46
I/O
SDIO command
Not supported by “02” product versions.
SDIO interface for communication with u-blox Wi-Fi module
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
Audio
I2S_TXD
35
O /
I/O
I2S transmit data /
GPIO
I2S transmit data output, alternatively configurable as GPIO.
I2S not supported by LARA-R204 module ‘02’ product version.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_RXD
37
I /
I/O
I2S receive data /
GPIO
I2S receive data input, alternatively configurable as GPIO.
I2S not supported by LARA-R204 module ‘02’ product version.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_CLK
36
I/O /
I/O
I2S clock /
GPIO
I2S serial clock, alternatively configurable as GPIO.
I2S not supported by LARA-R204 module ‘02’ product version.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
I2S_WA
34
I/O /
I/O
I2S word alignment /
GPIO
I2S word alignment, alternatively configurable as GPIO.
I2S not supported by LARA-R204 module ‘02’ product version.
See sections 1.10 and 1.12 for functional description.
See sections 2.7 and 2.8 for external circuit design-in.
Clock
output
GPIO6
19
O
Clock output
1.8 V configurable clock output.
See section 1.11 for functional description.
See section 2.7 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
GPIO
GPIO1
16
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO2
23
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
GPIO5
42
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.12 for functional description.
See section 2.8 for external circuit design-in.
Reserved
RSVD
33
N/A
RESERVED pin
This pin must be connected to ground.
See sections 1.13 and 2.9
RSVD
31, 97, 98
N/A
RESERVED pin
Internally not connected. Leave unconnected.
See sections 1.13 and 2.9
Table 3: LARA-R2 series modules pin definition, grouped by function

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1.4 Operating modes
LARA-R2 series modules have several operating modes. The operating modes defined in Table 4 and described in
detail in Table 5 provide general guidelines for operation.
General Status
Operating Mode
Definition
Power-down
Not-Powered Mode
VCC supply not present or below operating range: module is switched off.
Power-Off Mode
VCC supply within operating range and module is switched off.
Normal operation
Idle-Mode
Module processor core runs with 32 kHz reference generated by the internal oscillator.
Active-Mode
Module processor core runs with 26 MHz reference generated by the internal oscillator.
Connected-Mode
RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference.
Table 4: Module operating modes definition
Mode
Description
Transition between operating modes
Not-Powered
Module is switched off.
Application interfaces are not accessible.
When VCC supply is removed, the module enters not-powered mode.
When in not-powered mode, the modules cannot be switched on by
PWR_ON, RESET_N or RTC alarm.
When in not-powered mode, the modules can be switched on applying
VCC supply (see 2.3.1) so that the module switches from not-powered
to active-mode.
Power-Off
Module is switched off: normal shutdown by an
appropriate power-off event (see 1.6.2).
Application interfaces are not accessible.
When the module is switched off by an appropriate power-off event
(see 1.6.2), the module enters power-off mode from active-mode.
When in power-off mode, the modules can be switched on by
PWR_ON, RESET_N or RTC alarm (see 2.3.1): the module switches
from power-off to active-mode.
When in power-off mode, the modules enter not-powered mode by
removing VCC supply.
Idle
Module is switched on with application
interfaces temporarily disabled or suspended:
the module is temporarily not ready to
communicate with an external device by means
of the application interfaces as configured to
reduce the current consumption.
The module enters the low power idle-mode
whenever possible if power saving is enabled by
AT+UPSV (see u-blox AT Commands Manual [2])
reducing power consumption (see 1.5.1.4).
The CTS output line indicates when the UART
interface is disabled/enabled due to the module
idle/active-mode according to power saving and
HW flow control settings (see 1.9.1.3, 1.9.1.4).
Power saving configuration is not enabled by
default: it can be enabled by AT+UPSV (see the
u-blox AT Commands Manual [2]).
The module automatically switches from active-mode to idle-mode
whenever possible if power saving is enabled (see sections 1.5.1.4,
1.9.1.4, 1.9.2.4 and to the u-blox AT Commands Manual [2], AT+UPSV
command).
The module wakes up from idle to active mode in the following events:
Automatic periodic monitoring of the paging channel for the
paging block reception according to network conditions (see
1.5.1.3, 1.9.1.4)
Automatic periodic enable of the UART interface to receive and
send data, if AT+UPSV=1 power saving is set (see 1.9.1.4)
Data received on UART interface, according to HW flow control
(AT&K) and power saving (AT+UPSV) settings (see 1.9.1.4)
RTS input set ON by the host DTE, with HW flow control disabled
and AT+UPSV=2 (see 1.9.1.4)
DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.1.4)
USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.2)
The connected USB host forces a remote wakeup of the module
as USB device (see 1.9.2.4)
The connected u-blox GNSS receiver forces a wakeup of the
cellular module using the GNSS Tx data ready function over the
GPIO3 pin (see 1.9.4)
The connected SDIO device forces a wakeup of the module as
SDIO host (see 1.9.5)
RTC alarm occurs (see u-blox AT Commands Manual [2], +CALA)

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Mode
Description
Transition between operating modes
Active
The module is ready to communicate with an
external device by means of the application
interfaces unless power saving configuration is
enabled by the AT+UPSV command (see
sections 1.5.1.3, 1.9.1.4 and to the u-blox AT
Commands Manual [2]).
When the module is switched on by an appropriate power-on event
(see 2.3.1), the module enters active-mode from not-powered or
power-off mode.
If power saving configuration is enabled by the AT+UPSV command,
the module automatically switches from active to idle-mode whenever
possible and the module wakes up from idle to active-mode in the
events listed above (see idle to active transition description).
When a voice call or a data call is initiated, the module switches from
active-mode to connected-mode.
Connected
A voice call or a data call is in progress.
The module is ready to communicate with an
external device by means of the application
interfaces unless power saving configuration is
enabled by the AT+UPSV command (see
sections 1.5.1.3, 1.9.1.4 and the u-blox AT
Commands Manual [2]).
When a data or voice connection is initiated, the module enters
connected-mode from active-mode.
Connected-mode is suspended if Tx/Rx data is not in progress, due to
connected discontinuous reception and fast dormancy capabilities of
the module and according to network environment settings and
scenario. In such case, the module automatically switches from
connected to active mode and then, if power saving configuration is
enabled by the AT+UPSV command, the module automatically switches
to idle-mode whenever possible. Vice-versa, the module wakes up from
idle to active mode and then connected mode if RF Tx/Rx is necessary.
When a data connection is terminated, the module returns to the
active-mode.
Table 5: Module operating modes description
Figure 2 describes the transition between the different operating modes.
Switch ON:
•Apply VCC
If power saving is enabled
and there is no activity for
a defined time interval
Any wake up event described
in the module operating
modes summary table above
Incoming/outgoing call or
other dedicated device
network communication
No RF Tx/Rx in progress,
Call terminated,
Communication dropped
Remove VCC
Switch ON:
•PWR_ON
•RTC alarm
•RESET_N
Not
powered
Power off
ActiveConnected Idle
Switch OFF:
•AT+CPWROFF
Figure 2: Operating modes transition

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1.5 Supply interfaces
1.5.1 Module supply input (VCC)
The modules must be supplied via the three VCC pins that represent the module power supply input.
The VCC pins are internally connected to the RF power amplifier and to the integrated Power Management Unit:
all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators,
including V_BCKP Real Time Clock supply, V_INT digital interfaces supply and VSIM SIM card supply.
During operation, the current drawn by the LARA-R2 series modules through the VCC pins can vary by several
orders of magnitude. This ranges from the pulse of current consumption during GSM transmitting bursts at
maximum power level in connected-mode (as described in section 1.5.1.2) to the low current consumption
during low power idle-mode with power saving enabled (as described in section 1.5.1.4).
LARA-R211 modules provide separate supply inputs over the three VCC pins:
VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding most of
the total current drawn of the module when RF transmission is enabled during a voice/data call
VCC pin #51 represents the supply input for the internal baseband Power Management Unit and the internal
transceiver, demanding minor part of the total current drawn of the module when RF transmission is
enabled during a voice/data call
Figure 3 provides a simplified block diagram of LARA-R2 series modules internal VCC supply routing.
53
VCC
52
VCC
51
VCC
LARA-R204
Power
Management
Unit
Memory
Baseband
Processor
Transceiver
RF PMU
LTE PA
53
VCC
52
VCC
51
VCC
LARA-R211
Power
Management
Unit
Memory
Baseband
Processor
Transceiver
RF PMU
LTE / 2G PAs
Figure 3: LARA-R2 series modules internal VCC supply routing simplified block diagram

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1.5.1.1 VCC supply requirements
Table 6 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the suggestions to
properly design a VCC supply circuit compliant to the requirements listed in Table 6.
VCC supply circuit affects the RF compliance of the device integrating LARA-R2 series modules
with applicable required certification schemes as well as antenna circuit design. Compliance is
guaranteed if the VCC requirements summarized in the Table 6 are fulfilled.
Item
Requirement
Remark
VCC nominal voltage
Within VCC normal operating range:
3.30 V min. / 4.40 V max
RF performance is guaranteed when VCC PA voltage is
inside the normal operating range limits.
RF performance may be affected when VCC PA voltage is
outside the normal operating range limits, though the
module is still fully functional until the VCC voltage is
inside the extended operating range limits.
VCC voltage during
normal operation
Within VCC extended operating range:
3.00 V min. / 4.50 V max
VCC voltage must be above the extended operating
range minimum limit to switch-on the module.
The module may switch-off when the VCC voltage drops
below the extended operating range minimum limit.
Operation above VCC extended operating range is not
recommended and may affect device reliability.
VCC average current
Support with adequate margin the highest averaged
VCC current consumption value in connected-mode
conditions specified in LARA-R2 series Data Sheet [1]
The highest averaged VCC current consumption can be
greater than the specified value according to the actual
antenna mismatching, temperature and VCC voltage.
See 1.5.1.2, 1.5.1.3 for connected-mode current profiles.
VCC peak current
Support with margin the highest peak VCC current
consumption value in connected-mode conditions
specified in LARA-R2 series Data Sheet [1]
The specified highest peak of VCC current consumption
occurs during GSM single transmit slot in 850/900 MHz
connected-mode, in case of mismatched antenna.
See 1.5.1.2 for 2G connected-mode current profiles.
VCC voltage drop
during 2G Tx slots
Lower than 400 mV
VCC voltage drop directly affects the RF compliance with
applicable certification schemes.
Figure 5 describes VCC voltage drop during Tx slots.
VCC voltage ripple
during 2G/LTE Tx
Noise in the supply has to be minimized
VCC voltage ripple directly affects the RF compliance with
applicable certification schemes.
Figure 5 describes VCC voltage ripple during Tx slots.
VCC under/over-shoot
at start/end of Tx slots
Absent or at least minimized
VCC under/over-shoot directly affects the RF compliance
with applicable certification schemes.
Figure 5 describes VCC voltage under/over-shoot.
Table 6: Summary of VCC supply requirements

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1.5.1.2 VCC current consumption in 2G connected-mode
When a GSM call is established, the VCC consumption is determined by the current consumption profile typical
of the GSM transmitting and receiving bursts.
The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which
is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for
determining the average current consumption.
If the module is transmitting in 2G single-slot mode (as in GSM talk mode) in the 850 or 900 MHz bands, at the
maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), the current consumption
can reach an high peak / pulse (see LARA-R2 series Data Sheet [1]) for 576.9 µs (width of the transmit slot/burst)
with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM
TDMA (Time Division Multiple Access).
If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption
figures are quite less high than the one in the low bands, due to 3GPP transmitter output power specifications.
During a GSM call, current consumption is not so significantly high in receiving or in monitor bursts and it is low
in the bursts unused to transmit / receive.
Figure 4 shows an example of the module current consumption profile versus time in GSM talk mode.
Time [ms]
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
Current [A]
200 mA
60-120 mA
1900 mA
Peak current depends
on TX power and
actual antenna load
GSM frame
4.615 ms
(1 frame = 8 slots)
60-120 mA
10-40 mA
0.0
1.5
1.0
0.5
2.0
Figure 4: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)
Figure 5 illustrates VCC voltage profile versus time during a GSM call, according to the related VCC current
consumption profile described in Figure 4.
Time
undershoot
overshoot
ripple
drop
Voltage
3.8 V
(typ)
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
RX
slot
unused
slot
unused
slot
TX
slot
unused
slot
unused
slot
MON
slot
unused
slot
GSM frame
4.615 ms
(1 frame = 8 slots)
GSM frame
4.615 ms
(1 frame = 8 slots)
Figure 5: Description of the VCC voltage profile versus time during a GSM call (1 TX slot, 1 RX slot)