Xilinx 7 Series User manual

7 Series FPGAs
Clocking Resources
User Guide
UG472 (v1.5) July 13, 2012
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7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012
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UG472 (v1.5) July 13, 2012 www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/11 1.0 Initial Xilinx release.
03/28/11 1.1 Updated disclaimer and copyright on page 2. Updated Clocking Architecture Overview
and Figure 2-2. Revised the discussion in Clock-Capable Inputs including adding
Table 1-1 and Figure 2-1. Revised some of the Global Clock Buffers descriptions. Revised
the description under Figure 2-17. Updated the I/O Clock Buffer—BUFIO section.
Updated Figure 2-20. Updated the Regional Clock Buffer—BUFR section. Updated the
description in Table 2-8. Revised Figure 2-23. Added the BUFMRCE to the BUFMR
Primitive section including Figure 2-25. Added BUFHCE to the Horizontal Clock
Buffer—BUFH, BUFHCE section. Moved Clock Gating for Power Savings.
Updated the MMCMs and PLLs section. Revised the Frequency Synthesis Only Using
Integer Divide section including Figure 3-4. Revised the discussion around adjacent
regions in CLKOUT[0:6] – Output Clocks. Updated the examples after Equation 3-11.
Moved and revised VHDL and Verilog Templates and the Clocking Wizard.
Added Appendix A, Multi-Region Clocking.
05/31/11 1.2 Added section on 7 Series FPGAs Clocking Differences from Previous FPGA
Generations.
Updated Figure 2-2. Clarified discussion in Clock-Capable Inputs section including
removing Table 1-1: Migration of devices in the same package with different top/bottom
alignments. Redrew Figure 2-4, Figure 2-16, Figure 2-18, and Figure 2-22.
Updated description of CLKOUT[0:6] in Table 3-5. Updated CLKFBSTOPPED –
Feedback Clock Status, page 79. Clarified the MMCM/PLL relationship including
updating Figure 3-10. Added more information to the Phase Shift section, including
Equation 3-5.
Revised Figure A-6 and Figure A-7. Added Appendix B, Clocking Resources and
Connectivity Variations per Clock Region.
10/27/11 1.3 Moved 7 Series FPGAs Clocking Differences from Previous FPGA Generations. Added
Clock Buffer Selection Considerations. Clarified description in Clock-Capable Inputs.
Added another note after Figure 2-22, page 51. Added the Stacked Silicon Interconnect
Clocking section.
Updated Figure 3-6, page 69. Clarified descriptions in Frequency Synthesis Using
Fractional Divide in the MMCM, page 69, Interpolated Fine Phase Shift in Fixed or
Dynamic Mode in the MMCM, page 71, Determine the Input Frequency, page 72,
CLKOUT[0:6] – Output Clocks, page 78, and Reference Clock Switching, page 87.
Revised description of STARTUP_WAIT, page 81. Updated RST description in Table 3-5,
page 74. Updated CLKOUT[0]_DIVIDE_F allowed values in Table 3-7, page 79. Updated
Clock Network Deskew, page 68 adding Figure 3-12, page 88.
Updated Table B-1 and added Table B-2.
02/16/12 1.4 Replaced “clocking backbone” with “clock backbone” and “clocking region” with “clock
region” throughout.
Added Chapter 1, Clocking Overview, containing 7 Series FPGAs Clocking Differences
from Previous FPGA Generations from Chapter 2 and Summary of Clock Connectivity
from Appendix B. Updated Table 1-1. Removed XC7A8, XC7A15, XC7A30T, and
XC7A50T from Table 1-2.
Added Clock-Capable Inputs. Updated Global Clocking Resources, including BUFMR
Primitive. Updated Horizontal Clock Buffer—BUFH, BUFHCE. Updated paragraph
before Figure 2-27.
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7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012
02/16/12 1.4
(Cont’d)
In introductory paragraph of High-Performance Clocks, removed description of HPCs
connecting to OSERDES and buffers. Replaced cross reference to UG429, 7 Series FPGAs
Migration Methodology Guide, with UG872, Large FPGA Methodology Guide. Updated
Stacked Silicon Interconnect Clocking. Replaced SRL with SLR in Figure 2-28. Added
Figure 2-30.
Removed hold block from Figure 3-2. Updated clock frequencies in Frequency Synthesis
Only Using Integer Divide. Replaced 64 with 63 in Equation 3-4. Updated Interpolated
Fine Phase Shift in Fixed or Dynamic Mode in the MMCM. Updated pin description of
LOCKED in Table 3-5. Updated LOCKED. In Table 3-7, updated type and allowed
values of CLKOUT[0]_DIVIDE_F and CLKFBOUT_MULT_F, and description of
STARTUP_WAIT and COMPENSATION. In Table 3-8, added STARTUP_WAIT and
updated description of COMPENSATION. Replaced GTX with GT in Figure 3-10.
Updated Dynamic Reconfiguration Port.
Added Appendix B, Clocking Resources and Connectivity Variations per Clock Region.
07/13/12 1.5 Updated paragraph after Figure 1-4. Added bullet about spread spectrum support to
Key Differences from Virtex-6 FPGAs. Updated BUFG and BUFH pins, and removed
IBUFDS_GTE2.O/IBUFDS_GTE2.ODIV2 pin from Table 1-1. Updated Table 1-2.
Updated note 5 in Table 2-1. Added Figure 2-28.
Updated last sentence of Introduction. Updated DO[15:0] – Dynamic Reconfiguration
Output Bus. Added SS_EN, SS_MODE, and SS_MOD_PERIOD to Table 3-7. Added
Spread-Spectrum Clock Generation.
Date Version Revision
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UG472 (v1.5) July 13, 2012
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 1: Clocking Overview
Clocking Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Routing Resources Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CMT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Buffers, Management, and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Series FPGAs Clocking Differences from Previous FPGA Generations . . . . . 19
Key Differences from Virtex-6 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Key Differences from Spartan-6 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Summary of Clock Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clocking Differences in 7 Series FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 2: Clock Routing Resources
Clock Buffer Selection Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock-Capable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Single Clock Driving a Single CMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Single Clock Driving Multiple CMTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clock-Capable Input Pin Placement Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Global Clocking Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Tree and Nets - GCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Global Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Global Clock Buffer Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Additional Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Regional Clocking Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Clock-Capable I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I/O Clock Buffer—BUFIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
BUFIO Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
BUFIO Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Regional Clock Buffer—BUFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
BUFR Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
BUFR Attributes and Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
BUFR Use Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Regional Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Multi-Region Clock Buffer—BUFMR/BUFMRCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
BUFMR Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Horizontal Clock Buffer—BUFH, BUFHCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
High-Performance Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Clock Gating for Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table of Contents
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Stacked Silicon Interconnect Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Placement of Clocking Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clock Buffer Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Chapter 3: Clock Management Tile
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MMCMs and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
General Usage Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MMCM and PLL Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MMCME2_BASE and PLLE2_BASE Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MMCME2_ADV and PLLE2_ADV Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Clock Network Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Frequency Synthesis Only Using Integer Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Frequency Synthesis Using Fractional Divide in the MMCM . . . . . . . . . . . . . . . . . . . . 69
Jitter Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
VCO Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Minimum and Maximum Input Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Duty Cycle Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Phase Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Dynamic Phase Shift Interface in the MMCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MMCM Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MMCM/PLL Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Determine the Input Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Determine the M and D Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MMCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PLL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MMCM and PLL Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
MMCM Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PLL Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MMCM Clock Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Detailed VCO and Output Counter Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Reference Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Missing Input Clock or Feedback Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MMCM and PLL Use Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Clock Network Deskew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MMCM with Internal Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Zero Delay Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
CMT to CMT Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Spread-Spectrum Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MMCM Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
VHDL and Verilog Templates and the Clocking Wizard . . . . . . . . . . . . . . . . . . . . . 97
Appendix A: Multi-Region Clocking
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Clocking Across Multiple Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BUFMR Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Clock Alignment Across Clock Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Single Buffer per Clock Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Driving Multiple BUFIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Driving Multiple BUFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Multiple Buffers Per Clock Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Driving Multiple BUFRs (with Divide) and BUFIO . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Driving Multiple BUFRs (With and Without Divide) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
BUFR Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Appendix B: Clocking Resources and Connectivity Variations per
Clock Region
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UG472 (v1.5) July 13, 2012
Preface
About This Guide
Xilinx® 7 series FPGAs include three scalable optimized FPGA families that are all
designed for lowest power to enable a common design to scale across families for optimal
power, performance, and cost. The Artix™-7 family is optimized for lowest cost and
absolute power for the highest volume applications. The Virtex®-7 family is optimized for
highest system performance and capacity. The Kintex™-7 family is an innovative class of
FPGAs optimized for the best price-performance. This guide serves as a technical reference
describing the 7 series FPGAs clocking resources.
This 7 series FPGAs clocking resources user guide, part of an overall set of documentation
on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/7.
Guide Contents
This manual contains the following chapters:
•Chapter 1, Clocking Overview
•Chapter 2, Clock Routing Resources
•Chapter 3, Clock Management Tile
•Appendix A, Multi-Region Clocking
•Appendix B, Clocking Resources and Connectivity Variations per Clock Region
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/support/documentation/index.htm.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
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Preface: About This Guide
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