Xilinx VC707 User manual

July 2012
VC707 MIG Design Creation
XTP143

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Revision History
Date Version Description
07/25/12 3.0 Regenerated for 14.2.
05/08/12 2.0 Regenerated for 14.1. AR44540 fixed. AR45653 fixed. AR46866 fixed.
04/12/12 1.1 Minor updates.
03/09/12 1.0 Initial version for 13.4.

Overview
VC707 Board
VC707 Setup
Generate MIG Example Design
Modifications to Example Design
Compile Example Design
Run MIG Example Design
References
Note: This presentation applies to the VC707

Xilinx VC707 Board
Note: Presentation applies to the VC707

ISE Software Requirement
Xilinx ISE 14.2 software
–Apply AR50886
Note: Presentation applies to the VC707

ChipScope Pro Software Requirement
Xilinx ChipScope Pro 14.2 software
Note: Presentation applies to the VC707

Generate MIG Example Design
Open the CORE Generator
Start →All Programs →Xilinx Design Tools →ISE Design Suite 14.2 →
ISE Design Tools →32-bit Tools →CORE Generator
Create a new project; select File →New Project
Note: Presentation applies to the VC707

Generate MIG Example Design
Create a project in a
new directory
named:
–vc707_mig_design
Select Part
Set the Part (as
shipped on
the VC707):
–Family: Virtex7
–Device: xc7vx485t
–Package: ffg1761
–Speed Grade: -2
Select Generation
Note: Presentation applies to the VC707

Generate MIG Example Design
Under Generation
–Set the Design Entry
to Verilog
Click OK
Note: Presentation applies to the VC707

Generate MIG Example Design
Right click on MIG 7 Series Version 1.5
–Select Customize and Generate
Note: Presentation applies to the VC707