Acromag AcroPack Series User manual

AP500/AP520/AP521 AcroPack
Serial Communication Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-7037 U.S.A.
Tel: [phone]
Fax: [phone]
Copyright 2016, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501053D

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 1 - http://www.acromag.com
- 1 -
www.acromag.com
Table of Contents
1.0 GENERAL INFORMATION..........................................................................................4
1.1 Intended Audience .......................................................................................................4
1.2 Preface.........................................................................................................................4
1.2.1 Trademark, Trade Name and Copyright Information .................................................................. 4
1.2.2 Class A Product Warning............................................................................................................. 4
1.2.3 Environmental Protection Statement ......................................................................................... 4
1.3 AcroPack Information –All Models...............................................................................5
Figure 1.1 - AP500 Block Diagram ................................................................................................. 5
Figure 1.2 - AP520 Block Diagram ................................................................................................. 5
Figure 1.3 - AP521 Block Diagram ................................................................................................. 5
1.3.1 Ordering Information ................................................................................................................. 6
Table 1.1 Ordering Options ........................................................................................................... 6
1.3.2 Key Features............................................................................................................................... 6
1.3.3 Key Features PCIe Interface ........................................................................................................ 7
1.4 Signal Interface Products ..............................................................................................7
1.5 Software Support .........................................................................................................7
Windows............................................................................................................................................ 7
VxWorks............................................................................................................................................ 7
Linux.................................................................................................................................................. 7
1.6 References ...................................................................................................................8
2.0 PREPARATION FOR USE..............................................................................................9
2.1 Unpacking and Inspecting.............................................................................................9
2.2 Installation Considerations .........................................................................................10
2.3 Board Configuration ...................................................................................................10
2.4 Field I/O Connector ....................................................................................................10
Table 2.1 Field I/O Connector Pin Assignments .......................................................................... 11
Table 2.2 Field I/O 68 PinConnector Assignments ...................................................................... 13
2.5 RS-422/485 Termination (AP521 Only)........................................................................17

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2.6 Noise and Grounding Considerations ..........................................................................17
2.7 Logic Interface Connector ...........................................................................................17
Table 2.3: Logic Interface Connections........................................................................................ 18
3.0 PROGRAMMING INFORMATION........................................................................... 19
3.1 PCI Configuration Registers ..........................................................................................19
Table 3.1 PCI Configuration Registers ......................................................................................... 20
3.2 UART and Device Configuration Registers.....................................................................21
Table 3.2 UART and Device Configuration Registers ................................................................... 21
Table 3.3 Device Configuration Registers.................................................................................... 21
3.2.1 UART Channel Configuration Registers........................................................................................22
FIFO Data Loading and Unloading n 32-bit Format ..................................................................... 22
Table 3.4 UART Channel Configuration Registers........................................................................ 23
3.2.2 RHR - Receiver Holding Register (READ Only) ..............................................................................24
3.2.3 THR - Transmitter Holding Register (WRITE Only)........................................................................25
3.2.4 DLL & DLM - Divisor Latch Registers, Ports A-H (R/W) .................................................................25
Table 3.5 Baud Rate Divisors(14.7456MHZ)................................................................................ 26
3.2.5 IER - Interrupt Enable Register (R/W) ..........................................................................................27
Table 3.6 Interrupt Enable Register............................................................................................. 27
3.2.6 ISR - Interrupt Status Register (READ Only) .................................................................................28
Table 3.7 Interrupt source........................................................................................................... 28
3.2.7 FCR - FIFO Control Register (WRITE Only) ....................................................................................29
Table 3.8 FIFO Control Register................................................................................................... 29
3.2.8 LCR - Line Control Register (Read/Write).....................................................................................30
Table 3.9 Line Control Registers .................................................................................................. 30
3.2.9 MCR - Modem Control Register (R/W) ........................................................................................32
Table 3.10 Modem Control Register............................................................................................ 32
3.2.10 LSR - Line Status Register (Read/Write-Restricted)....................................................................33
Table 3.11 Line Status Register.................................................................................................... 33
3.2.11 MSR - Modem Status Register (Read/Write) .............................................................................35
Table 3.12 Modem Status Register.............................................................................................. 35
3.2.12 SCR - Scratch Pad (Read/Write) .................................................................................................37
3.2.13 Enhanced Register Set ...............................................................................................................37
3.2.14 EFR - Enhanced Feature Register (Read/Write)..........................................................................37
Table 3.13 EFR - Enhanced Feature Register ............................................................................... 37
3.2.15 XON/XOFF-1,2 Registers (R/W) .................................................................................................39
3.3 Model Identification.....................................................................................................39
Table 3.14 Model ID .................................................................................................................... 39
4.0 SERVICE AND REPAIR............................................................................................... 40

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4.1 Service and Repair Assistance.....................................................................................40
4.2 Preliminary Service Procedure ....................................................................................40
4.3 Where to Get Help......................................................................................................40
5.0 SPECIFICATIONS......................................................................................................... 41
5.1 Physical......................................................................................................................41
5.2 Power Requirements ..................................................................................................41
Table 5.1 Model ID ...................................................................................................................... 41
5.3 Environmental Considerations....................................................................................41
5.3.1 Operating Temperature.............................................................................................................41
5.3.2 Other Environmental Requirements ..........................................................................................42
5.3.2.1 Relative Humidity .......................................................................................................... 42
5.3.2.2 Isolation ......................................................................................................................... 42
5.3.3 Vibration and Shock Standards..................................................................................................42
5.3.4 EMC Directives ..........................................................................................................................42
5.4 Reliability Prediction ....................................................................................................43
Table 5.4 MTBF (all models).................................................................................................................43
5.5 PCIe Bus Specifications ...............................................................................................43
CERTIFICATE OF VOLATILITY ........................................................................................ 44
REVISION HISTORY ............................................................................................................ 45

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
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1.0 GENERAL INFORMATION
1.1 Intended Audience
This user's manual was written for technically qualified personnel who will
be working with I/O devices using the AcroPack module. It is not intended
for a general, non-technical audience that is unfamiliar with AcroPack
devices and their application.
1.2 Preface
The information contained in this manual is subject to change without
notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.
Acromag makes no warranty of any kind with regard to this material,
including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. Further, Acromag assumes no responsibility
for any errors that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual. No part
of this manual may be copied or reproduced in any form, without the prior
written consent of Acromag,
1.2.1 Trademark, Trade Name and Copyright Information
© 2016 by Acromag Incorporated.
All rights reserved. Acromag and Xembedded are registered trademarks of
Acromag Incorporated. All other trademarks, registered trademarks, trade
names, and service marks are the property of their respective owners.
1.2.2 Class A Product Warning
This is a Class A product. In a domestic environment this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
1.2.3 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final
disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
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1.3 AcroPack Information –All Models
The AcroPack IO modules are based on the PCI Express Mini Card
Electromechanical specification and are 70mm in length with an additional
100 pin field I/O connector.
The AcroPack is 19.05mm longer than the full length mini PCIe card at
50.95mm. It has the same mPCIe board width of 30mm and uses the same
mPCIe standard board hold down standoff and screw keep out areas.
The AP500 uses the 16550-compatible Exar 17v354 UART and contains four
RS-232 serial communication ports that provide full EIA/TIA-232E modem
line support, including RTS, CTS, DTR, DSR, DCD, and RI.
Figure 1.1 - AP500 Block Diagram
Exar 17V354
UART
Mini--PCIe Connector
PCIe x1 RS-232
Transceivers (4)
RS-232
Ports (4)
Field-I/O Connector
The AP520 uses the 16550-compatible Exar 17v358 UART and contains eight
RS-232 serial communication ports that provide EIA/TIA-232E modem line
support, including RTS, and CTS.
Figure 1.2 - AP520 Block Diagram
Exar 17V358
UART
Mini--PCIe Connector
PCIe x1 RS-232
Transceivers (8)
RS-232
Ports (8)
Field-I/O Connector
The AP521 uses the 16550-compatible Exar 17v358 UART and contains eight
RS-422/485 serial communication ports that provide EIA-TIA-422B or full
duplex EIA-485 line support. Termination and biasing resistors are installed
by default. For non-terminated ports please consult the factory.
Figure 1.3 - AP521 Block Diagram
Exar 17V358
UART
Mini--PCIe Connector
PCIe x1 RS-422/485
Transceivers (8)
RS-422/485
Ports (8)
Field-I/O Connector

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USER’S MANUAL
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1.3.1 Ordering Information
The AcroPack ordering options are given in the following table.
Table 1.1 Ordering Options
Model Number
#/Type of
Serial Ports
Operational Temperature
Range
AP500E-LF1,2
4x RS-232
-40oC to 85°C1,2
AP520-64E-LF1,2
8x RS-232
-40oC to 85°C1,2
AP521-64E-LF1,2
8x RS-422/485
-40oC to 85°C1,2
Note 1: For all models listed - all standoffs and screws required for an air cooled
application are provided with the carrier.
Note 2: A conduction cooled application will require purchase of AcroPack
Accessory AP-CC-01 (Conduction Cool Kit).
1.3.2 Key Features
High Density –Provides 4 (AP500) or 8 (AP520/521) serial ports on
each module. Multiple modules mounted on a carrier board provide
up to 24 serial ports in a single VPX system slot or up to 16 serial
ports in a PCIe system slot.
16550 compatible –Exar Quad or Octal UART with 16550-
compatible register set.
256-Byte FIFO Buffers –256-byte TX and RX FIFOs with
programmable trigger levels.
Programmable Baud Rate –Each individual channel has its own
programmable baud rate generator with fractional divisor. While
the UART supports data rates up to 31.25Mbps, the serial
transceivers only support data rates up to 500kbps (AP500/520) or
20Mbps (AP521).
Interrupt Support –Individually controlled transmit, receive, line
status, and data set interrupts may be generated.
General Purpose Timer/Counter –This 16-bit timer/counter uses
an internal 125MHz clock as the clock source and can be set to be a
single-shot or re-triggerable and is capable of generating an
interrupt.
Individual Modem Control Signals –The AP500 module provides all
modem control signals: RTS, CTS, DTR, DSR, DCD, and RI. The AP520
only provides RTS and CTS.

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1.3.3 Key Features PCIe Interface
PCIe Bus –The AP module includes a PCI Express Generation 1
interface operating at a bus speed of 2.5 Gbps with one lane in each
direction.
Compatibility –PCI Express Base Specification v2.1 compliant PCI
Express Endpoint.
1.4 Signal Interface Products
This AcroPack module will mate directly to all Acromag AP carriers. Once
connected, the module is accessed via a 50 pin front panel connector.
The cables and termination panels are also available. For optimum
performance with the AP5XX communication modules, use of the shortest
possible length of shielded I/O cable is recommended.
1.5Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows,
and VxWorks.
Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. This software (model APSW-
API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that
are compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented
as a library of “C” functions which link with existing user code to make
possible simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The
software is implemented as a library of “C” functions which link with existing
user code to make possible simple control of all Acromag AcroPack modules.

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
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1.6 References
The following resources regarding AcroPack modules are available for
download on Acromag’s website or by contacting your sales representative.
PCI Express MINI Card Electromechanical Specification, REV 1.2
http://www.pcisig.com
Exar 17v354 High Performance Quad PCI Express UART datasheet
Exar 17v358 High Performance Octal PCI Express UART datasheet

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USER’S MANUAL
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2.0 PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications
of power, wiring, component, sensor, or software failures in designing any
type of control or monitoring system. This is especially important where
personal injury or the loss of economic property or human life is possible. It
is important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not
ship or store this product near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its
original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the Acromag Limited Warranty.
2.1 Unpacking and Inspecting
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.
The board utilizes static-sensitive components and should only be handled at
a static-safe workstation.

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2.2 Installation Considerations
IMPORTANT: Adequate air
circulation must be provided to
prevent a temperature rise
above the maximum operating
temperature.
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, adequate air circulation must be provided to
prevent a temperature rise above the maximum operating temperature and
to prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
2.3 Board Configuration
Power should be removed from the board when installing AP modules,
cables, termination panels, and field wiring. Model AP500/520/UART
communication boards have no hardware jumpers or switches to configure.
2.4 Field I/O Connector
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack module as board to board interconnect.
This connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec
connector on the carrier. The stack height is 4.5mm.
Threaded metric M2.5 screws and spacers are supplied with the module to
provide additional stability for harsh environments.
Pin assignments are unique to each AP5xx model. Table 2.1 lists signal pin
assignments for the 100-pin module/carrier field I/O connectors, as well as
the 50-pin CHAMP and ribbon I/O connectors on the carrier. Every other pin
of the 100 pin module connector are left unconnected in order to meet the
minimum creepage distance required for 60 Volt isolation (which is not
implemented on the AP500/520/521 modules).

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Table 2.1 Field I/O Connector Pin Assignments
Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 50-pin
Ribbon I/O
Connector
Pin#
Carrier 50-pin
CHAMP I/O
Connector
Pin#
AP500
Module
Function
AP520
Module
Function
AP521
Module
Function
2
Field I/O 1
1
1
GND
GND
GND
1
Field I/O 2
2
26
RI_A*
TXD_A
TXD-_A
4
RSVD/ISOL
3
RSVD/ISOL
6
Field I/O 3
3
2
DTR_A*
RXD_A
TXD+_A
5
Field I/O 4
4
27
CTS_A*
RTS_A*
RXD-_A
8
RSVD/ISOL
7
RSVD/ISOL
10
Field I/O 5
5
3
TXD_A
CTS_A*
RXD+_A
9
Field I/O 6
6
28
RTS_A*
GND
GND
12
RSVD/ISOL
11
RSVD/ISOL
14
Field I/O 7
7
4
RXD_A
TXD_B
TXD-_B
13
Field I/O 8
8
29
DSR_A*
RXD_B
TXD+_B
16
RSVD/ISOL
15
RSVD/ISOL
18
Field I/O 9
9
5
DCD_A*
RTS_B*
RXD-_B
17
Field I/O 10
10
30
GND
CTS_B*
RXD+_B
20
RSVD/ISOL
19
RSVD/ISOL
22
Field I/O 11
11
6
RI_B*
GND
GND
21
Field I/O 12
12
31
DTR_B*
TXD_C
TXD-_C
24
RSVD/ISOL
23
RSVD/ISOL
26
Field I/O 13
13
7
CTS_B*
RXD_C
TXD+_C
25
Field I/O 14
14
32
TXD_B
RTS_C*
RXD-_C
28
RSVD/ISOL
27
RSVD/ISOL
30
Field I/O 15
15
8
RTS_B*
CTS_C*
RXD+_C
29
Field I/O 16
16
33
RXD_B
GND
GND
32
RSVD/ISOL
31
RSVD/ISOL
34
Field I/O 17
17
9
DSR_B*
TXD_D
TXD-_D
33
Field I/O 18
18
34
DCD_B*
RXD_D
TXD+_D

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Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 50-pin
Ribbon I/O
Connector
Pin#
Carrier 50-pin
CHAMP I/O
Connector
Pin#
AP500
Module
Function
AP520
Module
Function
AP521
Module
Function
36
RSVD/ISOL
35
RSVD/ISOL
38
Field I/O 19
19
10
GND
RTS_D*
RXD-_D
37
Field I/O 20
20
35
GND
CTS_D*
RXD+_D
40
RSVD/ISOL
39
RSVD/ISOL
42
Field I/O 21
21
11
GND
GND
GND
41
Field I/O 22
22
36
GND
TXD_E
TXD-_E
44
RSVD/ISOL
43
RSVD/ISOL
46
Field I/O 23
23
12
GND
RXD_E
TXD+_E
45
Field I/O 24
24
37
GND
RTS_E*
RXD-_E
48
RSVD/ISOL
47
RSVD/ISOL
50
Field I/O 25
25
13
GND
CTS_E*
RXD+_E
49
Field I/O 26
26
38
GND
GND
GND
52
RSVD/ISOL
51
RSVD/ISOL
54
Field I/O 27
27
14
RI_C*
TXD_F
TXD-_F
53
Field I/O 28
28
39
DTR_C*
RXD_F
TXD+_F
56
RSVD/ISOL
55
RSVD/ISOL
58
Field I/O 29
29
15
CTS_C*
RTS_F*
RXD-_F
57
Field I/O 30
30
40
TXD_C
CTS_F*
RXD+_F
60
RSVD/ISOL
59
RSVD/ISOL
62
Field I/O 31
31
16
RTS_C*
GND
GND
61
Field I/O 32
32
41
RXD_C
TXD_G
TXD-_G
64
RSVD/ISOL
63
RSVD/ISOL
66
Field I/O 33
33
17
DSR_C*
RXD_G
TXD+_G
65
Field I/O 34
34
42
DCD_C*
RTS_G*
RXD-_G
68
RSVD/ISOL
67
RSVD/ISOL
70
Field I/O 35
35
18
GND
CTS_G*
RXD+_G

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Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 50-pin
Ribbon I/O
Connector
Pin#
Carrier 50-pin
CHAMP I/O
Connector
Pin#
AP500
Module
Function
AP520
Module
Function
AP521
Module
Function
69
Field I/O 36
36
43
RI_D*
GND
GND
72
RSVD/ISOL
71
RSVD/ISOL
74
Field I/O 37
37
19
DTR_D*
TXD_H
TXD-_H
73
Field I/O 38
38
44
CTS_D*
RXD_H
TXD+_H
76
RSVD/ISOL
75
RSVD/ISOL
78
Field I/O 39
39
20
TXD_D
RTS_H*
RXD-_H
77
Field I/O 40
40
45
RTS_D*
CTS_H*
RXD+_H
80
RSVD/ISOL
79
RSVD/ISOL
82
Field I/O 41
41
21
RXD_D
GND
GND
81
Field I/O 42
42
46
DSR_D*
GND
No Connect
84
RSVD/ISOL
83
RSVD/ISOL
86
Field I/O 43
43
22
DCD_D*
GND
No Connect
85
Field I/O 44
44
47
GND
GND
No Connect
88
RSVD/ISOL
87
RSVD/ISOL
90
Field I/O 45
45
23
GND
GND
No Connect
89
Field I/O 46
46
48
GND
GND
No Connect
92
RSVD/ISOL
91
RSVD/ISOL
94
Field I/O 47
47
24
GND
GND
No Connect
93
Field I/O 48
48
49
GND
GND
No Connect
96
RSVD/ISOL
95
RSVD/ISOL
98
Field I/O 49
49
25
GND
GND
No Connect
97
Field I/O 50
50
50
GND
GND
No Connect
100
RSVD/ISOL
99
RSVD/ISOL
Note: An Asterisk (*) is used to indicate an active-low signal.
Table 2.2 Field I/O 68 PinConnector Assignments

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 14 - http://www.acromag.com
- 14 -
www.acromag.com
Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 68-pin CHAMP I/O
Connector Pin#
AP500
Module
Function
AP520
Module
Function
AP521
Module
Function
2
Field I/O 1
1
GND
GND
GND
1
Field I/O 2
35
RI_A*
TXD_A
TXD-_A
4
RSVD/ISOL
3
RSVD/ISOL
6
Field I/O 3
2
DTR_A*
RXD_A
TXD+_A
5
Field I/O 4
36
CTS_A*
RTS_A*
RXD-_A
8
RSVD/ISOL
7
RSVD/ISOL
10
Field I/O 5
3
TXD_A
CTS_A*
RXD+_A
9
Field I/O 6
37
28
RTS_A*
GND
GND
12
RSVD/ISOL
11
RSVD/ISOL
14
Field I/O 7
4
RXD_A
TXD_B
TXD-_B
13
Field I/O 8
38
DSR_A*
RXD_B
TXD+_B
16
RSVD/ISOL
15
RSVD/ISOL
18
Field I/O 9
5
DCD_A*
RTS_B*
RXD-_B
17
Field I/O 10
39
GND
CTS_B*
RXD+_B
20
RSVD/ISOL
19
RSVD/ISOL
22
Field I/O 11
6
RI_B*
GND
GND
21
Field I/O 12
40
DTR_B*
TXD_C
TXD-_C
24
RSVD/ISOL
23
RSVD/ISOL
26
Field I/O 13
7
CTS_B*
RXD_C
TXD+_C
25
Field I/O 14
41
TXD_B
RTS_C*
RXD-_C
28
RSVD/ISOL
27
RSVD/ISOL
30
Field I/O 15
8
RTS_B*
CTS_C*
RXD+_C
29
Field I/O 16
42
RXD_B
GND
GND
32
RSVD/ISOL
31
RSVD/ISOL
34
Field I/O 17
9
DSR_B*
TXD_D
TXD-_D
33
Field I/O 18
43
DCD_B*
RXD_D
TXD+_D
36
RSVD/ISOL

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 15 - http://www.acromag.com
- 15 -
www.acromag.com
Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 68-pin CHAMP I/O
Connector Pin#
AP500
Module
Function
AP520
Module
Function
AP521
Module
Function
35
RSVD/ISOL
38
Field I/O 19
10
GND
RTS_D*
RXD-_D
37
Field I/O 20
44
GND
CTS_D*
RXD+_D
40
RSVD/ISOL
39
RSVD/ISOL
42
Field I/O 21
11
GND
GND
GND
41
Field I/O 22
45
GND
TXD_E
TXD-_E
44
RSVD/ISOL
43
RSVD/ISOL
46
Field I/O 23
12
GND
RXD_E
TXD+_E
45
Field I/O 24
46
GND
RTS_E*
RXD-_E
48
RSVD/ISOL
47
RSVD/ISOL
50
Field I/O 25
13
GND
CTS_E*
RXD+_E
49
Field I/O 26
47
GND
GND
GND
52
RSVD/ISOL
51
RSVD/ISOL
54
Field I/O 27
14
RI_C*
TXD_F
TXD-_F
53
Field I/O 28
48
DTR_C*
RXD_F
TXD+_F
56
RSVD/ISOL
55
RSVD/ISOL
58
Field I/O 29
15
CTS_C*
RTS_F*
RXD-_F
57
Field I/O 30
49
TXD_C
CTS_F*
RXD+_F
60
RSVD/ISOL
59
RSVD/ISOL
62
Field I/O 31
16
RTS_C*
GND
GND
61
Field I/O 32
50
RXD_C
TXD_G
TXD-_G
64
RSVD/ISOL
63
RSVD/ISOL
66
Field I/O 33
17
DSR_C*
RXD_G
TXD+_G
65
Field I/O 34
51
DCD_C*
RTS_G*
RXD-_G
68
RSVD/ISOL
67
RSVD/ISOL
70
Field I/O 35
18
GND
CTS_G*
RXD+_G
69
Field I/O 36
52
RI_D*
GND
GND

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 16 - http://www.acromag.com
- 16 -
www.acromag.com
Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 68-pin CHAMP I/O
Connector Pin#
AP500
Module
Function
AP520
Module
Function
AP521
Module
Function
72
RSVD/ISOL
71
RSVD/ISOL
74
Field I/O 37
19
DTR_D*
TXD_H
TXD-_H
73
Field I/O 38
53
CTS_D*
RXD_H
TXD+_H
76
RSVD/ISOL
75
RSVD/ISOL
78
Field I/O 39
20
TXD_D
RTS_H*
RXD-_H
77
Field I/O 40
54
RTS_D*
CTS_H*
RXD+_H
80
RSVD/ISOL
79
RSVD/ISOL
82
Field I/O 41
21
RXD_D
GND
GND
81
Field I/O 42
55
DSR_D*
GND
No Connect
84
RSVD/ISOL
83
RSVD/ISOL
86
Field I/O 43
22
DCD_D*
GND
No Connect
85
Field I/O 44
56
GND
GND
No Connect
88
RSVD/ISOL
87
RSVD/ISOL
90
Field I/O 45
23
GND
GND
No Connect
89
Field I/O 46
57
GND
GND
No Connect
92
RSVD/ISOL
91
RSVD/ISOL
94
Field I/O 47
24
GND
GND
No Connect
93
Field I/O 48
58
GND
GND
No Connect
96
RSVD/ISOL
95
RSVD/ISOL
98
Field I/O 49
25
GND
GND
No Connect
97
Field I/O 50
59
GND
GND
No Connect
100
RSVD/ISOL
99
RSVD/ISOL
Note: An Asterisk (*) is used to indicate an active-low signal.

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 17 - http://www.acromag.com
- 17 -
www.acromag.com
2.5 RS-422/485 Termination (AP521 Only)
The standard AP521 modules have 120ohm termination resistors installed
on both line drivers and receivers, as well as 560ohm biasing resistors
installed on the line drivers. For modules without termination please consult
the factory.
2.6Noise and Grounding Considerations
The board is non-isolated, since there is electrical continuity between the
logic and field I/O grounds. As such, the field I/O connections are not
isolated from the system. Care should be taken in designing installations
without isolation to avoid noise pickup and ground loops caused by multiple
ground connections.
2.7Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector on
the carrier board. The pin assignments of this connector are standard for all
AP modules according to the PCI Express MINI Card Electromechanical
Specification, REV 1.2 (with exceptions shown in Table 2.2 and noted
below).
Threaded metric M2.5 screws and spacers are supplied with the AP module
to provide additional stability for harsh environments (see Drawing XXX for
assembly details).

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 18 - http://www.acromag.com
- 18 -
www.acromag.com
Table 2.3: Logic Interface Connections
Pin #
Name
Pin #
Name
51
+5V3
52
+3.3V4
49
N.C. (+12V)3
50
GND
47
N.C. (-12V)3
48
+1.5V
45
Present3
46
N.C. (LED_WPAN#)1
43
GND
44
N.C. (LED_WLAN#)1
41
+3.3V4
42
N.C. (LED_WWAN#)1
39
+3.3V4
40
GND
37
GND
38
N.C. (USB_D+)1
35
GND
36
N.C. (USB_D-)1
33
PETp0
34
GND
31
PETn0
32
SMB_DATA5
29
GND
30
SMB_CLK5
27
GND
28
N.C. (+1.5V)
25
PERp0
26
GND
23
PERn0
24
+3.3V4
21
GND
22
PERST#
19
TDI (UIM_C4)1,6
20
N.C. (W_DISABLE#)1
17
TDO (UIM_C8)1,6
18
GND
15
GND
16
N.C. (UIM_VPP)2
13
RECLK+
14
N.C. (UIM_RESET)2
11
REFCLK-
12
N.C. (UIM_CLK)2
9
GND
10
N.C. (UIM_DATA)2
7
N.C. (CLKREQ#)
8
N.C. (UIM_PWR)2
5
N.C. (TCK) [COEX2]1
6
N.C. (+1.5V)
3
N.C. (TMS) [COEX1]1
4
GND
1
N.C. (WAKE#)1
2
+3.3V4
Note 1: The following mini-PCIe signals are not supported: USB_D+, USB_D-, WAKE#, LED_WPAN#, LED_WLAN#, LED_WWAN#,
W_DISABLE#, COEX1, COEX2, UIM_C4, UIM_C8.
Note 2: UIM_PWR, UIM_RESET, UIM_CLK, UIM_VPP, UIM_DATA –SIM card for cell signals may be available on some AcroPack
carriers. See carrier documentation for more information.
Note 3: +5, +12, and -12 Volt power supplies have been assigned to pins that are reserved in the mini-PCIe specification. Use of
fuses on these power supplies, along with new Present signal on pin 45, to allow support of mini-PCIe cards from other
vendors that cannot tolerate power applied to these reserved pins. The Present signal must be grounded on the AP
modules. The +12V, -12V, and +5V voltages are needed to power the proposed Analog AcroPack modules.
Note 4: All +3.3Vaux power pins are changed to system +3.3V power.
Note 5: The SM bus signals SMB_CLK and SMB_DATA will be used to clock a carrier location serial stream from the carrier, however
this is not supported on the AP500/520/521 modules.
Note 6: TDI is tied to TDO on the AP500/520/521 modules as they do not use JTAG.

AP500/AP520/AP521 ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 19 - http://www.acromag.com
- 19 -
www.acromag.com
3.0 PROGRAMMING INFORMATION
This section provides an overview of the AP5XX module's registers as well as
specific information necessary to identify the model and its
geographical/carrier location information. Once the driver is loaded the
modules will be identified by the operating system as a standard serial port
so low-level programming is not required for normal operation in a
supported operating system.
More detailed register information can be found in Section 1.0 of the
Exar17v35x UART datasheets, referenced in Section 1.6.
For information on software available for use with the AP5XX modules, see
Section 1.5.
3.1 PCI Configuration Registers
The PCIe bus is defined to address three distinct address spaces: I/O,
memory, and configuration space. The AcroPack module can be accessed
via the PCIe bus memory space and configuration spaces only.
The AcroPack configuration registers are initialized by system software at
power-up to configure the card. The AcroPack module is a Plug-and-Play
PCIe card. As a Plug-and-Play card the board’s base address and system
interrupt request are not selected via jumpers but are assigned by system
software upon power-up via the configuration registers. A PCIe bus
configuration access is used to access the AcroPack’s configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCIe bus to determine what PCIe devices
are present. The software also determines the configuration requirements
of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory base address.
Since this board is not fixed in address space, its device driver must use the
mapping information stored in the board’s Configuration Space registers to
determine where the board is mapped in memory space.
The configuration registers are also used to indicate that the board requires
an interrupt request. The system software then programs the configuration
registers with the interrupt request for the board.
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers shown in the following table to facilitate