Acromag AcroPack AP48 Series User manual

Series AP48x AcroPack
Counter Timer Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: [phone]
Email: [email protected]
Copyright 2016, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501060G

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Table of Contents
1.0 GENERAL INFORMATION..........................................................................................5
1.1 Intended Audience .......................................................................................................5
1.2 Preface.........................................................................................................................5
1.2.1 Trademark, Trade Name and Copyright Information .................................................................. 5
1.2.2 Class A Product Warning............................................................................................................. 5
1.2.3 Environmental Protection Statement ......................................................................................... 5
1.3 AcroPack Information –All Models...............................................................................5
1.3.1 Ordering Information ................................................................................................................. 6
1.3.2 Key Features............................................................................................................................... 6
1.3.3 Key Features PCIe Interface........................................................................................................ 8
1.4 Signal Interface Products ..............................................................................................8
1.5 Software Support .........................................................................................................8
Windows............................................................................................................................................ 9
VxWorks............................................................................................................................................ 9
Linux.................................................................................................................................................. 9
1.6 References ...................................................................................................................9
2.0 PREPARATION FOR USE........................................................................................... 10
2.1 Unpacking and Inspecting...........................................................................................10
2.2 Installation Considerations .........................................................................................11
2.3 Board Configuration ...................................................................................................11
2.4 Field I/O Connector ....................................................................................................11
Table 2.1 AP482 Field I/O Connector Pin Assignments.........................................................................12
Table 2.2 AP483 Field I/O Connector Pin Assignments .........................................................................14
Table 2.3 AP484 Field I/O Connector Pin Assignments .........................................................................17
NOTE 1: VPX4500-CC-LF IS AN EXAMPLE OF A CARRIER THAT USES THE
RIBBON CABLE CONNECTOR SEE IMAGE OF CARRIER. .......................................... 19

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NOTE 2: APCE7020E-LF IS AN EXAMPLE OF A CARRIER THAT USES THE
CHAMP CONNECTOR SEE IMAGE OF CARRIER........................................................... 20
2.5 Noise and Grounding Considerations ..........................................................................20
2.6 Logic Interface Connector ...........................................................................................20
Table 2.4: Logic Interface Connections........................................................................................ 20
3.0 PROGRAMMING INFORMATION........................................................................... 22
CONFIGURATION REGISTERS................................................................................................................22
Table 3.1 Configuration Registers................................................................................................ 23
Table 3.2: AP482 Memory Map................................................................................................... 23
Global Interrupt Enable Status Register (Read/Write) - (BAR0 + 0x0000 0000) ....................................27
Table 3.3 Global Interrupt Register ............................................................................................ 27
Module Location In System Register (Read Only) - (BAR0 + 0x0000 0004)............................................28
Table 3.4 Location Register........................................................................................................ 28
Counters Interrupt Status/Clear Register (Read/Write) - (BAR0 + 0x0000 0008) ..................................28
Table 3.5 Counter Interrupt Status Clear Register..................................................................... 29
Counter Interrupt Enable/Disable Register (Read/Write) - (BAR0 + 0x0000 000C) ...............................29
Table 3.6 Counter Interrupt Enable Register............................................................................. 29
Counter Trigger Register (Write) - (BAR0 + 0x0000 0010).....................................................................30
Table 3.7 Counter Trigger Register ............................................................................................ 30
Counter Stop Register (Write) - (BAR0 + 0x0000 0014).........................................................................31
Table 3.8 Counter Stop Register ................................................................................................ 31
Load Read Back Register (Write) - (BAR0 + 0x0000 0018).....................................................................31
Table 3.9 Load Read Back Register ............................................................................................ 32
Toggle Counter Constants Register (Read/Write) - (BAR0 + 0x0000 001C) ...........................................32
Table 3.10 Toggle Counter Constant Register ........................................................................... 32
Counter Control Register (Read/Write)................................................................................................33
Quadrature Position Measurement .....................................................................................................34
Figure 3.1 Quadrature Cycles with X4 Encoding........................................................................ 34
Table 3.11 Counter Control Register (Quadrature Position Measurement).............................. 35
Pulse Width Modulation ......................................................................................................................37
Table 3.12 Counter Control Register (Pulse Width Modulation)............................................... 38
Watchdog Timer Operation .................................................................................................................39
Table 3.13 Counter Control Register (Watchdog Timer) ........................................................... 40
Event Counting Operation....................................................................................................................41
Table 3.14 Counter Control Register (Event Counting) ............................................................. 42
Frequency Measurement Operation ....................................................................................................43
Table 3.15 Counter Control Register (Frequency Measurement) ............................................. 44
Input Pulse Width Measurement .........................................................................................................45
Table 3.16 Counter Control Register (Pulse Width Measurement)........................................... 46
Input Period Measurement..................................................................................................................47

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Table 3.17 Counter Control Register (Period Measurement).................................................... 48
One-Shot Pulse Mode ..........................................................................................................................49
Table 3.18 Counter Control Register (One-Shot Mode) ............................................................ 50
Counter Interrupt Information Register (Read Only)............................................................................51
Table 3.19 Counter Interrupt Information Register................................................................... 51
Counter Read Back Register (Read Only)..............................................................................................51
Counter Constant A Register (Read/Write) ..........................................................................................52
Counter Constant A Register 2 (Read/Write) .......................................................................................52
Counter Constant B Register (Read/Write) ..........................................................................................52
Counter Constant B Register 2 (Read/Write)........................................................................................52
Digital Input Register (Read Only) - (BAR0 + 0x0000 0160)...................................................................53
Table 3.20 Digital Input Register................................................................................................ 53
Digital Output Register (Read/Write) - (BAR0 + 0x0000 0164)..............................................................53
Table 3.21 Digital Output Register............................................................................................. 53
XADC Status/Control Register (Read/Write) - (BAR0 + 168H)...............................................................54
XADC Address Register (Write Only) - (BAR0 + 16CH)...........................................................................54
Table 3.22: System Monitor Register Map .................................................................................. 54
Table 3.23 FPGA Voltage and Temperature Range ..................................................................... 55
Firmware Revision Register (Read Only) - (BAR0 + 0x0000 0200) .........................................................55
4.0 THEORY OF OPERATION.......................................................................................... 56
4.1 Counter Timer ............................................................................................................56
4.2 Digital Input/Output...................................................................................................56
4.3 Mini PCIe Interface.....................................................................................................56
4.4 PCIe Interface Logic ....................................................................................................56
5.0 SERVICE AND REPAIR............................................................................................... 57
5.1 Service and Repair Assistance.....................................................................................57
5.2 Preliminary Service Procedure ....................................................................................57
5.3 Where to Get Help......................................................................................................57
6.0 SPECIFICATIONS......................................................................................................... 58
6.1 Physical......................................................................................................................58
6.2 Power Requirements..................................................................................................58

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6.3 Environmental Considerations....................................................................................58
6.3.1 Operating Temperature.............................................................................................................58
6.3.2 Other Environmental Requirements..........................................................................................59
6.3.2.1 Relative Humidity .......................................................................................................... 59
6.3.2.2 Isolation ......................................................................................................................... 59
6.3.3 Vibration and Shock Standards..................................................................................................59
6.3.4 EMC Directives ..........................................................................................................................59
6.4 Reliability Prediction ....................................................................................................60
AP482E-LF............................................................................................................................................60
AP483E-LF............................................................................................................................................60
AP484E-LF............................................................................................................................................60
6.5 Counter/Timers............................................................................................................60
6.6 PCIe Bus Specifications ...............................................................................................61
Figure 1 AP482 Block Diagram .............................................................................................................63
Figure 2 AP483 Block Diagram .............................................................................................................63
Figure 3 AP484 Block Diagram .............................................................................................................64
APPENDIX A .......................................................................................................................... 65
AP-CC-01 Heatsink Kit Installation......................................................................................65
CERTIFICATE OF VOLATILITY ........................................................................................ 68
REVISION HISTORY ............................................................................................................ 69

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1.0 GENERAL INFORMATION
1.1 Intended Audience
This users’ manual was written for technically qualified personnel who will
be working with I/O devices using the AcroPack module. It is not intended
for a general, non-technical audience that is unfamiliar with AcroPack
devices and their application.
1.2 Preface
The information contained in this manual is subject to change without
notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.
Acromag makes no warranty of any kind with regard to this material,
including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. Further, Acromag assumes no responsibility
for any errors that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual. No part
of this manual may be copied or reproduced in any form, without the prior
written consent of Acromag,
1.2.1 Trademark, Trade Name and Copyright Information
© 2016 by Acromag Incorporated.
All rights reserved. Acromag and Xembedded are registered trademarks of
Acromag Incorporated. All other trademarks, registered trademarks, trade
names, and service marks are the property of their respective owners.
1.2.2 Class A Product Warning
This is a Class A product. In a domestic environment this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
1.2.3 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final
disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.
1.3 AcroPack Information –All Models
The AcroPack IO module are based on the PCI Express Mini Card
Electromechanical specification and are 70mm in length with an add 100 pin
field I/O connector.

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The AcroPack is 19.05mm longer than the full length mini PCIe card at
50.95mm. It has the same mPCIe board width of 30mm and uses the same
mPCIe standard board hold down standoff and screw keep out areas.
The AP482 board has ten 32-bit multifunction counter/timers. In addition,
two digital input channels and six digital output channels are provided.
The AP483 board has five TTL and three RS422/RS485 32-bit multifunction
counter/timers. In addition, one digital input channel and three digital
output channels are provided.
The AP484 board has six RS422/RS485 32-bit multifunction counter/timers.
The AP48X modules utilizes state of the art Surface-Mounted Technology
(SMT) to achieve its wide functionality and is an ideal choice for a wide
range of industrial I/O applications that require a high-density, highly
reliable, high-performance interface at a low cost.
The counters can be configured for quadrature position measurement, pulse
width modulated output, watchdog timer, event counter, frequency
measurement, pulse width measurement, period measurement, or one shot
pulse output.
1.3.1 Ordering Information
The AcroPack ordering options are given in the following table.
Model Number
Temperature
I/O Type
Counters
AP482E-LF1,2
-40oC to 85oC
TTL
10
AP483E-LF1,2
-40oC to 85oC
TTL
RS422/RS485
5
3
AP484E-LF1,2
-40oC to 85oC
RS422/RS485
6
Note 1: Operating temperature range for models:-40oCto 85oC.
Applications requiring operating temperatures of 70oCto 85oC
will require purchase of AcroPack Heatsink Accessory AP-CC-01.
AP-CC-01
AcroPack Heatsink Conduction
Cool Kit
See Appendix A for installation instructions.
1.3.2 Key Features
•TTL I/O –482 Counter/Timer I/O is available as TTL only. Mixed TTL
and RS422/RS485 I/O options are available on the 483 models.
Only RS422/RS485 I/O is available on the 484 models.

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•Quadrature Position Measurement –Three input signals can be
used to determine bi-direction motion. The sequence of logic high
pulses for two input signals, A and B, indicate direction and a third
signal (index) is used to initialize the counter. X1, X2, and X4
decoding is also implemented. X1 decoding executes one count per
duty cycle of the A and B signals, while X2, and X4 execute two and
four counts per duty cycle respectively.
•Pulse Width Modulation –Each counter can be programmed for
pulse width modulation. The duration of the logic high and low
levels of the output signal can be independently controlled. An
external gate signal can also be used to start/stop generation of the
output signal.
•Watchdog Timer –Each counter can be configured as a countdown
timer for implementation as a watchdog timer. A gate-off signal is
available for use to stop the count down operation. Interrupt
generation upon a countdown to zero condition is available.
•Event Counter –Each counter can be configured to count input
pulses or events. A gate-off signal is provided to control count-up
or count down with each event. Interrupt generation upon
programmed count condition is available.
•Frequency Measurement –Each counter can be configured to
count how many active edges are received during a period defined
by an external count enable signal. An interrupt can be generated
upon measurement complete.
•Pulse-Width or Period Measurement –Each counter can be
configured to measure pulse-width or waveform period. In
addition, an interrupt can be generated upon measurement
complete.
•One-Shot and Repetitive One-Shot –A one-shot pulse waveform
may also be generated by each counter. The duration of the pulse
and the delay until the pulse goes active is user programmable. A
repetitive one-shot can be initiated with repetitive trigger pulses.
•Programmable Interface Polarity –The polarities of the counter’s
external trigger, input, and output pins are programmable for active
high or low operation. These counter control signals are available
through the board’s field connector.
•Internal or External Triggering –A software or hardware trigger is
selectable to initiate quadrature position measurement, pulse width
modulation, watchdog countdown, event counting, frequency
measurement, pulse-width measurement, period measurement, or
one shot.

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•TTL Compatible Thresholds –Input and output signal thresholds are
at TTL levels.
1.3.3 Key Features PCIe Interface
•PCIe Bus –The AP module includes a PCI Express Generation 1
interface operating at a bus speed of 2.5 Gbps with one lane in each
direction.
•Compatibility –PCI Express Base Specification v2.1 compliant PCI
Express Endpoint.
1.4Signal Interface Products
This AcroPack Module will mate directly to all Acromag AP carriers. Once
connected, the module is accessed via a front panel connector.
The cables and termination panels are also available. For optimum
performance with the AP440 digital I/O module, use of the shortest possible
length of shielded I/O cable is recommended.
1.5Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows,
and VxWorks

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Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. This software (model APSW-
API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that
are compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented
as a library of “C” functions which link with existing user code to make
possible simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The
software is implemented as a library of “C” functions which link with existing
user code to make possible simple control of all Acromag AcroPack modules.
1.6 References
The following resources regarding AcroPack modules are available for
download on Acromag’s website or by contacting your sales representative.
•PCI Express MINI Card Electromechanical Specification, REV 1.2
https://www.pcisig.com

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2.0 PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications
of power, wiring, component, sensor, or software failures in designing any
type of control or monitoring system. This is especially important where
personal injury or the loss of economic property or human life is possible. It
is important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not
ship or store this product near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its
original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the Acromag Limited Warranty.
2.1 Unpacking and Inspecting
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.
The board utilizes static-sensitive components and should only be handled at
a static-safe workstation.

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2.2 Installation Considerations
IMPORTANT: Adequate air
circulation must be provided to
prevent a temperature rise
above the maximum operating
temperature.
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, adequate air circulation must be provided to
prevent a temperature rise above the maximum operating temperature and
to prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
2.3 Board Configuration
Power should be removed from the board when installing AP modules,
cables, termination panels, and field wiring. Model AP482/3/4 counter
timer boards have no hardware jumpers or switches to configure.
2.4Field I/O Connector
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack card as board to board interconnect.
This connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec
connector on the carrier. The stack height is 4.5mm.
Threaded metric M2.5 screws and spacers are supplied with the carrier to
provide additional stability for harsh environments.
Pin assignments are unique to each AP model. Tables 2.1 to 2.3 lists signal
pin assignments for the module field I/O connector. Every other pin of the
100 pin connector is left unconnected in order to meet the minimum
creepage distance required for 60 Volt isolation.

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Table 2.1 AP482 Field I/O Connector Pin Assignments
68 Pin Champ
Carrier Connector
50 Pin Champ
Carrier Connector2
Ribbon Carrier
Connector1
Module P2 Pin
Number
Field I/O Signal
1
1
1
2
In0_A
35
26
2
1
In1_A
4
Reserved/isolation
3
Reserved/isolation
2
2
3
6
In2_A
36
27
4
5
In3_A
8
Reserved/isolation
7
Reserved/isolation
3
3
5
10
In4_A
37
28
6
9
In5_A
12
Reserved/isolation
11
Reserved/isolation
4
4
7
14
In6_A
38
29
8
13
In7_A
16
Reserved/isolation
15
Reserved/isolation
5
5
9
18
In8_A
39
30
10
17
In9_A
20
Reserved/isolation
19
Reserved/isolation
6
6
11
22
In0_B
40
31
12
21
In1_B
24
Reserved/isolation
23
Reserved/isolation
7
7
13
26
In2_B
41
32
14
25
In3_B
28
Reserved/isolation
27
Reserved/isolation
8
8
15
30
In4_B
42
33
16
29
In5_B
32
Reserved/isolation
31
Reserved/isolation
9
9
17
34
In6_B
43
34
18
33
In7_B
36
Reserved/isolation
35
Reserved/isolation
10
10
19
38
In8_B
44
35
20
37
In9_B
40
Reserved/isolation

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39
Reserved/isolation
11
11
21
42
In0_C
45
36
22
41
In1_C
44
Reserved/isolation
43
Reserved/isolation
12
12
23
46
In2_C
46
37
24
45
In3_C
48
Reserved/isolation
47
Reserved/isolation
13
13
25
50
In4_C
47
38
26
49
In5_C
52
Reserved/isolation
51
Reserved/isolation
14
14
27
54
In6_C
48
39
28
53
In7_C
56
Reserved/isolation
55
Reserved/isolation
15
15
29
58
In8_C
49
40
30
57
In9_C
60
Reserved/isolation
59
Reserved/isolation
16
16
31
62
Din0
50
41
32
61
Din1
64
Reserved/isolation
63
Reserved/isolation
17
17
33
66
Out0
51
42
34
65
Out1
68
Reserved/isolation
67
Reserved/isolation
18
18
35
70
Out2
52
43
36
69
Out3
72
Reserved/isolation
71
Reserved/isolation
19
19
37
74
Out4
53
44
38
73
Out5
76
Reserved/isolation
75
Reserved/isolation
20
20
39
78
Out6
54
45
40
77
Out7
80
Reserved/isolation
79
Reserved/isolation
21
21
41
82
Out8
55
46
42
81
Out9
84
Reserved/isolation

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83
Reserved/isolation
22
22
43
86
DOut0
56
47
44
85
DOut1
88
Reserved/isolation
87
Reserved/isolation
23
23
45
90
DOut2
57
48
46
89
DOut3
92
Reserved/isolation
91
Reserved/isolation
24
24
47
94
DOut4
58
49
48
93
DOut5
96
Reserved/isolation
95
Reserved/isolation
25
25
49
98
External Clock
Enable
59
50
50
97
GND
100
Reserved/isolation
99
Reserved/isolation
Table 2.2 AP483 Field I/O Connector Pin Assignments
68 Pin Champ
Carrier Connector
50 Pin Champ
Carrier Connector2
Ribbon Carrier
Connector1
Module P2 Pin
Number
Field I/O Signal
1
1
1
2
In0_A
35
26
2
1
In1_A
4
Reserved/isolation
3
Reserved/isolation
2
2
3
6
In2_A
36
27
4
5
In3_A
8
Reserved/isolation
7
Reserved/isolation
3
3
5
10
In4_A
37
28
6
9
In0_B
12
Reserved/isolation
11
Reserved/isolation
4
4
7
14
In1_B
38
29
8
13
In2_B
16
Reserved/isolation
15
Reserved/isolation
5
5
9
18
In3_B
39
30
10
17
In4_B
20
Reserved/isolation
19
Reserved/isolation

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6
6
11
22
In0_C
40
31
12
21
In1_C
24
Reserved/isolation
23
Reserved/isolation
7
7
13
26
In2_C
41
32
14
25
In3_C
28
Reserved/isolation
27
Reserved/isolation
8
8
15
30
In4_C
42
33
16
29
Din 0
32
Reserved/isolation
31
Reserved/isolation
9
9
17
34
Out0
43
34
18
33
Out1
36
Reserved/isolation
35
Reserved/isolation
10
10
19
38
Out2
44
35
20
37
Out3
40
Reserved/isolation
39
Reserved/isolation
11
11
21
42
Out4
45
36
22
41
DOut0
44
Reserved/isolation
43
Reserved/isolation
12
12
23
46
DOut1
46
37
24
45
DOut2
48
Reserved/isolation
47
Reserved/isolation
13
13
25
50
In5_A+
47
38
26
49
In5_A-
52
Reserved/isolation
51
Reserved/isolation
14
14
27
54
In5_B+
48
39
28
53
In5_B-
56
Reserved/isolation
55
Reserved/isolation
15
15
29
58
In5_C+
49
40
30
57
In5_C-
60
Reserved/isolation
59
Reserved/isolation
16
16
31
62
Out5+
50
41
32
61
Out5-
64
Reserved/isolation
63
Reserved/isolation

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17
17
33
66
In6_A+
51
42
34
65
In6_A-
68
Reserved/isolation
67
Reserved/isolation
18
18
35
70
In6_B+
52
43
36
69
In6_B-
72
Reserved/isolation
71
Reserved/isolation
19
19
37
74
In6_C+
53
44
38
73
In6_C-
76
Reserved/isolation
75
Reserved/isolation
20
20
39
78
Out6+
54
45
40
77
Out6-
80
Reserved/isolation
79
Reserved/isolation
21
21
41
82
In7_A+
55
46
42
81
In7_A-
84
Reserved/isolation
83
Reserved/isolation
22
22
43
86
In7_B+
56
47
44
85
In7_B-
88
Reserved/isolation
87
Reserved/isolation
23
23
45
90
In7_C+
57
48
46
89
In7_C-
92
Reserved/isolation
91
Reserved/isolation
24
24
47
94
Out7+
58
49
48
93
Out7-
96
Reserved/isolation
95
Reserved/isolation
25
25
49
98
External Clock
Enable
59
50
50
97
GND
100
Reserved/isolation
99
Reserved/isolation

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Table 2.3 AP484 Field I/O Connector Pin Assignments
68 Pin Champ
Carrier Connector
50 Pin Champ
Carrier Connector2
Ribbon Carrier
Connector1
Module P2 Pin
Number
Field I/O Signal
1
1
1
2
In0_A+
35
26
2
1
In0_A-
4
Reserved/isolation
3
Reserved/isolation
2
2
3
6
In0_B+
36
27
4
5
In0_B-
8
Reserved/isolation
7
Reserved/isolation
3
3
5
10
In0_C+
37
28
6
9
In0_C-
12
Reserved/isolation
11
Reserved/isolation
4
4
7
14
Out0+
38
29
8
13
Out0-
16
Reserved/isolation
15
Reserved/isolation
5
5
9
18
In1_A+
39
30
10
17
In1_A-
20
Reserved/isolation
19
Reserved/isolation
6
6
11
22
In1_B+
40
31
12
21
In1_B-
24
Reserved/isolation
23
Reserved/isolation
7
7
13
26
In1_C+
41
32
14
25
In1_C-
28
Reserved/isolation
27
Reserved/isolation
8
8
15
30
Out1+
42
33
16
29
Out1-
32
Reserved/isolation
31
Reserved/isolation
9
9
17
34
In2_A+
43
34
18
33
In2_A-
36
Reserved/isolation
35
Reserved/isolation
10
10
19
38
In2_B+
44
35
20
37
In2_B-
40
Reserved/isolation

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39
Reserved/isolation
11
11
21
42
In2_C+
45
36
22
41
In2_C-
44
Reserved/isolation
43
Reserved/isolation
12
12
23
46
Out2+
46
37
24
45
Out2-
48
Reserved/isolation
47
Reserved/isolation
13
13
25
50
In3_A+
47
38
26
49
In3_A-
52
Reserved/isolation
51
Reserved/isolation
14
14
27
54
In3_B+
48
39
28
53
In3_B-
56
Reserved/isolation
55
Reserved/isolation
15
15
29
58
In3_C+
49
40
30
57
In3_C-
60
Reserved/isolation
59
Reserved/isolation
16
16
31
62
Out3+
50
41
32
61
Out3-
64
Reserved/isolation
63
Reserved/isolation
17
17
33
66
In4_A+
51
42
34
65
In4_A-
68
Reserved/isolation
67
Reserved/isolation
18
18
35
70
In4_B+
52
43
36
69
In4_B-
72
Reserved/isolation
71
Reserved/isolation
19
19
37
74
In4_C+
53
44
38
73
In4_C-
76
Reserved/isolation
75
Reserved/isolation
20
20
39
78
Out4+
54
45
40
77
Out4-
80
Reserved/isolation
79
Reserved/isolation
21
21
41
82
In5_A+
55
46
42
81
In5_A-

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84
Reserved/isolation
83
Reserved/isolation
22
22
43
86
In5_B+
56
47
44
85
In5_B-
88
Reserved/isolation
87
Reserved/isolation
23
23
45
90
In5_C+
57
48
46
89
In5_C-
92
Reserved/isolation
91
Reserved/isolation
24
24
47
94
Out5+
58
49
48
93
Out5-
96
Reserved/isolation
95
Reserved/isolation
25
25
49
98
External Clock
Enable
59
50
50
97
GND
100
Reserved/isolation
99
Reserved/isolation
Note 1: VPX4500-CC-LF is an example
of a carrier that uses the ribbon cable
connector see image of carrier.