Acromag APZU AcroPack Series User manual

Series APZU AcroPack
Zynq Ultrascale+ Based Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: [phone]
Fax: [phone]
Copyright 2020, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501150A

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Table of Contents
1.0 GENERAL INFORMATION..........................................................................................4
1.1 Intended Audience .........................................................................................................4
1.2 Preface...........................................................................................................................4
1.2.1 Trademark, Trade Name and Copyright Information .................................................................4
1.2.2 Class A Product Warning...........................................................................................................4
1.2.3 Environmental Protection Statement........................................................................................4
1.3 AcroPack Information – All Models ................................................................................5
1.3.1 Ordering Information ...............................................................................................................5
1.3.2 Key Features.............................................................................................................................5
1.3.3 Key Features PCIe Interface ......................................................................................................6
Figure 1 Block Diagram Model APZU-303...........................................................................................7
Figure 2 Block Diagram Model APZU-301/304....................................................................................8
1.4 Signal Interface Products................................................................................................8
1.5 Software Support ...........................................................................................................8
Windows.........................................................................................................................................9
VxWorks..........................................................................................................................................9
Linux...............................................................................................................................................9
1.6 References .....................................................................................................................9
2.0 PREPARATION FOR USE........................................................................................... 10
2.1 Unpacking and Inspecting ............................................................................................10
2.2 Installation Considerations...........................................................................................11
2.3 Board Configuration .....................................................................................................11
Table 2.1 Boot Mode Switch Settings ................................................................................................11
2.4 Field I/O Connector ......................................................................................................12
Table 2.2 Field I/O Connector Pin Assignments.................................................................................. 12
2.5 Logic Interface Connector.............................................................................................14
Table 2.3 Logic Interface Connections.............................................................................................. 14
3.0 PROGRAMMING INFORMATION........................................................................... 16

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CONFIGURATION REGISTERS ...............................................................................................16
Table 3.1 Configuration Registers...................................................................................................... 17
Table 3.2: BAR1 Memory Map .......................................................................................................... 18
Table 3.3: BAR1 M01_AXI Memory Map............................................................................................ 18
Global Interrupt Register (Read/Write) - (BAR1 + 0x0000 0000) ..........................................19
Table 3.4 Interrupt Register.............................................................................................................19
Module Location In System Register (Read Only) - (BAR1 + 0x0000 0004)............................19
Table 3.5 Location Register ............................................................................................................. 19
Digital Input/Output Registers (Read/Write) - (BAR1 + 0x0000 0008) ..................................20
Digital Direction Control Register (Read/Write) - (BAR1 + 0x0000 000C)..............................20
Interrupt Enable Register (Read/Write) - (BAR1 + 0x0000 0010) ........................................................21
Interrupt Type (COS or H/L) Configuration Register (Read/Write) - (BAR1 + 0x0000 0014) ..21
Interrupt Polarity Registers (Read/Write) - (BAR1 + 0x0000 0018) .......................................22
Interrupt Status Register (Read/Write) - (BAR1 + 0x0000 001C)...........................................22
RS485 Data Registers (Read/Write) - (BAR1 + 0x0000 002C) ................................................22
RS485 Direction Control Register (Read/Write) - (BAR1 + 0x0000 0030) ..............................23
Firmware Revision Register (Read Only) - (BAR1 + 0x0000 0200) .........................................23
System Monitor (SYSMONE 4) ............................................................................................. 23
Table 3.6: SYSMONE4 (System Monitor) (Read Only) - Memory Map.................................................24
Table 3.7: FPGA Voltage and Temperature Range..............................................................................24
Block RAM ...........................................................................................................................24
The Effect of Reset............................................................................................................................ 24
Quad-SPI Flash.................................................................................................................................. 25
MAC Address EEPROM...................................................................................................................... 25
4.0 THEORY OF OPERATION.......................................................................................... 26
4.1 AcroPack Operation .....................................................................................................26
4.2 Digital Interface Logic................................................................................................... 26
5.0 OVERVIEW OF XILINX VIVADO AND VITIS TOOLS .......................................... 31
5.0.1 APZU Testing Hardware Requirements ................................................................................... 31
5.0.2 Vitis Integrated Design Environment and Vivado Design Suite................................................. 31

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5.1 Vivado and the Programmable Logic ............................................................................32
5.1.1 APZU Programmable Logic Block Diagram Overview ...............................................................32
5.1.2 APZU Programmable Logic Block Design Constraints ...............................................................45
5.1.3 APZU Programmable Logic Block FPGA Configuration.............................................................. 45
5.2 Vitis Integrated Design Environment (IDE)....................................................................46
5.2.1 Creating a Hardware Platform using Vitis IDE.......................................................................... 47
6.0 APZU PROCESSING SYSTEM BARE METAL SOFTWARE ................................. 58
6.1 PCIe Software...............................................................................................................58
6.2 Ethernet Bare Metal Software......................................................................................61
6.3 IIC Bare Metal Software ...............................................................................................62
6.4 USB Bare Metal Software .............................................................................................63
6.5 LED Bare Metal Software..............................................................................................67
7.0 SERVICE AND REPAIR ............................................................................................... 68
7.1 Service and Repair Assistance ......................................................................................68
7.2 Preliminary Service Procedure......................................................................................68
7.3 Where to Get Help ....................................................................................................... 68
8.0 SPECIFICATIONS......................................................................................................... 69
8.1 Physical ........................................................................................................................69
8.2 Power Requirements....................................................................................................69
8.3 Environmental Considerations .....................................................................................69
8.3.1 Operating Temperature ..........................................................................................................69
8.3.2. Relative Humidity.................................................................................................................. 70
8.3.3 Isolation .................................................................................................................................70
8.3.4 Vibration and Shock Standards ...............................................................................................70
8.3.5 EMC Directives .......................................................................................................................70
8.4 Reliability Prediction......................................................................................................70
Table 8.4.1 MTBF of APZU-303..........................................................................................................70
8.5 Field I/O .......................................................................................................................71

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8.6 PCIe Bus Specifications................................................................................................. 71
Table 8.6 PCIe Bus Data Rates ...........................................................................................................71
CERTIFICATE OF VOLATILITY ........................................................................................ 73
REVISION HISTORY ............................................................................................................ 74
1.0 GENERAL INFORMATION
1.1 Intended Audience
This users’ manual was written for technically qualified personnel who will
be working with I/O devices using the AcroPack module. It is not intended
for a general, non-technical audience that is unfamiliar with I/O devices and
their application.
1.2 Preface
The information contained in this manual is subject to change without
notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.
Acromag makes no warranty of any kind with regard to this material,
including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. Further, Acromag assumes no responsibility
for any errors that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual. No part
of this manual may be copied or reproduced in any form, without the prior
written consent of Acromag.
1.2.1 Trademark, Trade Name and Copyright Information
© 2020 by Acromag Incorporated.
All rights reserved. Acromag is a registered trademark of Acromag
Incorporated. All other trademarks, registered trademarks, trade names,
and service marks are the property of their respective owners.
1.2.2 Class A Product Warning
This is a Class A product. In a domestic environment this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
1.2.3 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final

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disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.
1.3 AcroPack Information – All Models
The AcroPack IO module are based on the PCI Express Mini Card
Electromechanical specification and are 70mm in length with an added 100
pin field I/O connector.
The AcroPack is 19.05mm longer than the full length mini PCIe card at
50.95mm. It has the same mPCIe board width of 30mm and uses the same
mPCIe standard board hold down standoff and screw keep out areas.
The APZU+ module is a Xilinx Zynq base module the has FPGA fabric
available for parallel computing applications. The key information resulting
from the parallel processing can then be passed to the ARM processing
system for further manipulation and processing.
The APZU+ utilizes state of the art Surface-Mounted Technology (SMT) to
achieve its wide functionality and is an ideal choice for a wide range of
industrial I/O applications that require a high-density, highly reliable, high-
performance interface at a low cost.
1.3.1 Ordering Information
The AcroPack ordering options are given in the following table.
Model Number Description Zynq I/O Bank
APZU-3011 28 TTL I/O 1.8 volt HP Bank 65
APZU-3031 20 TTL & 3 RS485/422 3.3 volt HD Bank 26
APZU-3041 14 LVDS I/O 1.8 volt HP Bank 65
Note 1: Operating temperature range for models:-40oCto 75oC.
1.3.2 Key Features
Zynq UltraScale Plus device XCZU3CG
oDual-core ARM Cortex-A53 Processing Unit
1.5GHz CPU
Single/double precision Floating Point Unit
oDual-core ARM Cortex-R5 Real-Time processor system

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600MHz CPU
Single/double precision Floating Point Unit
oProgrammable Logic resources
154,350 logic cells
70,560 LUTs
360 DSP slices
Board support package and FPGA Design Kit for Xilinx Vivado
oIP Block design
Block RAM
System Monitor
AXI interface to Digital I/O
Ethernet Gigabit Ethernet over copper wire 1000BASE-T
LPDDR4 Storage Memory Provides 2 Giga Byte (512Mbit x 32) of LPDDR4 Memory.
USB Peripheral Port USB 2.0 Transceiver
USB-UART provides a Zynq debug terminal port
Provides MicroSD socket as primary boot device.
512 Mega bit Nor Flash (alternative boot)
1.3.3 Key Features PCIe Interface
PCIe Bus – The AP module includes a PCI Express Generation 1
interface operating at a bus speed of 2.5 Gbps with one lane in each
direction.
Compatibility – PCI Express Base Specification v2.1 compliant PCI
Express Endpoint.

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Figure 1 Block Diagram Model APZU-303
Quad-SPI Flash
64MB/512Mb
LPDDR4
2 GByte
(512 x 32)
Ethernet MAC
Power Chip
MPSoC
XCZU3CG
Programmable Logic (PL)
PCIe
X1 lane
Ethernet
10/100/1000
USB 2.0
USB-UART
Boot Mode
SW2
AcroPack
I/O
50 Pin
MicroSD
(primary boot) Processing System (PS)
Bank 26
Bank 65
3 RS485 Ports
A
B
3.3V TTL Digital
I2C
R
D
20

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Figure 2 Block Diagram Model APZU-301/304
1.4 Signal Interface Products
Breakout Panel
5028-626
This AcroPack Module will mate directly to all Acromag AP carriers. Once
connected, the module is accessed via a 68 pin front panel connector.
The cables and termination panels are also available. The APZU Cable
Breakout panel (Model number 5028-626) will mate directly to all 68-pin
AcroPack Carriers. The breakout panel and short 68-pin male to male 1 foot
cable will bring an ethernet port, USB 2.0 port, UART to USB port, digital I/O
at jumper blocks, and power and reset buttons out to the field.
1.5 Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows,
and VxWorks
Quad SPI Flash
64MB/512Mb
LPDDR4
2 GByte
(512 x 32)
Ethernet MAC
Power Chip
MPSoC
XCZU3CG
Programmable Logic (PL)
PCIe
X1 lane
Ethernet
10/100/1000
USB 2.0
USB-UART
Boot Mode
SW2
AcroPack
I/O
50 Pin
MicroSD
(primary boot) Processing System (PS)
(APZU-304)
14 LVDS I/O
I2C
28
Bank 65
(APZU-301)
28 TTL I/O (1.8V)

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Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. This software (model APSW-
API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that
are compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented
as a library of “C” functions which link with existing user code to make
possible simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The
software is implemented as a library of “C” functions which link with existing
user code to make possible simple control of all Acromag AcroPack modules.
1.6 References
The following resources regarding AcroPack modules are available for
download on Acromag’s website or by contacting your sales representative.
PCI Express MINI Card Electromechanical Specification, REV 1.2
http://www.pcisig.com

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2.0 PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications
of power, wiring, component, sensor, or software failures in designing any
type of control or monitoring system. This is especially important where
personal injury or the loss of economic property or human life is possible. It
is important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not
ship or store this product near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its
original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the Acromag Limited Warranty.
2.1 Unpacking and Inspecting
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.
The board utilizes static-sensitive components and should only be handled at
a static-safe workstation.

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2.2 Installation Considerations
IMPORTANT: Adequate air
circulation must be provided to
prevent a temperature rise
above the maximum operating
temperature.
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, adequate air circulation must be provided to
prevent a temperature rise above the maximum operating temperature and
to prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
2.3 Board Configuration
Power should be removed from the board when installing AP modules,
cables, termination panels, and field wiring. Boot mode configuration is set
via SW2 switches seen below. In the image blow the switch settings are all
set OFF. ON = logic low, OFF = logic high
Table 2.1 Boot Mode Switch Settings
BOOT MODE SW2[4-3-2-1]
JTAG ON-ON-ON-ON
Quad-SPI Flash ON-ON-OFF-ON
MicroSD SD0 ON-ON-OFF-OFF

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2.4 Field I/O Connector
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack card as board to board interconnect.
This connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec
connector on the carrier. The stack height is 4.5mm.
Pin assignments are unique to each AP model. Table 2.2 lists signal pin
assignments for the module field I/O connector. Every other pin of the 100
pin connector is left unconnected in order to meet the minimum creepage
distance required for 60 Volt isolation.
The signals listed in Table 2.2 are available on the APZU Cable Breakout
panel Acromag part number 5028-626. For the APZU-303 these signals
include: 20 TTL, three RS485 signal pairs, UART to USB port, USB 2.0,
Ethernet via RJ-45, push button reset, and power-on push button.
Table 2.2 Field I/O Connector Pin Assignments
APZU-304(APZU-301)
14 LVDS (28 TTL)
Field I/O Signal
APZU-303
20 TTL & 3 RS485
Field I/O Signal
APZU Cable Breakout AcroPack
Module ST5
Pin Number
P1/P2/P3/P4
8-Pin Headers
J5 USB 2.0
TypeA2
Or J6 USB
Mini3
J7
Ethernet4
J4
68 Pin
Champ
Carrier
Connector1
Diff0_P (TTL0) B26_TTL0 P1-1 1 2
Diff0_N (TTL1) B26_TTL1 P1-3 35 1
Diff1_P (TTL2) B26_TTL2 P1-5 2 6
Diff1_N (TTL3) B26_TTL3 P1-7 36 5
Diff2_P (TTL4) B26_TTL4 P1-2 3 10
Diff2_N (TTL5) B26_TTL5 P1-4 37 9
Diff3_P (TTL6) GND P1-6 4 14
Diff3_N (TTL7) B26_TTL7 P1-8 38 13
Diff4_P (TTL8) B26_TTL6 P2-3 5 18
Diff4_N (TTL9) B26_TTL9 P2-5 39 17
Diff5_P (TTL10) B26_TTL8 P2-2 6 22
Diff5_N (TTL11) B26_TTL11 P2-4 40 21
Diff6_P (TTL12) B26_TTL10 P2-6 7 26
Diff6_N (TTL13) B26_TTL13 P2-8 41 25
Diff7_P (TTL14) B26_TTL12 P3-1 8 30

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Diff7_N (TTL15) B26_TTL15 P3-3 42 29
Diff8_P (TTL16) B26_TTL14 P3-5 9 34
Diff8_N (TTL17) B26_TTL17 P3-7 43 33
Diff9_P (TTL18) B26_TTL16 P3-2 10 38
Diff9_N (TTL19) B26_TTL19 P3-4 44 37
Diff10_P (TTL20) B26_TTL18 P3-6 11 42
Diff10_N (TTL21) GND P3-8 45 41
Diff11_P (TTL22) RS485_A_P P4-3 12 46
Diff11_N (TTL23) RS485_A_N P4-5 46 45
Diff12_P (TTL24) RS485_B_P P4-2 13 50
Diff12_N (TTL25) RS485_B_N P4-4 47 49
Diff13_P (TTL26) RS485_C_P P4-6 14 54
Diff13_N (TTL27) RS485_C_N P4-8 48 53
MIO44_UART1_TX MIO44_UART1_TX J6 15 58
MIO45_UART1_RX MIO45_UART1_RX J6 49 57
USB_UART1_CTS USB_UART1_CTS J6 16 62
USB_UART1_RTS USB_UART1_RTS J6 50 61
ULPIO_D_P ULPIO_D_P J5 17 66
ULPIO_D_N ULPIO_D_N J5 51 65
ULPIO_VBUS ULPIO_VBUS J5 18 70
GND GND GND P2-7
P4-7
52 69
Eth_LED0 Eth_LED0 J7 19 74
Eth_LED1 Eth_LED1 J7 53 73
PHY_MDI0_P PHY_MDI0_P J7 20 78
PHY_MDI0_N PHY_MDI0_N J7 54 77
PHY_MDI1_P PHY_MDI1_P J7 21 82
PHY_MDI1_N PHY_MDI1_N J7 55 81
PHY_MDI2_P PHY_MDI2_P J7 22 86
PHY_MDI2_N PHY_MDI2_N J7 56 85
PHY_MDI3_P PHY_MDI3_P J7 23 90
PHY_MDI3_N PHY_MDI3_N J7 57 89
GND GND GND P2-7
P4-7
24 94
VCC_3V3 VCC_3V3 P2-1, P4-1 58 93
PS_POR_PB PS_POR_PB SW2 Reset 25 98
POWER_EN_PB POWER_EN_PB SW1 Power 59 97
Notes (2.1):
1. J4 – Carrier Field I/O 68-pin Champ Manufacturer Name: TE Connectivity Part: 5796055-1
2. J5 – USB Shielded I/O Receptacle Molex 67329-8001

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3. J6 – MINI USB I/O Receptacle Tyco Electronics 1-1734035
4. J7 – Ethernet Gigabit MagJack Bel 08261K1T23-F
2.5 Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector on
the carrier board. The pin assignments of this connector are standard for all
AP modules according to the PCI Express MINI Card Electromechanical
Specification, REV 1.2 (with exceptions shown in Table 2.3 and noted
below).
Threaded metric M2.5 screws and spacers are supplied with the AP module
carriers and conduction cooling kit to provide additional stability for harsh
environments.
Power supplies +5, +12, and -12 Volt have been assigned to pins that are
reserved in the mini-PCIe specification. The Present signal is grounded on
the AP module. In addition, COEX1, COEX2 – wireless transmitter control
are reassigned to JTAG signals TMS and TCK. Lastly, UIM_C4, UIM_C8 –
reserved User Identity Module signals are reassigned to JTAG signals TDI and
TDO.
Table 2.3 Logic Interface Connections
Pin # Name Pin # Name
51 +5V2 52 +3.3V3
49 +12V2 50 GND
47 -12V2 48 +1.5V
45 Present2 46 N.C. (LED_WPAN#)1
43 GND 44 N.C. (LED_WLAN#)1
41 +3.3V3 42 N.C. (LED_WWAN#)1
39 +3.3V3 40 GND
37 GND 38 N.C. (USB_D+)1
35 GND 36 N.C. (USB_D-)1
33 PETp0 34 GND
31 PETn0 32 SMB_DATA4
29 GND 30 SMB_CLK4
27 GND 28 +1.5V
25 PERp0 26 GND
23 PERn0 24 +3.3V3
21 GND 22 PERST#
19 TDI (UIM_C4)1 20 N.C. (W_DISABLE#)1
17 TDO (UIM_C8)1 18 GND
15 GND 16 UIM_VPP
13 RECLK+ 14 UIM_RESET
11 REFCLK- 12 UIM_CLK
9 GND 10 UIM_DATA

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7 CLKREQ# 8 UIM_PWR
5 TCK (COEX2)1 6 +1.5V
3 TMS (COEX1)14 GND
1 N.C. (WAKE#)1 2 +3.3V3
Note 1: The following mini-PCIe signals are not used by the APZU+: USB_D+, USB_D-, WAKE#, LED_WPAN#,
LED_WLAN#, LED_WWAN#, W_DISABLE#. Signal COEX1, COEX2, UIM_C4, UIM_C8 have been repurposed for
JTAG
Note 2: +5, +12, and -12 Volt power supplies have been assigned to pins that are reserved in the mini-PCIe
specification.
Note 3: All +3.3Vaux power pins are changed to system +3.3V power.
Note 4: The Present signal is tied to circuit common on the AP module.
Note 5: The SM bus signals SMB_CLK and SMB_DATA will be used to clock a carrier location serial stream from
the carrier. These signals are under the control of the AcroPack module.

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3.0 PROGRAMMING INFORMATION
This Section provides the specific information necessary to program and
operate the APZU+ module.
The PCIe bus is defined to address three distinct address spaces: I/O,
memory, and configuration space. The AcroPack module can be accessed
via the PCIe bus memory space and configuration spaces, only.
The AcroPack configuration registers are initialized by system software at
power-up to configure the card. The AcroPack module is a Plug-and-Play
PCIe card. As a Plug-and-Play card the board’s base address and system
interrupt request are not selected via jumpers but are assigned by system
software upon power-up via the configuration registers. A PCIe bus
configuration access is used to access the AcroPack’s configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCIe bus to determine what PCIe devices
are present. The software also determines the configuration requirements
of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory base address.
Since this board is not fixed in address space, its device driver must use the
mapping information stored in the board’s Configuration Space registers to
determine where the board is mapped in memory space.
The configuration registers are also used to indicate that the board requires
an interrupt request. The system software then programs the configuration
registers with the interrupt request for the board.
CONFIGURATION REGISTERS
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers shown in the following table to facilitate Plug-and-
Play compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers and the Interrupt Register which must be read to
determine the base address assigned to the board and the interrupt request
that goes active on a board interrupt request.

SERIES APZU+ ACROPACK USER’S MANUAL
Acromag, Inc. Tel: [phone] - 17 - www.acromag.com
Table 3.1 Configuration Registers
Reg.
Num.
D31 D24 D23 D16 D15 D8 D7 D0
0 Device ID
0x7731 APZU-301(E)
0x7733 APZU-303(E)
0x7734 APZU-304(E)
Vendor ID
16D5
1 Status Command
2 Class Code=118000 Rev ID=00
3 BIST Header Latenc
y
Cache
4:6 32-bit Memory Base Address for Memory Accesses to PCIe
1M Space (BAR0)
32K Space (BAR1)
64K Space (BAR2)
7:10 Not Used
11 Subsystem ID
0x7731 APZU-301(E)
0x7733 APZU-303(E)
0x7734 APZU-304(E)
Subsystem Vendor ID
16D5
12 Not Used
13,14 Reserved
15 Max
_
Lat Min
_
Gnt Inter. Pin Inter. Line
This board is allocated a 1M byte block of memory (BAR0), to access the
Zynq DMA registers. The PCIe bus decodes 1M bytes for BAR0 for this
memory space.
This board is allocated a 32K byte block of memory (BAR1), to access the
programmable logic registers. The PCIe bus decodes 32K bytes for BAR1 for
this memory space.
The memory space address map for the APZU+ is shown in Table 3.2. The
Zynq memory space allocated for the programmable logic starts at
0xA000_0000. An ingress translation register maps BAR1 PCIe bus 32K byte
space into the Zynq memory space starting at 0xA000_0000. Note that the
base address for the board (BAR1) in memory space must be added to
0xA000_0000 to properly access the FPGA programmable logic registers.
Register accesses as 32, 16, and 8-bit data in memory space are permitted.
In addition, the ingress translation register maps BAR2 PCIe bus space 64K
byte space into the Zynq DDR memory space starting at 0x100_0000.

SERIES APZU+ ACROPACK USER’S MANUAL
Acroma
g,
Inc. Tel: [phone] - 18 - www.acroma
g
.com
Table 3.2: BAR1 Memory Map
This board is addressable in the PCIe memory space to control the
configuration and status monitoring of the following board functions.
Base Address Size Description
00000_0000→0x0000_1FFF 8k M01_AXI (Digital I/O, Direction
Control, Interrupts)
0x0000_2000→0x0000_3FFF 4k
System Management Wizard
(System Monitor)
0x0000_4000→0x0000_7FFF 4k Block RAM
Table 3.3: BAR1 M01_AXI Memory Map
Note that any registers/bits not
mentioned will remain at the
default value logic low.
BAR1 Base Address Bit(s) Description
0x0000 0000 31:0 Global Interrupt Register
0x0000 0004 31:0 Location in System Register
0x0000 0008 31:0 Digital Input/Output Register
0x0000 000C 31:0 Digital Direction Control Register
0x0000 0010 31:0 Interrupt Enable Register
0x0000 0014 31:0 Interrupt Type Register
0x0000 0018 31:0 Interrupt Polarity Register
0x0000 001C 31:0 Interrupt Status Register
0x0000 0020 31:0 NOT USED
0x0000 0024 31:0 NOT USED
0x0000 0028 31:0 NOT USED
0x0000 002C 31:0 RS485 Data Register1
0x0000 0030 31:0 RS485 Direction Control Register1
0x0000 0034→
0x0000 01FF 31:0 NOT USED
0x0000 0200 31:0 Firmware Revision Register
0x0000 0204→
0x0000 1FFF 31:0 NOT USED2
Note 1: RS485 is only available on the APZU-303 model.

SERIES APZU+ ACROPACK USER’S MANUAL
Acromag, Inc. Tel: [phone] - 19 - www.acromag.com
Global Interrupt Register (Read/Write) - (BAR1 + 0x0000 0000)
This read/write register is used to: globally enable board interrupts and
determine the pending status of interrupts.
An enabled Event Sense bit and the board interrupt enabled when both
enabled will allow interrupts to be generated.
The function of each of the interrupt register bits are described in Table 3.6.
This register can be read or written with either 8-bit, 16-bit, or 32-bit data
transfers. A power-up or system reset sets all interrupt register bits to 0.
Table 3.4 Interrupt Register
Note that any registers/bits not
mentioned will remain at the
default value logic low.
Bit(s) FUNCTION
0
Board Interrupt Enable Bit. This bit must be set to logic “1” to
enable generation of interrupts from the AP module. Setting
this bit to logic “0” will disable board interrupts. (Read/Write
Bit)
0 Disabled
1 Enabled
1
Interrupt Pending Status Bit. This bit can be read to
determine the interrupt pending status of the AP module.
When this bit is logic “1” an interrupt is pending and will cause
an interrupt request if bit-0 of the register is set. When this
bit is logic “0” an interrupt is not being requested.
The Interrupt Status Register should be used to identify the
source of the interrupting channel. This is a read only bit.
Write to this bit will not cause the bit to change. Only clearing
the pending interrupts will clear this bit.
0 No Interru
p
t
1 Interru
p
t Pendin
g
31 to 2 Not Used
Module Location In System Register (Read Only) - (BAR1 + 0x0000 0004)
This read only register is used identify the module’s plugin location in a
system.
Table 3.5 Location Register
Note that any registers/bits not
mentioned will remain at the
default value logic low.
Bit(s) FUNCTION
2 to 0
Module Site Location Bits. These bits identify the location on
the carrier of the AP module.
000 Carrier Site A
001 Carrier Site B
010 Carrier Site C
011 Carrier Site D