Acromag XMC-6VLX Series User manual

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XMC-6VLX Conduction Cooled
Virtex-6 Based FPGA
XMC Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
P.O. BOX 437
Wixom, MI 48393-7037 U.S.A.
Tel: [phone]
Copyright 2012, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8500-931C

XMC-6VLX
USER’S MANUAL
Acromag, Inc. Tel: [phone] - 1 - http://www.acromag.com
- 1 -
www.acromag.com
Table of Contents
1.0 GENERAL INFORMATION..............................................................................................5
Ordering Information...........................................................................................................6
Key Features........................................................................................................................6
PCle Interface Features ........................................................................................................7
Software..............................................................................................................................8
ENGINEERING DESIGN KIT ........................................................................................................................... 8
BOARD DLL CONTROL SOFTWARE ............................................................................................................... 8
BOARD VxWORKS SOFTWARE ..................................................................................................................... 8
BOARD Linux SOFTWARE ............................................................................................................................. 8
2.0 PREPARATION FOR USE ...............................................................................................9
Unpacking and Inspecting ....................................................................................................9
Card Cage Considerations ....................................................................................................9
Heat Sink Considerations .....................................................................................................9
Board Installation......................................................................................................................................... 9
Default Hardware Configuration ............................................................................................................... 10
P16 Secondary XMC Connector ................................................................................................................. 10
Rear P4 Field I/O Connector ...................................................................................................................... 11
Mezzanine Connector ................................................................................................................................ 12
Non-Isolation Considerations.............................................................................................13
3.0 PROGRAMMING INFORMATION.............................................................................. 14
GETTING STARTED .............................................................................................................14
Virtex 6 Configuration................................................................................................................................ 15
Platform Flash Xilinx Configuration ........................................................................................................... 15
BPI Flash Xilinx Configuration .................................................................................................................... 15
PCIe CONFIGURATION ADDRESS SPACE..............................................................................16
CONFIGURATION REGISTERS ..................................................................................................................... 16
BAR0 MEMORY MAP .........................................................................................................18
INTERRUPT CONTROLLER ...................................................................................................19

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Interrupt Status Register (Read/Write) - (BAR0 + 0x00100000)................................................................ 19
Interrupt Pending Register (Read) - (BAR0 + 0x00100004) ....................................................................... 20
Interrupt Enable Register (Read/Write) - (BAR0 + 0x00100008) ............................................................... 20
Interrupt Acknowledge Register (Write) - (BAR0 + 0x0010000C).............................................................. 21
Set Interrupt Enable Register (Write) - (BAR0 + 0x00100010)................................................................... 21
Clear Interrupt Enable Register (Write) - (BAR0 + 0x00100014) ............................................................... 22
Interrupt Vector Register (Read) - (BAR0 + 0x00100018).......................................................................... 22
Master Enable Register (Read/Write) - (BAR0 + 0x0010001C) .................................................................. 22
AXI-CDMA .........................................................................................................................23
CDMA Control Register (Read/Write) - (BAR0 + 0x000A0000) .................................................................. 24
CDMA Status Register (Read/Write) - (BAR0 + 0x000A0004).................................................................... 26
CDMA Current Descriptor Pointer Register (Read/Write) - (BAR0 + 0x000A0008) ................................... 29
CDMA Tail Descriptor Pointer Register (Read/Write) - (BAR0 + 0x000A0010).......................................... 30
CDMA Source Address Register (Read/Write) - (BAR0 + 0x000A0018) ..................................................... 31
CDMA Destination Address Register (Read/Write) - (BAR0 + 0x000A0020) ............................................. 31
CDMA Bytes to Transfer Register (Read/Write) - (BAR0 + 0x000A0028) .................................................. 32
Simple CDMA Programming Example........................................................................................................ 32
AXI-BAR0 Aperture Base Address .......................................................................................33
PCIe AXI-Bridge Control .....................................................................................................34
Physical Side Interface Status/Control Register (Read/Write) - (BAR0 + 0x000F0144) ............................. 34
AXI Base Address Translation Configuration Register (Read Only) - (BAR0 + 0xF0208/0xF020C) ............. 35
FPGA Fabric MEMORY MAP ...............................................................................................36
Front, Rear, and P16 I/O Registers (Read/Write) –(BAR0 + 0x301000 to 0x 301FFF)............................... 37
Front I/O Interrupt Status/Clear Register (Read/Write) - (BAR0 + 0x300000) .......................................... 37
DDR Memory Test Status Register (Read/Write) - (BAR0 + 0x300008) ..................................................... 38
XMC Board Identification Code Register (Read Only) - (BAR0 + 0x30000C) .............................................. 38
Configuration Control (Read/Write) –(BAR0 + 0x300100)........................................................................ 38
Aurora Monitor (Read/Write) –(BAR0 + 0x300104) ................................................................................. 39
Flash Introduction...................................................................................................................................... 39
Flash Status (Read Only) –(BAR0 + 0x300200).......................................................................................... 41
Flash Control (Write Only) –(BAR0 + 0x300204)....................................................................................... 42
Flash Read (Read Only) –(BAR0 + 0x300208)............................................................................................ 42
Flash Start Write (Write Only) –(BAR0 + 0x30020C) ................................................................................. 43
Flash Erase Block (Write Only) –(BAR0 + 0x300210)................................................................................. 43
Flash Data Register (Read/Write) –(BAR0 + 0x300214)............................................................................ 43
Flash Address (Read/Write) –(BAR0 + 0x300218)..................................................................................... 43
Simple BPI Flash Programming Example.................................................................................................... 44
Simple Platform Flash Programming Example........................................................................................... 44
System Monitor Status/Control Register (Read/Write) –(BAR0 + 0x300300) .......................................... 45
System Monitor Address Register (Write Only) –(BAR0 + 0x300304) ...................................................... 45
Front Input Data Register (Read Only) - (BAR0 + 0x301000) ..................................................................... 46

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Front Output Data Register (Read/Write) - (BAR0 + 0x301004)................................................................ 46
Front I/O Interrupt Enable Register (Read/Write) - (BAR0 + 0x301008) ................................................... 47
Interrupt Type (COS or H/L) Configuration Register (Read/Write) - (BAR0 + 0x30100C) .......................... 47
Interrupt Polarity Register (Read/Write) - (BAR0 + 0x301010) ................................................................. 48
Rear Input Data Register (Read Only) - (BAR0 + 0x301100) ...................................................................... 49
Rear Output Data Register (Read/Write) - (BAR0 + 0x301104) ................................................................. 50
P16 Input Data Register (Read Only) - (BAR0 + 0x301200)........................................................................ 51
P16 Output Data Register (Write Only) - (BAR0 + 0x301204).................................................................... 52
BAR2 MEMORY MAP .........................................................................................................53
QDR Memory (Read/Write) –(BAR2 + 0x0000000 to 0x00FFFFFF)........................................................... 53
4.0 THEORY OF OPERATION ........................................................................................... 54
PCI INTERFACE LOGIC ................................................................................................................................ 55
DDR3 Memory ........................................................................................................................................... 55
QDR II+ SRAM Memory.............................................................................................................................. 55
Clock Generation ....................................................................................................................................... 56
Multi-Gigabit Transceivers (GTX MGTs)..................................................................................................... 56
SFP Module Connectors............................................................................................................................. 56
USB-to-UART Bridge................................................................................................................................... 56
16MB Platform Flash ................................................................................................................................. 57
32MB Linear BPI Flash ............................................................................................................................... 57
Configuration Flash Design Considerations ............................................................................................... 58
JTAG Port ................................................................................................................................................... 58
DIP Switch .................................................................................................................................................. 59
Power System Devices ............................................................................................................................... 59
System Monitor ......................................................................................................................................... 61
5.0 XPS EMBEDDED SYSTEM ........................................................................................... 62
Xilinx ISE Example Projects ........................................................................................................................ 62
Microblaze Peripherals .............................................................................................................................. 64
Host Peripherals......................................................................................................................................... 65
Common Peripherals ................................................................................................................................. 65
SDK............................................................................................................................................................. 65
Acromag Peripheral Repository ................................................................................................................. 67
Acromag modified library files................................................................................................................... 68
Running a Program from BPI FLASH Memory............................................................................................ 69
Running LWIP Echo Server......................................................................................................................... 72
EDK File Organization................................................................................................................................. 74
Example EDK Design Modification Walkthrough....................................................................................... 74
6.0 SERVICE AND REPAIR...............................................................................................101

XMC-6VLX
USER’S MANUAL
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Service and Repair Assistance ..........................................................................................101
Preliminary Service Procedure .........................................................................................101
Where to Get Help...........................................................................................................101
7.0 SPECIFICATIONS.........................................................................................................102
PHYSICAL.................................................................................................................................................. 102
POWER REQUIREMENTS .......................................................................................................................... 102
ENVIRONMENTAL .................................................................................................................................... 102
User Programmable (U2) FPGA ............................................................................................................... 103
EDK Example Design ................................................................................................................................ 103
P15 Connector ......................................................................................................................................... 103
P16 Connector ......................................................................................................................................... 104
P4 REAR I/O.............................................................................................................................................. 104
MEZZANINE FRONT I/O............................................................................................................................ 104
Board Oscillators...................................................................................................................................... 105
DDR3 Memory ......................................................................................................................................... 105
QDR II+ SRAM Memory............................................................................................................................ 105
16MB Platform Flash ............................................................................................................................... 106
32MB Linear BPI Flash ............................................................................................................................. 106
PCIe Bus Interface.................................................................................................................................... 106
XMC-6VLX Block Diagram.................................................................................................108
Certificate of Volatility.....................................................................................................109
REVISION HISTORY ..........................................................................................................110
All trademarks are the property of their respective owners.
IMPORTANT SAFETY CONSIDERATIONS
You must consider the possible negative effects of power, wiring, component, sensor, or software failure in the
design of any type of control or monitoring system. This is very important where property loss or human life is
involved. It is important that you perform satisfactory overall system design and it is agreed between you and
Acromag, that this is your responsibility.
The information of this manual may change without notice. Acromag makes no warranty of any kind with
regard to this material, including, but not limited to, the implied warranties of merchantability and fitness
for a particular purpose. Further, Acromag assumes no responsibility for any errors that may appear in this
manual and makes no commitment to update, or keep current, the information contained in this manual.
No part of this manual may be copied or reproduced in any form without the prior written consent of
Acromag, Inc.

XMC-6VLX
USER’S MANUAL
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RELATED PUBLICATIONS
The following manuals and part specifications provide the necessary information for in depth understanding of
the XMC-6VLX board.
Virtex-6 Data Book Spec
http://www.xilinx.com
CY7C1565KV18-400BZC Spec.
http://www.cypress.com
MT41J128M16HA-15EIT Spec.
http://www.micron.com
1.0 GENERAL INFORMATION
This XMC-6VLX is an XMC module with the heart of the design being the
Virtex 6 reprogrammable FPGA. The re-configurable XMC-6VLX modules
use the Xilinx Virtex 6 XC6VLX FPGA. Re-configuration of the FPGA is
possible via a direct download into the Xilinx Platform Flash over the PCIe
bus. The on board Platform Flash memory loaded with FPGA configuration
data allows automatic Xilinx configuration on power-up.
The XMC-6VLX is an XMC module with the following interfaces. Eight high
speed serial lanes are allocated to the XMC P15 connector. These lanes can
be used for an 8 lane PCIe (PCI Express) implementation, Serial RapidIO, or
10 Gigabit Ethernet. The example design will support a 4 lane Gen 1 PCIe
implementation with one DMA channel for data transfer between PCIe and
on board QDRII memory.
Eight high speed serial lanes are also allocated to the XMC P16 connector.
These eight serial lanes can be used for Serial RapidIO, PCIe, 10 Gigabit
Ethernet, or Xilinx Aurora. The example design will support an 8 lane Aurora
implementation for use of these lanes. Two Virtex 6 global clocks and 34
select I/O signals will also be provided on the P16 connector. Select I/O
signals are 2.5V Virtex 6 I/O pins that can be selected from single-ended I/O
standards (LVCMOS, HSTL, and SSTL) and differential I/O standards (LVDS,
HT, LVPECL, BLVDS, Differential HSTL and SSTL).
One P4 rear I/O connector will provide two global clock differential pairs,
and 30 LVDS signal pairs.
One mezzanine connector will provide JTAG, USB signals, two global
differential clock pairs, 11 LVDS signal pairs, and two ground signals. Two
high speed serial interfaces are also routed from the FPGA to this mezzanine
module connector.
The board will provide 2 Meg x 72-bit QDRII SRAM, 128 Meg x 64-bit DDR3
SDRAM, 4 Meg x 16-bit parallel Flash, and Xilinx 128 Megabit Platform Flash.
The parallel Flash will interface to the FPGA for MicroBlaze CPU program

XMC-6VLX
USER’S MANUAL
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Ordering Information
The following table lists the orderable models and their corresponding
operating temperature range.
Models XMC-6VLX240 and XMC-6VLX365 are conduction-cooled without
front I/O.
Table 1.1: The XMC-6VLX
boards are available in the
standard temperature range.
MODEL
OPERATING TEMPERATURE RANGE
XMC-6VLX240
0C to +70C
XMC-6VLX365
0C to +70C
Key Features
An XMC-6VLX block diagram, found at the end of this manual, illustrates the
key features listed below.
Reconfigurable Xilinx FPGA –In system configuration of the FPGA is
performed through flash configuration. The PCIe bus can be used to
change the flash configuration memory. This provides a means for
creating custom user defined designs. The Virtex 6 will configure from
the updated Platform flash on the next power cycle.
QDRII SRAM –Provides 2 Meg x 72-bit QDRII SRAM. SRAM is linked to
the Virtex 6 device for PCIe bus, and DMA engine access. It can also be
linked to front, rear, and high speed data path access.
DDR3 SDRAM –Provides 128 Meg x 64-bit DDR3 SDRAM. SDRAM is
linked to the Virtex 6 device for MicroBlaze and Ethernet access.
P15 High Speed Interface –The Eight high speed serial lanes are
allocated to the XMC P15 connector. These lanes can be used for an 8
lane PCIe (PCI Express) implementation, Serial RapidIO, or 10 Gigabit
Ethernet. The example design will support a 4 lane Gen 1 PCIe
implementation.
P16 High Speed Interface –The Eight high speed serial lanes are
allocated to the XMC P16 connector. These lanes can be used for Serial
RapidIO, PCIe, 10 Gigabit Ethernet, or Xilinx Aurora. The example design
will support an 8 lane Aurora loopback implementation.
Interface to Rear P4 Connector –The Virtex 6 FPGA is directly
connected to 64 pins of the rear P4 connector. All 2.5volt IO standards
supported by the Virtex 6 device are available. The example design
code storage. The Xilinx 128 Megabit Platform Flash will contain the power
up configuration bit file for the Virtex 6 FPGA.

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USER’S MANUAL
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provides LVCMOS single ended signaling.
Interface to Mezzanine Connector –The Virtex 6 FPGA is directly
connected to a front mezzanine connector. All 2.5volt IO standards
supported by the Virtex 6 device are available on 13 signal pairs. JTAG
for Virtex 6 configuration and use with Xilinx ChipScope FPGA signal
analysis tool. USB is provides a MicroBlaze debug terminal port. Two
high speed serial interfaces are also routed from the FPGA to this
mezzanine module connector.
Example Design Provided –The example VHDL design includes
implementation of the PCIe bus 4 lane Gen 1, control of digital front and
rear I/O, and QDRII read/write interface logic, SFP module interface for
1 Gig Ethernet with DDR3 Memory.
PCle Interface Features
PCIe Bus –An example design is provided with four lane PCI Express
Generation 1 operating at a bus speed of 2.5 Gbps per lane per
direction. This gives up to 2GBytes/sec data rate on the bus. FPGA
supports Gen1 8-lane (x8) or Gen2 4-lane (x4).
PCIe Bus Master –The PCIe interface logic becomes the bus master to
perform DMA transfers.
DMA Operation –The PCIe bus interface supports one DMA channel
capable of transferring data to and from the on board QDRII SRAM.
Compatibility –PCI Express Base Specification v2.0 compliant PCI
Express Endpoint. Provides one multifunction interrupt. The XMC-6VLX
is compatible with XMC VITA 42.3 specification for P15.

XMC-6VLX
USER’S MANUAL
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Software
The XMC-6VLX products will require support drivers specific to your
operating system.
ENGINEERING DESIGN KIT
Acromag provides an engineering design kit for the 6VLX boards (sold
separately), a “must buy” for first time 6VLX module purchasers. The design
kit (model XMC-6VLX-EDK) provides the user with the basic information
required to develop a custom FPGA program for download to the Xilinx
user-programmable FPGA. The design kit includes a CD containing:
schematics, parts list, part location drawing, example VHDL source, and
other utility files. The 6VLX modules are intended for users fluent in the use
of Xilinx FPGA design tools.
BOARD DLL CONTROL SOFTWARE
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with Acromag PMC,
XMC, and VPX I/O board products, PCI and PCIe I/O Cards, and CompactPCI
I/O Cards. This software (models PCISW-API-WIN32 and PCISW-API-WIN64)
consists of low-level drivers and Dynamic Link Libraries (DLLs) that are
compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
BOARD VxWORKS SOFTWARE
Acromag provides a software product (sold separately) consisting of board
VxWorkssoftware. This software (Model PMCSW-API-VXW) is composed
of VxWorks(real time operating system) libraries for all Acromag PMC,
XMC, and VPX I/O board products, PCI and PCIe I/O Cards, and CompactPCI
I/O Cards. The software is implemented as a library of “C” functions which
link with existing user code to make possible simple control of all Acromag
PCI and PCIe boards.
BOARD Linux SOFTWARE
Acromag provides a software product consisting of board Linuxsoftware.
This software (Model PMCSW-API-LNX) is composed of Linuxlibraries for
all Acromag PMC, XMC, and VPX I/O board products, PCI and PCIe I/O cards,
and CompactPCI I/O cards. The software supports X86 PCI bus only and is
implemented as library of “C” functions which link with existing user code to
make possible simple control of all Acromag PCI and PCIe boards.

XMC-6VLX
USER’S MANUAL
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2.0 PREPARATION FOR USE
Unpacking and Inspecting
WARNING: This board utilizes
static sensitive components
and should only be handled at
a static-safe workstation.
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.
Card Cage Considerations
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, adequate air circulation must be provided to
prevent a temperature rise above the maximum operating temperature and
to prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermo conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
Heat Sink Considerations
When the XMC-6VLX board is mounted on a conduction cooled carrier it
may be necessary to remove the Acromag provided heat sink. The heat sink
can be removed by removal of the 7 screws retaining the heat sink. These 7
screws are visible on the back of the board. After the 7 screws are removed,
lift the heat sink off and wipe clean the silver colored thermal interface
material from the Virtex 6 device.
Board Installation
Remove power from the system before installing board, cables, termination
panels, and field wiring.

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Default Hardware Configuration
The board may be configured differently, depending on the application.
When the board is shipped from the factory, it is configured with the
Acromag example design as follows:
Slave SelectMap using Platform Flash (XCF128X) with onboard 48 MHz
oscillator.
The control registers must be programmed to the desired configuration
before starting data input or output operation (see section 3).
P16 Secondary XMC Connector
The P16 secondary XMC connector connects directly to the user-
programmable FPGA for both high speed Giga bit data signals and standard
I/O user signals. The user I/O pins are connected to FPGA banks with VCCO
pins powered by 2.5 volts. Thus these user I/O pins will support the 2.5 volt
IOStandards. The IOSTANDARD attribute can be set in the user constraints
file (UCF). For example, P16 user I/O can be defined for LVDS_25 (Low-
Voltage Differential Signaling). The example design defines the P16 I/O to
LVCMOS25 (low voltage CMOS) in the user constraints file. The tables
included in the P16 Input Data Register and P16 Output Data Register
sections can be used to map the LVCMOS signal to the signal names given in
this table. The 2.5 volt IOStandards available are listed in the Virtex-6 User
Guide available from Xilinx.
Table 2.1: Board P16
Secondary XMC Connections
The example design implements
2.5volt LVCMOS I/O to the P16
connector.
Alternatively, 2.5volt LVDS I/O
can be used on the rear
connector.
Pin
A
B
C
D
E
F
1
DP00+
DP00-
S18G_N
DP01+
DP01-
S18G_P
2
GND
GND
S16_N
GND
GND
S17_N
3
DP02+
DP02-
S16_P
DP03+
DP03-
S17_P
4
GND
GND
S14_N
GND
GND
S15_N
5
DP04+
DP04-
S14_P
DP05+
DP05-
S15_P
6
GND
GND
S12_N
GND
GND
S13_N
7
DP06+
DP06-
S12_P
DP07+
DP07-
S13_P
8
GND
GND
S10_N
GND
GND
S11_N
9
DP08+
DP08-
S10_P
DP09+
DP09-
S11_P
10
GND
GND
S8_N
GND
GND
S9_N
11
DP10+
DP10-
S8_P
DP11+
DP11-
S9_P
12
GND
GND
S6_N
GND
GND
S7_N
13
DP12+
DP12-
S6_P
DP13+
DP13-
S7_P
14
GND
GND
S4_N
GND
GND
S5_N
15
DP14+
DP14-
S4_P
DP15+
DP15-
S5_P
16
GND
GND
S2_N
GND
GND
S3_N
17
DP16+
DP16-
S2_P
DP17+
DP17-
S3_P
18
GND
GND
S0G_N
GND
GND
S1_N
19
DP18+
DP18-
S0G_P
DP19+
DP19-
S1_P
As LVDS signal pairs, the signals can be grouped to match the ANSI/VITA
46.0 X38s pattern map. A total of 19 differential signal pairs are provided.
These differential signal pairs connect to column C and F of the P16 XMC

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connector as shown in the following table. For example S3_P and S3_N
form a signal pair. There are two global clock differential pairs available
(S0G_P, S0G_N) and (S18G_P, S18G_N). The P identifies the Positive input
while the N identifies the Negative input.
This XMC P16 Secondary connector is a 114-pin Samtec ASP-103614-05
connector. The connector complies with the ANSI/VITA 42.3-2006.
Rear P4 Field I/O Connector
The rear I/O P4 connector connects directly to the user-programmable
FPGA. The VCCO pins are powered by 2.5 volts and thus will support the 2.5
volt IOStandards. The IOSTANDARD attribute can be set in the user
constraints file (UCF). The example design defines the Rear P4 I/O to
LVCMOS25 (low voltage CMOS) in the user constraints file. The tables
included in the Rear Input Data Register and Rear Output Data Register
sections can be used to map the LVCMOS signal to the signal names given in
the table below.
The rear I/O can alternatively be defined for LVDS_25 (Low-Voltage
Differential Signaling) in the user constraints file. The 2.5 volt IOStandards
available are listed in the Virtex-6 User Guide available from Xilinx.
As LVDS signal pairs, the signals can be grouped as 32 LVDS I/O pairs. The
LVDS pairs are arranged in the same row in table 2.2. For example, RIO1_P
and RIO1_N form a signal pair. The P identifies the Positive input while the
N identifies the Negative input.
Table 2.2: Board Rear Field I/O
Pin Connections.
The example design implements
2.5volt LVCMOS I/O to the rear
connector.
Alternatively, 2.5volt LVDS I/O
can be used on the rear
connector.
Ch.
Positive Pin Description
Pin
Negative Pin Description
Pin
0
RIO0_GCLK_P
1
RIO0_GCLK_N
3
1
RIO1_P
2
RIO1_N
4
2
RIO2_P
5
RIO2_N
7
3
RIO3_P
6
RIO3_N
8
4
RIO4_P
9
RIO4_N
11
5
RIO5_P
10
RIO5_N
12
6
RIO6_P
13
RIO6_N
15
7
RIO7_P
14
RIO7_N
16
8
RIO8_P
17
RIO8_N
19
9
RIO9_P
18
RIO9_N
20
10
RIO10_P
21
RIO10_N
23
11
RIO11_P
22
RIO11_N
24
12
RIO12_P
25
RIO12_N
27
13
RIO13_P
26
RIO13_N
28
14
RIO14_P
29
RIO14_N
31
15
RIO15_P
30
RIO15_N
32
16
RIO16_P
33
RIO16_N
35
17
RIO17_P
34
RIO17_N
36
18
RIO18_P
37
RIO18_N
39
19
RIO19_P
38
RIO19_N
40

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20
RIO20_P
41
RIO20_N
43
21
RIO21_P
42
RIO21_N
44
22
RIO22_P
45
RIO22_N
47
23
RIO23_P
46
RIO23_N
48
24
RIO24_P
49
RIO24_N
51
25
RIO25_P
50
RIO25_N
52
26
RIO26_P
53
RIO26_N
55
27
RIO27_P
54
RIO27_N
56
28
RIO28_P
57
RIO28_N
59
29
RIO29_P
58
RIO29_N
60
30
RIO30_P
61
RIO30_N
63
31
RIO31_GCLK_P
62
RIO31_GCLK_N
64
This connector is a 64-pin female receptacle header (AMP 120527-1 or
equivalent) which mates to the male connector on the carrier board (AMP
120521-1 or equivalent).
Mezzanine Connector
The mezzanine connector provides interface to JTAG, USB and 13
differential I/O signal pairs. Two of these 13 signal pairs are routed to global
clock pins on the Virtex 6 device. Two high speed serial interfaces are also
routed from the FPGA to this mezzanine module connector.
The 26 front I/O signals connect directly to the user-programmable FPGA.
The VCCO pins are powered by 2.5 volts and thus will support the 2.5 volt
IOStandards. The IOSTANDARD attribute can be set in the user constraints
file (UCF). The example design defines the Front I/O to LVCMOS25 (low
voltage CMOS) in the user constraints file. The tables included in the Front
Input Data Register and Front Output Data Register sections can be used to
map the LVCMOS signal to the signal names given in the table below.
The Front I/O can alternatively be defined for LVDS_25 (Low-Voltage
Differential Signaling) in the user constraints file. The 2.5 volt IOStandards
available are listed in the Virtex-6 User Guide available from Xilinx.
Table 2.3: Board Mezzanine
Pin Connections.
The example design implements
2.5volt LVCMOS I/O to the front
connector.
Alternatively, 2.5volt LVDS I/O
can be used on the front
connector.
Ch.
Positive Pin
Pin
Negative Pin
Pin
TCK
A57
TMS
B50
TDO
A58
TDI
A64
0
FIO0_P
B55
FIO0_N
B54
1
FIO1_P
B51
FIO1_N
B52
2
FIO2_P
B47
FIO2_N
B48
3
FIO3_P
B44
FIO3_N
B45
4
FIO4_P
B41
FIO4_N
B42
5
FIO5_P
B38
FIO5_N
B39
6
FIO6_P
B35
FIO6_N
B36
7
FIO7_P
B32
FIO7_N
B33
8
FIO8_P
B29
FIO8_N
B30
9
FIO9_P
B26
FIO9_N
B27
10
FIO10_P
B23
FIO10_N
B24

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11
FIO11_GCLK_P
B20
FIO11_GCLK_N
B21
12
FIO12_GCLK_P
B17
FIO12_GCLK_N
B18
USB_D+
A7
USB_D-
A6
USB_VBUS(from host)
A9
SFP1_TX_Fault
B14
SFP2_TX_Fault
B11
SFP1_LOS
B15
SFP2_LOS
B12
SFP1_Present_n
A16
SFP2_ Present_n
A15
SFP1_clock
A18
SFP2_clock
A19
SFP1_data
A22
SFP2_data
A21
SFP1_TX_Disable
A25
SFP2_TX_Disable
A24
SFP1_TX_P
A28
SFP1_TX_N
A29
SFP1_RX_P
A31
SFP1_RX_N
A32
SFP2_TX_P
A34
SFP2_TX_N
A35
SFP2_RX_P
A37
SFP2_RX_N
A38
+3.3V
B10, B13, B16, B53
+2.5V
B1, B2, B3
+12V
A2
GND
A5, A8, A11A14, A17, A20, A23, A26, A17,
GND
A20, A23, A26, A27, A30, A33, A36, A39,
GND
A42, A45, A48, A51, A54, A67, A70, A73
GND
B19, B22, B25, B28, B31, B34, B37, B40,
GND
B43, B46, B49, B73
Non-Isolation Considerations
The board is non-isolated, since there is electrical continuity between the
logic and field I/O grounds. As such, the field I/O connections are not
isolated from the system. Care should be taken in designing installations
without isolation to avoid noise pickup and ground loops caused by multiple
ground connections.

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3.0 PROGRAMMING INFORMATION
GETTING STARTED
1. The XMC-6VLX board is shipped with the user-programmable Xilinx
FPGA code stored in the Platform Configuration flash memory (U1).
Upon power-up the XMC-6VLX will automatically configure the FPGA
with the example design code stored in flash. As a first step become
familiar with the XMC-6VLX, with the example code supplied by
Acromag. The board will perform all the functions of the example
design as described in this manual.
The Example Design Memory Map section gives a description of the I/O
operations performed by the example design. It will allow testing of
PCIe interface, read/write of QDRII SRAM, all digital I/O ports,
interrupts, testing of both SFP Ports, P16 Aurora loopback, and DMA
operation. It is strongly recommended that you become familiar with
the board features by using the example design as provided by
Acromag.
CAUTION: Do not attempt to reconfigure the flash memory until after
you have tested and become familiar with the XMC-6VLX as provided
in the example design.
2. After you are familiar with the XMC-6VLX and have tested it using the
example design, you can move on to step 2. Here you will modify the
example design VHDL code slightly. The Xilinx Platform Configuration
flash must be overwritten to test your code. Once the flash is erased
you will not be able to go back to the example design by simply
powering down and restarting the board. If your code does not function
as desired you may need to return to use of the Acromag design
example. You can reload the Acromag example design via the EDK
board and the JTAG port using the Xilinx iMPACT tool. Upon power-up,
the example design provided by Acromag will again be loaded into the
FPGA.
See the Flash Configuration section for a description of the steps
required to write new data or to reprogram the example design code to
the Platform flash device. Registers are provided in the FPGA
Programming Memory Map to implement Platform or BPI flash erase
and reprogram operations.
This Section provides the specific information necessary to program and
operate the board.

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Virtex 6 Configuration
The XMC-6VLX board supports configuration in the following modes:
Slave SelectMAP using Xilinx Platform Flash XL with onboard 48 MHz
oscillator. The Xilinx Platform flash configuration device contains the
Acromag example design.
Master BPI-Up using Linear BPI Flash device. A BPI flash device is
recommended for MicroBlaze program storage.
JTAG using Xilinx external program cable.
Upon a power-up cycle, the contents of the Xilinx Platform flash device are
downloaded to the FPGA. See chapter 4 for DIP switch setting options.
Platform Flash Xilinx Configuration
The Xilinx Platform flash configuration data can be reprogrammed using the
PCIe bus interface or the JTAG interface. The following is the general
procedure for reprogramming the Platform flash memory and
reconfiguration of the Xilinx FPGA:
1. Set DIP switch 5 to the OFF position. This will enable selection of the
Platform flash device and disable selection of the BPI flash device. Set
DIP switch 2 and 3 to the ON position. This will select Slave SelectMAP
mode.
2. Power Cycle the System with the XMC-6VLX module. At power-up the
configuration file will automatically be loaded into the FPGA provided
the DIP switch is set as described in the preceding step for configuration
from Platform flash.
BPI Flash Xilinx Configuration
The Byte-wide Peripheral Interface (BPI) flash is recommended for
MicroBlaze CPU program code storage. The following is the general
procedure for reprogramming the BPI flash memory:
1. Set DIP switch 5 to the ON position. This will enable selection of the BPI
flash device and disable selection of the Platform flash device.
2. See the Flash Configuration section for a description of the steps
required to write new data or program code to the BPI Flash device.
Registers are provided in the FPGA Programming Memory Map to
implement BPI flash erase and reprogram operations.

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PCIe CONFIGURATION ADDRESS SPACE
This board is a PCI Express Base Specification Revision v2.0 compliant PCIe
bus board.
The PCI bus is defined to address three distinct address spaces: I/O,
memory, and configuration space. This board can be accessed via the PCIe
bus memory, and configuration spaces.
The card’s configuration registers are initialized by system software at
power-up to configure the card. The board is a Plug-and-Play PCIe card. As
a Plug-and-Play card the board’s base address and system interrupt request
are not selected via jumpers but are assigned by system software upon
power-up via the configuration registers. A PCIe bus configuration access is
used to read/write the PCIe card’s configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCIe bus to determine what PCIe devices
are present. The software also determines the configuration requirements
of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory base address.
Since this board is relocatable and not fixed in address space, its device
driver must use the mapping information stored in the board’s
Configuration Space registers to determine where the board is mapped in
memory space.
The configuration registers are also used to indicate that the board requires
an interrupt request. The system software then programs the configuration
registers with the interrupt request assigned to the board.
CONFIGURATION REGISTERS
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers, shown in Table 3.1, to facilitate Plug-and-Play
compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers and the Interrupt Register which must be read to
determine the base address assigned to the board and the interrupt request
that goes active on a board interrupt request.

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Table 3.1 Configuration
Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID
0x6301 XMC-6VLX240F
0x6302 XMC-6VLX365F
0x6303 XMC-6VLX240
0x6304 XMC-6VLX365
Vendor ID
16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
64-bit Memory Base Address for Memory Accesses to PCIe
interrupt, I/O registers, System Monitor registers, and Flash
memory.
4M Space (BAR0)
5
64-bit Memory Base Address for Memory Accesses to QDRII
memory.
16M Space (BAR2)
6:10
Not Used
11
Subsystem ID
0x6301 XMC-6VLX240F
0x6302 XMC-6VLX365F
0x6303 XMC-6VLX240
0x6304 XMC-6VLX365
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 4M byte block of memory (BAR0), to access the
PCIe interrupt, I/O registers, System Monitor registers, and Flash memory.
The PCIe bus decodes 4M bytes for BAR0 for this memory space.
This board is also allocated a 16M byte block of memory (BAR2), to access
QDRII memory. The PCIe bus decodes 16M bytes for BAR2 for this memory
space.

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BAR0 MEMORY MAP
The BAR0 memory address space is used to access the PCIe interrupt, Front,
Rear, and P16 I/O registers, System Monitor registers, and Flash memory.
Note that the base address for the board (BAR0) in memory space must be
added to the addresses shown to properly access these registers.
Table 3.2: BAR0 Registers
Note that any registers/bits not
mentioned will remain at the
default value logic low.
BAR0 Base Address
Size
Description
0x00000000→0x0000FFFF
64K
Reserved
0x00010000→0x0001FFFF
64K
Reserved
0x00020000→0x0009FFFF
512K
Reserved
0x000A0000→0x000AFFFF
64K
AXI CDMA (DS792)
0x000B0000→0x000EFFFF
256K
Reserved
0x000F0000→0x000FFFFF
64K
PCIe AXI Bridge Control (DS820)
0x00100000→0x010FFFFF
64K
PCIe Interrupt Controller
0x00110000→0x002FFFFF
2M
Reserved
0x00300000→0x0030FFFF
64K
Flash, I/O Reg, System Monitor,
and Aurora
0x00310000→0x003FFFFF
1M
Reserved