Acromag IP502 Series User manual

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Series IP502 Industrial I/O Pack
Quad EIA RS-485 Serial Communication Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
P.O. BOX 437
Wixom, MI 48393-7037 U.S.A.
Tel: [phone]
Fax: [phone]
Copyright 1995, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8500-547-D02A009

SERIES IP502 INDUSTRIAL I/O PACK QUAD EIA RS-485 SERIAL COMMUNICATION MODULE
___________________________________________________________________________________________
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The information contained in this manual is subject to change
without notice. Acromag, Inc. makes no warranty of any kind with
regard to this material, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose.
Further, Acromag, Inc. assumes no responsibility for any errors that
mayappear in this manual and makes no commitment to update, or
keep current, the information contained in this manual. No part of
this manual may be copied or reproduced in anyform, without the
prior written consent of Acromag, Inc.
Table of Contents Page
1.0 GENERAL INFORMATION............................................... 2
KEY IP502 FEATURES..................................................... 2
INDUSTRIAL I/O PACK INTERFACE FEATURES.......... 3
SIGNAL INTERFACE PRODUCTS.................................. 3
INDUSTRIAL I/O PACK SOFTWARE LIBRARY.............. 3
2.0 PREPARATION FOR USE................................................ 4
UNPACKING AND INSPECTION..................................... 4
CARD CAGE CONSIDERATIONS................................... 4
BOARD CONFIGURATION.............................................. 4
CONNECTORS................................................................. 4
IP Field I/O Connector (P2)............................................ 4
Noise and Grounding Considerations............................. 5
IP Logic Interface Connector (P1).................................. 5
3.0 PROGRAMMING INFORMATION.................................... 5
ADDRESS MAPS.............................................................. 5
IP Communication & Configuration Registers................ 7
IP Identification PROM................................................... 12
THE EFFECT OF RESET................................................. 12
IP502 PROGRAMMING.................................................... 12
FIFO Polled Mode.......................................................... 13
FIFO Interrupt Mode....................................................... 13
Generating Interrupts..................................................... 13
4.0 THEORY OF OPERATION............................................... 15
RS-485 SERIAL INTERFACE........................................... 15
IP502 OPERATION........................................................... 16
LOGIC/POWER INTERFACE........................................... 16
5.0 SERVICE AND REPAIR.................................................... 16
SERVICE AND REPAIR ASSISTANCE........................... 16
PRELIMINARY SERVICE PROCEDURE......................... 16
6.0 SPECIFICATIONS............................................................. 17
GENERAL SPECIFICATIONS.......................................... 17
RS-485 PORTS................................................................. 17
TRANSCEIVERS.............................................................. 17
INDUSTRIAL I/O PACK COMPLIANCE........................... 17
APPENDIX......................................................................... 18
CABLE: MODEL 5025-550. & 5025-551........................... 18
CABLE: MODEL 5029-943................................................ 18
CABLE: MODEL 5029-900................................................ 18
TERMINATION PANEL: MODEL 5025-552..................... 18
TERMINATION PANEL: MODEL 5029-910..................... 19
TRANSITION MODULE: MODEL TRANS-GP................. 19
DRAWINGS Page
4501-434 IP MECHANICAL ASSEMBLY......................... 20
4501-556 IP502 COMMUNICATION CABLE.................... 21
4501-558 IP502 INTERFACE DIAGRAM......................... 22
4501-559 IP502 TERM/BIAS RESISTOR LOCATION..... 23
4501-557 IP502 BLOCK DIAGRAM.................................. 24
4501-462 CABLE 5025-550 (NON-SHIELDED).............. 25
4501-463 CABLE 5025-551 (SHIELDED)........................ 26
4501-464 TERMINATION PANEL 5025-552................... 27
4501-465 TRANSITION MODULE TRANS-GP............... 28
IMPORTANT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible adverse
effects of power, wiring, component, sensor, or software failures in
designing any type of control or monitoring system. This is
especially important where economic property loss or human life is
involved. It is important that the user employ satisfactory overall
system design. It is agreed between the Buyer and Acromag, that
this is the Buyer's responsibility.
1.0 GENERAL INFORMATION
The Industrial I/O Pack (IP) Series IP502 module provides four
asynchronous EIA RS-485 serial communication ports for
interfacing to the VMEbus or PC bus. This model includes half-
duplexdata paths which permits bi-directional data transmission,
one direction at a time. Four units may be mounted on a carrier
board to provide up to 16 asynchronous serial ports per 6U-VMEbus
system slot or ISA bus (PC/AT) system slot.
The electrical characteristics of the RS-485 standard specifies
transceivers that implement differential data transmission. The use
of differential data transmission allows the reliable transmission of
data at high rates over up to 4000 meter distances and through noisy
environments. Differential transmission nullifies the effects of
ground shifts and noise signals which appear as common-mode
voltages on the line.
Up to 32 network nodes can be connected to each cable
segment. This is achieved by using tri-state drivers under program
control. Standard protocols (for example polling or token-bus) can
be used to ensure only one driver is active at a time.
The transmit and receive paths of each channel include
generous 16-byte FIFO buffers to minimize CPU interaction.
Programmable baud rates up to 512K baud are supported. In
addition, character size, stop bits, and parity are software
configurable. Prioritized interrupt generation is supported for
transmit, and receive line-status.
The IP502 utilizes state of the art Surface-Mounted Technology
(SMT) to achieve its wide functionality and is an ideal choice for a
wide range of industrial communication interface applications that
require a highly reliable, high-performance interface at a low cost.
KEY IP502 FEATURES
•High Density - Provides programmable control of four EIA RS-
485 asynchronous serial ports. Four units mounted on a
carrier board provide 16 serial channels in a single VMEbus or
ISA bus (PC/AT) system slot.
•16-Character FIFO Buffers - Both the transmit and receive
channels of each serial port provide 16-byte (plus 3 bits per
byte) data buffering to reduce CPU interactions and interrupts.
•Programmable Character Size - Each serial port is software
programmable for 5, 6, 7, or 8 bit character sizes.
•Programmable Stop Bits - Each serial port allows 1, 1-1/2, or
2 stop-bits to be added to, or deleted from, the serial data
stream.

SERIES IP502 INDUSTRIAL I/O PACK QUAD EIA RS-485 SERIAL COMMUNICATION MODULE
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•Programmable Parity Generation & Detection - Even, Odd,
or No Parity generation and detection is supported.
•Line-Break Generation & Detection - provision for sending
and detecting the line break character is provided.
•False Start Bit Detection - Prevents the receiver from
assembling false data characters due to low-going noise spikes
on the RxD input line.
•Programmable Baud Rate - The internal baud rate generator
allows the 8MHz clock to be divided by anydivisor between 1
and 2(16-1), providing support for bit rates up to 512Kbps.
•Interrupt Support - Individually controlled transmit, receive,
line status, and data set interrupts may be generated. Unique
interrupt vectors may be assigned to each port. Interrupt
generation uses a priority shifting scheme based on the last
interrupt serviced, preventing the continuous interrupts of one
port from freezing out the interrupts of another port.
•Socketed Termination and Bias Resistors - The network
termination and bias resistors are installed in sockets on the
board and may be easily inserted or removed where required.
•Internal Diagnostic Capabilities - Loopback controls for
communication link fault isolation are included. Break, parity,
overrun, and framing error simulation is also possible.
•Fail safe Receivers - The receivers employed in this model
include a fail safe feature which guarantees a high output state
when the inputs are left open or floating.
•Industry Standard 16550 Family UART w/16C450 Mode -
The UART of this device is a member of the industry standard
16550 family of UART’s and remains software compatible.
Additionally, this device can operate in a 16C450 UART family
software compatible mode. The transmit and receive channels
are double-buffered in this mode. Hold and shift registers
eliminate the need for precise synchronization between the host
CPU and the serial data.
INDUSTRIAL I/O PACK INTERFACE FEATURES
•High density - Single-size, industry standard, IP module
footprint. Four units mounted on a carrier board provide up to
16 serial ports in a single system slot. Both VMEbus and ISA
bus (PC/AT) carriers are supported.
•Local ID - Each IP module has its own 8-bit ID PROM which
can be read via access to the "ID PROM" space.
•8-bit I/O - Port register Read/Write is performed through 8-bit
data transfer cycles in the IP module I/O space.
•High Speed - Access times for all data transfer cycles are
described in terms of "wait" states - 2 wait states are required
for reading and writing channel data and for interrupt select
cycles, 1 wait state for reading the ID PROM (see
Specifications section for detailed information).
SIGNAL INTERFACE PRODUCTS
(See Appendixfor more information on compatible products)
This IP module will mate directly to any industry standard IP
carrier board (including Acromag AVME9630/9660 3U/6U non-
intelligent VMEbus carrier boards). Additionally, Acromag’s
APC8600 ISA bus (PC/AT) carrier board is also supported. A wide
range of other Acromag IP modules are also available to serve your
signal conditioning and interface needs.
The following cables and termination panels are also available.
Consult your carrier board documentation for the correct interface
product part numbers to ensure compatibility with your carrier board.
Cables
Model 5025-551-X (Shielded Cable), or Model 5025-550-X
(Non-Shielded Cable): A Flat 50-pin cable with female
connectors at both ends for connecting AVME9630/9660, or
other compatible carrier boards, to Model 5025-552 termination
panels. The “-X” suffix of the model number is used to indicate
the length in feet. The unshielded cable is recommended for
digital I/O, while the shielded cable is recommended for
optimum performance with precision analog I/O applications.
Model 5029-943 IP500 Serial Communication Cable: A 5 foot
long, flat 50-pin cable with a female connector on one end (for
connection to AVME9630/9660 or other compatible carrier
boards) and four DE-9P connectors (serial ports) on the other
end. Also used for interface with Acromag Model IP501 (RS-
422) & IP502 (RS-485) serial communication modules.
Model 5029-900 APC8600 High-Density Cable: A 36-inch long
interface cable that mates the high-density (25mil pitch) 50-pin
I/O connectors of the APC8600 ISA bus carrier board, to the
high-density connectors on the APC8600 Termination Panel
(described below).
Termination Panels:
Model 5025-552: A DIN-rail mountable panel that provides 50
screw terminals for universal field I/O termination. Connects to
Acromag AVME9630/9660, or other compatible carrier boards,
via flat 50-pin ribbon cable (Model 5025-550-X or 5025-551-X).
Model 5029-910 APC8600 High-Density-to-Screw-Terminal
Termination Panel: This panel converts the high-density ribbon-
cable connectors coming from the APC8600 carrier board
(Acromag cable Model 5029-900) to screw terminals, for direct-
wired interfaces.
Transition Module:
Model TRANS-GP: This module repeats field I/O connections
of IP modules A through D for rear exit from a VMEbus card
cage. It is available for use in card cages which provide rear exit
for I/O connections via transition modules (transition modules
can only be used in card cages specifically designed for them).
It is a double-height (6U), single-slot module with front panel
hardware adhering to the VMEbus mechanical dimensions,
except for shorter printed circuit board depth. It connects to
Acromag Termination Panel 5025-552 from the rear of the card
cage, and to AVME9630/9660 boards within the card cage, via
flat 50-pin ribbon cable (cable Model 5025-550-X or 5025-551-
X).
INDUSTRIAL I/O PACK SOFTWARE LIBRARY
Acromag provides an Industrial I/O Pack Software Library
diskette (Model IPSW-LIB-M03, MSDOS format) to simplify
communication with the board. Example software functions are
provided for both VMEbus and ISA bus (PC/AT) applications. All
functions are written in the “C” programming language and can be
linked to your application. For more details, refer to the
“README.TXT” file in the root directory on the diskette and the
“INFO502.TXT” file in the appropriate “IP502” subdirectory off of
“\VMEIP” or “\PCIP”, according toyour carrier.

SERIES IP502 INDUSTRIAL I/O PACK QUAD EIA RS-485 SERIAL COMMUNICATION MODULE
___________________________________________________________________________________________
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2.0 PREPARATION FOR USE
UNPACKING AND INSPECTION
Upon receipt of this product, Inspect the shipping carton for
evidence of mishandling during transit. If the shipping carton is
badlydamaged or water stained, request that the carrier's agent be
present when the carton is opened. If the carrier's agent is absent
when the carton is opened and the contents of the carton are
damaged, keep the carton and packing material for the agent's
inspection.
For repairs to a product damaged in shipment, refer to the
Acromag Service Policy to obtain return instructions. It is suggested
that salvageable shipping cartons and packing material be saved for
future use in the event the product must be shipped.
This board is physically protected with
packing material and electrically
protected with an anti-static bag during
shipment. However, it is recommended
that the board be visually inspected for
evidence of mishandling prior to applying
power.
The board utilizes static sensitive
components and should only be handled
at a static-safe workstation.
CARD CAGE CONSIDERATIONS
Refer to the specifications for loading and power requirements.
Be sure that the system power supplies are able to accommodate
the power requirements of the carrier board, plus the installed IP
modules, within the voltage tolerances specified.
IMPORTANT: Adequate air circulation must be provided to prevent
a temperature rise above the maximum operating temperature.
The dense packing of the IP modules to the carrier board
restricts air flow within the card cage and is cause for concern.
Adequate air circulation must be provided to prevent a temperature
rise above the maximum operating temperature and to prolong the
life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
BOARD CONFIGURATION
Remove power from the board when installing IP modules,
cables, termination panels, and field wiring. Refer to Mechanical
Assembly Drawing 4501-434 and your IP module documentation for
configuration and assembly instructions. Model IP502 communica-
tion boards have no hardware jumpers or switches to configure.
However, network termination and bias resistor SIP’s are installed in
sockets on the board and can be easily removed where required
(refer to Drawing 4501-558 & 4501-559).
IMPORTANT: The IP502 comes with network termination (120Ω)
and bias (560Ω) resistors installed in sockets on the board. You
need to consider your network application carefully, and remove
resistors where appropriate. Termination resistors should only be
installed at the ends of the network. Likewise, a network channel
only needs one set of bias resistors, usually on the driving end. You
should also remove redundant bias resistors where appropriate.
Failure to remove termination and bias resistors where required will
significantly increase current draw and in some cases, may affect
performance. Refer to Drawing 4501-558 and 4501-559 for
instructions.
CONNECTORS
IP Field I/O Connector (P2)
P2 provides the field I/O interface connections for mating IP
modules to the carrier board. P2 is a 50-pin female receptacle
header (AMP 173279-3 or equivalent) which mates to the male
connector of the carrier board (AMP 173280-3 or equivalent). This
provides excellent connection integrity and utilizes gold-plating in the
mating area. Threaded metric M2 screws and spacers are supplied
with the module to provide additional stability for harsh environments
(see Mechanical Assembly Drawing 4501-434). The field and logic
side connectors are keyed to avoid incorrect assembly. P2 pin
assignments are unique to each IP model (see Table 2.1) and
normally correspond to the pin numbers of the field I/O interface
connector on the carrier board (you should verify this for your carrier
board).
Table 2.1: IP502 Field I/O Pin Connections (P2)
Pin Description Number Pin Description Number
COMMON 1 COMMON 26
Not Used 2 Not Used 27
TXRX+_A 3 TXRX+_C 28
Not Used 4 Not Used 29
TXRX-_A 5 TXRX-_C 30
Not Used 6 Not Used 31
TXRX-_A 7 TXRX-_C 32
Not Used 8 Not Used 33
TXRX+_A 9 TXRX+_C 34
COMMON 10 COMMON 35
Not Used 11 Not Used 36
TXRX+_B 12 TXRX+_D 37
Not Used 13 Not Used 38
TXRX-_B 14 TXRX-_D 39
Not Used 15 Not Used 40
TXRX-_B 16 TXRX-_D 41
Not Used 17 Not Used 42
TXRX+_B 18 TXRX+_D 43
COMMON 19 COMMON 44
COMMON 20 COMMON 45
COMMON 21 COMMON 46
COMMON 22 COMMON 47
COMMON 23 COMMON 48
COMMON 24 COMMON 49
COMMON 25 COMMON 50
An Asterisk (*) is used to indicatean active-low signal.

SERIES IP502 INDUSTRIAL I/O PACK QUAD EIA RS-485 SERIAL COMMUNICATION MODULE
___________________________________________________________________________________________
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Note that the pin-wire assignments are arranged such that IDC
D-SUB ribbon cable connectors can be conveniently attached to
provide serial port A (pins 1-9), serial port B (pins 10-18), serial port
C (pins 26-34), & serial port D (pins 35-43) connectivity. Plus (+)
and minus (-) following the signal name indicate differential signal
polarity. In Table2.1, asuffix of “_A”, “_B”, “_C”, or “_D” is
appended to each pin label to denote its port association. A brief
description of each of the serial port signals at P2 is included next.
A complete functional description of the P2 pin functions is included
in Section 4.0 (Theory Of Operation). Be careful not to confuse the
four RS485 ports A-D of the IP502 module with the carrier board’s
four IP module slots A-D.
Table 2.2: P2 Pin Signal Descriptions
SIGNAL DESCRIPTION
TXRX+_A
TXRX+_B
TXRX+_C
TXRX+_D
Transmit Data Line Output and Receive Data Line
Input +. To the communication network master this
line is used as the + transmit data line. To the
communication network slaves this line is used as
the + receive data line.
TXRX-_A
TXRX-_B
TXRX-_C
TXRX-_D
Transmit Data Line Output and Receive Data Line
Input -. To the communication network master this
line is used as the - transmit data line. To the
communication network slaves this line is used as
the - receive data line.
Note that not all UART signal paths are used by this model and
their corresponding UART pins are tied high (+5V). This includes,
RI (Ring Indicator), CTS (Clear To Send), DSR (Data Set Ready),
and DCD (Data Carrier Detect). In addition, the UART RTS (Ready
To Send) signal active while DTR (Data Terminal Ready) signal
inactive enables the transceivers to transmit data. As shown in the
table below, RTS and DTR in any other state enables the transceiver
to receive data.
RTS DTR Transceiver Mode
Inactive Inactive Receive
Inactive Active Receive
Active Inactive Transmit
Active Active Receive
Noise and Grounding Considerations
The serial channels of this module are non-isolated and share a
common signal ground connection. Further, the IP502 is non-
isolated between the logic and field I/O grounds since signal
common is electrically connected to the IP module ground.
Consequently, the field interface connections are not isolated from
the carrier board and backplane. Care should betaken in designing
installations without isolation to avoid noise pickup and ground loops
caused by multiple ground connections.
The signal ground connection at the communication ports are
common to the IP interface ground, which is typically common to
safety (chassis) ground when mounted on a carrier board and
inserted in a backplane. As such, be careful not to attach signal
ground to safety ground via any device connected to these ports, or
a ground loop will be produced, and this may adversely affect
operation.
The communication cabling of the P2 interface carries digital
data at a high transfer rate. For best performance, increased signal
integrity, and safety reasons, you should isolate these connections.
Keep them away from power and other wiring to avoid noise-coupling
and crosstalk interference. EIA RS-485 communication distances
are generally limited to less than 4000 feet. Always keep interface
cabling and ground wiring as short as possible for best performance.
Please refer to Drawing 4501-556 for example connections and
proper grounding practices.
IP Logic Interface Connector (P1)
P1 of the IP module provides the logic interface to the mating
connector on the carrier board. This connector is a 50-pin female
receptacle header (AMP 173279-3 or equivalent) which mates to the
male connector of the carrier board (AMP 173280-3 or equivalent).
This provides excellent connection integrity and utilizes gold-plating
in the mating area. Threaded metric M2 screws and spacers are
supplied with the IP module to provide additional stability for harsh
environments (see Drawing 4501-434 for assemblydetails). Field
and logic side connectors are keyed to avoid incorrect assembly.
The pin assignments of P1 are standard for all IP modules
according to the Industrial I/O Pack Specification (see Table 2.3).
Table 2.3: Standard Logic Interface Connections (P1)
Pin Description Number Pin Description Number
GND 1 GND 26
CLK2+5V27
Reset* 3 R/W* 28
D00 4 IDSEL* 29
D01 5 DMAReq0* 30
D02 6 MEMSEL* 31
D03 7 DMAReq1* 32
D04 8 IntSel* 33
D05 9 DMAck0* 34
D06 10 IOSEL* 35
D07 11 RESERVED 36
D08 12 A1 37
D09 13 DMAEnd* 38
D10 14 A2 39
D11 15 ERROR* 40
D12 16 A3 41
D13 17 INTReq0* 42
D14 18 A4 43
D15 19 INTReq1* 44
BS0* 20 A5 45
BS1* 21 STROBE* 46
-12V 22 A6 47
+12V 23 ACK* 48
+5V 24 RESERVED 49
GND 25 GND 50
An Asterisk (*) is used to indicatean active-low signal.
BOLD ITALIC Logic Lines are NOT USED by this IP Model.
3.0 PROGRAMMING INFORMATION
ADDRESS MAPS
This board is addressable in the Industrial Pack I/O space to
control the interface configuration, data transfer, and steering logic
of four EIA RS-485 serial ports. As such, three types of information
are stored in the I/O space: control, status, and data. These
registers are listed below along with their mnemonics used
throughout this manual.

SERIES IP502 INDUSTRIAL I/O PACK QUAD EIA RS-485 SERIAL COMMUNICATION MODULE
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SERIAL DATA REGISTERS (Per Serial Port):
RBR Receive Buffer Register
THR Transmitter Holding Register
SERIAL STATUS REGISTERS (Per Serial Port):
LSR Line Status Register
MSR Modem Status Register
SERIAL CONTROL REGISTERS (Per Serial Port):
LCR Line Control Register
FCR FIFO Control Register
MCR Modem Control Register
DLL Divisor Latch LSB
DLM Divisor Latch MSB
IER Interrupt Enable Register
SCR Scratchpad/Interrupt Vector Register
The I/O space may be as large as 64, 16-bit words (128 bytes)
using address lines A1..A6, but the IP502 uses only a portion of this
space. The I/O space address map for the IP502 is shown in Table
3.1. Note the base address for the IP module I/O space (see your
carrier board instructions) must be added to the addresses shown to
properly access the I/O space. All accesses are to the low byte on
an 8-bit word basis (D0..D7).
This module supports byte accesses using the “Big Endian”
byte ordering format. Big Endian is the convention used in the
Motorola 68000 microprocessor family and is the VMEbus
convention. In Big Endian, the lower-order byte is stored at odd-byte
addresses. The Intel x86 family of microprocessors use the
opposite convention, or “Little Endian” byte ordering. Little Endian
uses even-byte addresses to store the low-order byte. As such, use
of this module on a PC carrier board will require the use of the even
address locations to access the lower 8-bit data while on a VMEbus
carrier use of odd address locations are required to access the lower
8-bit data.
Note that some functions share the same register address. For
these items, the address lines are used along with the divisor latch
access bit (bit 7 of the Line Control Register) and/or the read and
write signals to determine the function required. Beyond the first two
address locations for each serial port, the state of the divisor latch
access bit is irrelevant.
Table 3.1A: IP502 I/O Space Address (Hex) Memory Map
Serial Port A Registers:
Base
Addr+ MSB D15 D08 LSB D07 D00 LCR Bit7 Base Addr+
00 Not Driven1READ - RBR
Port A Receiver
Buffer Register 001
00 Not Driven1WRITE -THR
Port A Transmitter
Holding Register 001
00 Not Driven1R/W - DLL
Port A Divisor Latch
LSB 101
02 Not Driven1R/W - IER
Port A Interrupt
Enable Register 003
02 Not Driven1R/W - DLM
Port A Divisor Latch
MSB 103
Serial Port A Registers:
Base
Addr+ MSB D15 D08 LSB D07 D00 LCR Bit7 Base Addr+
04 Not Driven1READ - IIR
Port A Interrupt
Identification Register 05
04 Not Driven1WRITE -FCR
Port A FIFO Control
Register 05
06 Not Driven1R/W - LCR
Port A Line Control Register 07
08 Not Driven1R/W - MCR
Port A Modem Control
Register 09
0A Not Driven1R/W - LSR
Port A Line Status Register 0B
0C Not Driven1R/W - MSR
Port A Modem Status
Register 0D
0E Not Driven1R/W - SCR
Port A Scratch Pad/Interrupt
Vector Register 0F
Table 3.1B: IP502 I/O Space Memory Map...continued
Serial Port B Registers:
Base
Addr+ MSB D15 D08 LSB D07 D00 LCR Bit7 Base Addr+
10 Not Driven1READ - RBR
Port B Receiver
Buffer Register 011
10 Not Driven1WRITE -THR
Port B Transmitter
Holding Register 011
10 Not Driven1R/W - DLL
Port B Divisor Latch
LSB 111
12 Not Driven1R/W - IER
Port B Interrupt
Enable Register 013
12 Not Driven1R/W - DLM
Port B Divisor Latch
MSB 113
14 Not Driven1READ - IIR
Port B Interrupt
Identification Register 15
14 Not Driven1WRITE -FCR
Port B FIFO Control
Register 15
16 Not Driven1R/W - LCR
Port B Line Control Register 17
18 Not Driven1R/W - MCR
Port B Modem Control
Register 19
1A Not Driven1R/W - LSR
Port B Line Status Register 1B
1C Not Driven1R/W - MSR
Port B Modem Status
Register 1D
1E Not Driven1R/W - SCR
Port B Scratch Pad/Interrupt
Vector Register 1F

SERIES IP502 INDUSTRIAL I/O PACK QUAD EIA RS-485 SERIAL COMMUNICATION MODULE
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Table 3.1C: IP502 I/O Space Memory Map...continued
Serial Port C Registers:
Base
Addr+ MSB D15 D08 LSB D07 D00 LCR Bit7 Base Addr+
20 Not Driven1READ - RBR
Port C Receiver
Buffer Register 021
20 Not Driven1WRITE -THR
Port C Transmitter
Holding Register 021
20 Not Driven1R/W - DLL
Port C Divisor Latch
LSB 121
22 Not Driven1R/W - IER
Port C Interrupt
Enable Register 023
22 Not Driven1R/W - DLM
Port C Divisor Latch
MSB 123
24 Not Driven1READ - IIR
Port C Interrupt
Identification Register 25
24 Not Driven1WRITE -FCR
Port C FIFO Control
Register 25
26 Not Driven1R/W - LCR
Port C Line Control Register 27
28 Not Driven1R/W - MCR
Port C Modem Control
Register 29
2A Not Driven1R/W - LSR
Port C Line Status Register 2B
2C Not Driven1R/W - MSR
Port C Modem Status
Register 2D
2E Not Driven1R/W - SCR
Port C Scratch Pad/
Interrupt Vector Register 2F
This board operates in two different modes. In one mode, this
device remains software compatible with the industry standard
16C450 familyof UART’s and provides double-buffering of data
registers. In the FIFO Mode (enabled via bit 0 of the FCR register),
data registers are FIFO-buffered so that read and write operations
can be performed while the UART is performing serial-to-parallel
and parallel-to-serial conversions. Two FIFO modes are possible:
FIFO Interrupt Mode and FIFO Polled Mode. Some registers
operate differently between the available modes and this is noted in
the following paragraphs.
Table 3.1D: IP502 I/O Space Memory Map...continued
Serial Port D Registers:
Base
Addr+ MSB D15 D08 LSB D07 D00 LCR Bit7 Base Addr+
30 Not Driven1READ - RBR
Port D Receiver
Buffer Register 031
30 Not Driven1WRITE -THR
Port D Transmitter
Holding Register 031
30 Not Driven1R/W - DLL
Port D Divisor Latch
LSB 131
32 Not Driven1R/W - IER
Port D Interrupt
Enable Register 033
32 Not Driven1R/W - DLM
Port D Divisor Latch
MSB 133
34 Not Driven1READ - IIR
Port D Interrupt
Identification Register 35
34 Not Driven1WRITE -FCR
Port D FIFO Control
Register 35
36 Not Driven1R/W - LCR
Port D Line Control Register 37
38 Not Driven1R/W - MCR
Port D Modem Control
Register 39
3A Not Driven1R/W - LSR
Port D Line Status Register 3B
3C Not Driven1R/W - MSR
Port D Modem Status
Register 3D
3E Not Driven1R/W - SCR
Port D Scratch Pad/
Interrupt Vector Register 3F
40
↓
↓↓
↓
7E NOT USED241
↓
↓↓
↓
7F
Notes (Table 3.1A, B, C, and D):
1. The upper 8 bits of these registers are not driven. Pullups on
the carrier board data bus cause these bits to read high (1’s).
2. The IP will not respond to addresses that are "Not Used".
3. All Reads and writes are 2 wait states (except ID PROM reads
which are 1 wait state).
RBR - Receiver Buffer Register, Ports A-D (READ Only)
The Receiver Buffer Register (RBR) is a serial port input data
register that receives the input data from the receiver shift register
and holds from 5 to 8 bits of data, as specified by the character size
programmed in the Line Control Register (LCR bits 0 & 1). If less
than 8 bits are transmitted, then datais right-justified to the LSB. If
parity is used, then LCR bit 3 (parity enable) and LCR bit 4 (type of
parity) are required. Status for the receiver is provided via the Line-
Status Register (LSR). When a full character is received (including
parity and stop bits), the data-received indication bit 0 of the LSR is
set to 1. The host CPU then reads the RBR, which resets LSR bit 0
low. If the character is not read prior to a new character transfer
between the receiver shift register and the RBR, the overrun-error
status indication is set in LSR bit 1. If there is a parity error, the
error is indicated in LSR bit 2. If a stop bit is not detected, a framing
error indication is set in bit 3 of the LSR.

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Serial asynchronous data is input to the receiver shift register via
the receive data line (RxD). From the idle state, this line is
monitored for a high-to-low transition (start bit). When the start bit is
detected, a counter is reset and counts the 16x clock to 7-1/2 (which
is the center of the start bit). The start bit is judged valid if RxD is
still low at this point. This is known as false start-bit detection. By
verifying the start bit in this manner, it helps to prevent thereceiver
from assembling an invalid data character due to a low-going noise
spike on RxD. If the data on RxD is a symmetrical square wave, the
center of the data cells will occur within ±3.125% of the actual center
(providing an error margin of 46.875%). Thus, the start bit can
begin as much as one 16x clock cycle prior to being detected.
THR - Transmitter Holding Register, Ports A-D (WRITE Only)
The Transmitter Holding Register (THR) is a serial port output
data register that holds from 5 to 8 bits of data, as specified by the
character size programmed in the Line Control Register. If less than
8 bits are transmitted, then data is entered right-justified to the LSB.
This data is framed as required, then shifted to the transmit data line
(TxD). In the idle state, TxD is held high. In Loopback Mode, this
data is looped back into the Receiver Buffer Register.
DLL & DLM - Divisor Latch Registers, Ports A-D (R/W)
The Divisor Latch Registers form the divisor used by the internal
baud-rate generator to divide the 8MHz system clock to produce an
internal sampling clock suitable for synchronization to the desired
baud rate. The output of the baud generator (RCLK) is sixteen times
the baud rate. Two 8-bit divisor latch registers per port are used to
store the divisors in 16-bit binary format. The DLL register stores
the low-order byte of the divisor, DLM stores the high-order byte.
These registers must be loaded during initialization.
Note that bit 7 of the LCR register must first be set high to
access the divisor latch registers (DLL & DLM) during a read/write
operation.
Upon loading either latch, a 16-bit baud counter is immediately
loaded (this prevents long counts on initial load). The clock may be
divided by any divisor from 1 to 2(16-1). The output frequency of the
baud rate generator (RCLK) is 16x the data rate. The relationship
between the output of the baud generator (RCLK), the baud rate, the
divisor, and the 8MHz system clock can be summarized in the
following equations:
DIVISOR = CLOCK FREQUENCY ÷[BAUD RATE x 16];
RCLK = 16 x BAUD RATE;
= 16 x [CLOCK ÷(16 x DIVISOR)] = CLOCK ÷DIVISOR
The following table shows the correct divisor to use for
generation of some standard baud rates (based on the 8MHz clock).
Note that baud rates up to 512K may be configured. Provisions for
installation of an external crystal has been provided on the circuit
board (16MHz). With the 16MHz crystal higher baud rates are
possible--you maycontact Acromag Applications Engineering to
explore options in this area.
Table 3.2: Baud Rate Divisors and Relative Error (8MHz Clk)
BAUD RATE
DESIRED DIVISOR (N) USED FOR 16x CLOCK %ERROR DIFF BET DESIRED & ACTUAL
50 10000 2710H 0
75 6667 1A06H 0.005
110 4545 11C1H 0.010
134.5 3717 0E85H 0.013
150 3333 0D05H 0.010
300 1667 0683H 0.020
600 833 0341H 0.040
1200 417 01A1H 0.080
1800 277 0115H 0.080
2000 250 00FAH 0
2400 208 00D0H 0.160
3600 139 0086H 0.080
4800 104 0068H 0.160
7200 69 0045H 0.644
9600 52 0034H 0.160
19200 26 001AH 0.160
38400 13 000DH 0.160
56000 9 0009H 0.790
128000 4 0004H 2.344
256000 2 0002H 2.344
512000 1 0001H 2.400
With respect to this device, the baud rate may be considered
equal to the number of bits transmitted per second (bps). The bit
rate (bps), or baud rate, defines the bit time. This is the length of
time a bit will be held on before the next bit is transmitted. A receiver
and transmitter must be communicating at the same bit rate, or data
will be garbled. A receiver is alerted to an incoming character by the
start bit, which marks the beginning of the character. It then times
the incoming signal, sampling each bit as near to the center of the
bit time as possible.
To better understand the asynchronous timing used by this
device, note that the receive data line (RxD) is monitored for a high-
to-low transition (start bit). When thestart bit is detected, a counter
is reset and counts the 16x sampling clock to 7-1/2 (which is the
center of the start bit). The receiver then counts from 0 to 15 to
sample the next bit near its center. This continues until a stop bit is
detected which signals the end of the data stream. Use of a
sampling rate 16x the baud rate reduces the synchronization error
that builds up in estimating the center of each successivebit
following the start bit. As such, if the data on RxD is a symmetrical
square wave, the center of each successive data cell will occur
within ±3.125% of the actual center (this is 50% ÷16, providing an
error margin of 46.875%). Thus, the start bit can begin as much as
one 16xclock cycle prior to being detected.
IER - Interrupt Enable Register, Ports A-D (R/W)
The Interrupt Enable Register is used to independently enable/
disable the four possible serial channel interrupt sources that drive
the INTREQ0* line (Ports A-D share this line). Interrupts are
disabled by resetting the corresponding IER bit low (0), and enabled
by setting the IER bit high (1). Disabling the interrupt system (IER
bits 0-3 low) also inhibits the Interrupt Identification Register (IIR)
and the interrupt request line (INTREQ0*). All other functions
operate in their normal manner, including the setting of the Line
Status Register (LSR) and the Modem Status Register (MSR).
Enabling modem interrupts for the IP502 will have no effect since
modem interrupts are triggered off CTS* which is not used.

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Interrupt Enable Register
IER BIT INTERRUPT ACTION
0 Received Data Available Interrupt Enable and
Time-Out Interrupt (FIFO Mode) Enable
1 Transmitter Holding Register Empty Interrupt Enable
2 Receiver Line Status Interrupt Enable
3 Modem Status Interrupt Enable
4-7 Not Used - Set to Logic 0
A power-up or system reset sets all IER bits to 0 (bits 0-3 forced
low, bits 4-7 permanently low).
IIR - Interrupt Identification Register, Ports A-D (READ Only)
The Interrupt Identification Register is used to indicate that a
prioritized interrupt is pending and the typeof interrupt that is
pending. This register will indicate the highest-priority type of
interrupt pending for the channel. Individual serial channels prioritize
their interrupts into four levels (indicated below). This helps
minimize software overhead during data character transfers.
Additionally, with respect to the four channels sharing INTREQ0,
interrupts are served according to a shifting priority scheme that is a
function of the last port served. Modem interrupts are not possible
with the IP502 since the CTS* handshake line is not used.
PRIORITY/LEVEL INTERRUPT
1 Receiver Line Status
2 Received Data Ready or Character Time-out
3 Transmitter Holding Register Empty
4 Modem Status
The four lower order bits of this register are used toidentify the
interrupt pending as follows:
Interrupt Identification Register
BITS
3-0 INT
PRTY INTERR.
TYPE INTERRUPT SOURCE RESET CONTROL
0001 -- None None --
0110 1st Receiver
Line Status OE, PE, FE, or BI (See LSR
Bits 1-4)
LSR Read
0100 2nd Received
Data
Available
Receiver Data
Available or
Trigger Level
Reached
RBR Read till
FIFO below
trigger level
1100 2nd Character
Time-out
Indication
No characters
have been
removed from
or input to the
Rx FIFO
during last 4
character times
and there is at
least 1 char-
acter in it
during this time
RBR Read
0010 3rd THRE
(LSR Bit 5) THRE (LSR Bit 5) IIR Read (if LSR bit 5 is the
interrupt
source) or a
THR Write
0000 4th Modem
Status CTS* not used. Modem
interrupts are
not supported
MSR Read
Bits 4 and 5 of this register are always set to 0. Bits 6 and 7 are
set when bit 0 of the FIFO Control Register is set to 1. A power-up
or system reset sets IIR bit 0 to 1, bits 1,2,3,6, and 7 to 0, while bits
4 & 5 are permanently low.
FCR - FIFO Control Register, Ports A-D (WRITE Only)
This write-only register is used to enable and clear the FIFO
buffers, set the trigger level of the Rx FIFO, and select the type of
DMA signaling (DMA is NOT supported by this model).
A power-up or system reset sets all FCR bits to 0.
FIFO Control Register
FCR BIT FUNCTION
0 When set to “1”, this bit enables both the Tx and Rx
FIFO’s. All bytes in both FIFO’s can be cleared by
resetting this bit to 0. Data is cleared automatically
from the FIFO’s when changing from FIFO mode to
the alternate (16C450) mode and visa-versa.
Programming of other FCR bits is enabled by setting
this bit to 1.
1 When set to “1”, this bit clears all bytes in the Rx-
FIFO and resets the counter logic to 0 (this does not
clear the shift register).
2 When set to “1”, this bit clears all bytes in the Tx-
FIFO and resets the counter logic to 0 (this does not
clear the shift register).
3 When set to “1”, this bit sets DMA Signal from Mode
0 to Mode 1, if FIFO Control Register Bit 0 = 1 (DMA
Not Supported)
4,5 Not Used
6,7 Used for setting the trigger level of the Rx FIFO
interrupt as follows:
BIT 7-6 Rx-FIFO TRIGGER LEVEL
00 01 Bytes
01 04 Bytes
10 08 Bytes
11 14 Bytes
MCR - Modem Control Register, Ports A-D (R/W)
The Modem Control register controls the interface with the
modem or data set as described below. For this model, handshake
lines are not supported. The RTS output is directly controlled by its
control bit in this register (a high input asserts these signals) and is
used to enable the transceiver for data output.

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Modem Control Register
MCR
Bit FUNCTION PROGRAMMING
0Data
Terminal
Ready
Output
Signal
(DTR)
0=DTR* Not Asserted (Inactive)
1=DTR* Asserted (Active).
A DTR signal path is NOT SUPPORTED
by this model. Instead, this output is
used to enable the transceivers for data
input. DTR active enables data receive
mode.
1 Request to
Send
Output
Signal
(RTS)
0=RTS* Not Asserted (Inactive)
1=RTS* Asserted (Active)
A RTS signal path is NOT SUPPORTED
by this model. Instead, this output is
used to enable the transceivers for data
output. RTS active enables data
transmit mode.
2Out1
(Internal) No Effect on External Operation
3Out2
(Internal) 0=External Serial Channel Interrupt
Disabled
1=External Serial Channel Interrupt
Enabled
4 Loop10=Loop Disabled
1=Loop Enabled
5,6,7 Not Used Bits are set to logic 0
Notes (Modem Control Register):
1. MCR Bit 4 provides a local loopback feature for diagnostic
testing of the UART channel. When set high, the UART serial
output (connected to the TXD driver) is set to the marking (logic
1 state), and the UART receiver serial data input is
disconnected from the RxD receiver path. The output of the
UART transmitter shift register is then looped back into the
receiver shift register input. The four modem control inputs
(CTS, DSR, DCD, and RI) are disconnected from their receiver
input paths. The four modem control outputs (DTR, RTS,
OUT1, and OUT2) are internally connected to the four modem
control inputs (while their associated pins are forced to their
high/ inactive state). Thus, in the loopback diagnostic mode,
transmitted data is immediately received permitting the host
processor to verify the transmit and receive data paths of the
selected serial channel. In this mode, interrupts are generated
by controlling the state of the four lower order MCR bits
internally, instead of by the external hardware paths. However,
no interrupt request or interrupt vectors are actually served in
loopback mode, and interrupt pending status is only reflected
internally.
A power-up or system reset sets all MCR bits to 0 (bits 5-7 are
permanently low).
MSR - Modem Status Register, Ports A-D (Read/Write)
The Modem Status Register (MSR) provides the host CPU with
an indication on the status of the modem input lines from a modem
or other peripheral device. This model does not provide support for
handshake lines.
Modem Status Register
MSR BIT FUNCTION
0∆CTS - NOT SUPPORTED
1∆DSR - NOT SUPPORTED
2∆RI - NOT SUPPORTED
3∆DCD - NOT SUPPORTED
4 CTS - If the channel is in the loopback mode (MCR
bit 4 = 1), then the state of RTS in the MCR is
reflected
5 DSR - NOT SUPPORTED
6 RI - NOT SUPPORTED
7 DCD - NOT SUPPORTED
Note that reading MSR clears the delta-modem status indication
(bits 0), but has no effect on the other status bits. For both the LSR
& MSR, the setting of the status bit during a status register read
operation is inhibited (the status bit will not be set until the trailing
edge of the read). However, if the same status condition occurs
during a read operation, that status bit is cleared on the trailing edge
of the read instead of being set again.
A power-up or system reset sets MSR bit 0 to 0 (bit 4 is
determined by input signal). Unused bits are always clear.
LSR - Line Status Register, Ports A-D (Read/Write-Restricted)
The Line Status Register (LSR) provides status indication
corresponding to the data transfer. LSR bits 1-4 are the error
conditions that produce receiver line-status interrupts (a priority 1
interrupt in the Interrupt Identification Register). The line status
register may bewritten, but this is intended for factory test and
should be considered read-only by the applications software.
Line Status Register
LSR
Bit FUNCTION PROGRAMMING
0 Data Ready
(DR) 0=Not Ready (reset low by CPU Read of RBR or FIFO).
1=Data Ready (set high when character
received and transferred into the RBR
or FIFO).
1 Overrun
Error (OE) 0=No Error 1=Indicates that data in the RBR is not
being read before the next character is
transferred into the RBR, overwriting the
previous character. In the FIFO mode, it
is set after the FIFO is filled and the next
character is received. The overrun error
is detected by the CPU on the first LSR
read after it happens. The character in
the shift register is not transferred into
the FIFO, but is overwritten. This bit is
reset low when the CPU reads the LSR.
2 Parity Error
(PE) 0=No Error 1=Parity Error - the received character
does not have the correct parity as
configured via LCR bits 3 & 4. This bit is
set high on detection of a parity error and
reset low when the host CPU reads the
contents of the LSR. In the FIFO mode,
the parity error is associated with a
particular character in the FIFO (LSR Bit
2 reflects the error when the character is
at the top of the FIFO).

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LSR
Bit FUNCTION PROGRAMMING
3Framing
Error (FE) 0=No Error 1=Framing Error - Indicates that the
received character does not have a valid
stop bit (stop bit following last data bit or
parity bit detected as a zero/space bit).
This bit is reset low when the CPU reads
the contents of the LSR. In FIFO mode,
the framing error is associated with a
particular character in the FIFO (LSR
Bit 3 reflects the error when the
character is at the top of the FIFO).
4 Break
Interrupt
(BI)
0=No Break
1=Break - the received data input has been
held in the space (logic 0) state for more
than a full-word transmission time (start
bits + data + parity bit + stop bits).
Reset upon read of LSR. In FIFO mode,
this bit is associated with a particular
character in the FIFO and reflects the
Break Interrupt when the break character
is at the top of the FIFO. It is detected
by the host CPU during the first LSR
read. Only one “0” character is loaded
into the FIFO when BI occurs.
5 Transmitter
Holding
Register
Empty
(THRE)
0=Not Empty
1=Empty - indicates that the channel is
ready to accept a new character for
transmission. Set high when character
is transferred from the THR into the
transmitter shift register. Reset low by
loading the THR (It is not reset by a host
CPU read of the LSR). In FIFO mode,
this bit is set when the Tx FIFO is empty
and cleared when onebyte is written to
the Tx FIFO. When a Transmitter
Holding Register Empty interrupt is
enabled by IER bit 1, this signal causes
a priority 3 interrupt in the IIR. If the IIR
indicates that this signal is causing the
interrupt, the interrupt is cleared by a
read of the IIR.
6 Transmitter
Empty
(TEMT)
0=Not Empty
1=Transmitter Empty- set when both the
Transmitter Holding Register (THR) and
the Transmitter Shift Register (TSR) are
both empty. Reset low when a character
is loaded into the THR and remains low
until the character is transmitted (it is not
reset low by a read of the LSR). In FIFO
mode, this bit is set when both the
transmitter FIFO and shift register are
empty.
7 Receiver
FIFO Error 0=No Error in FIFO (it is always 0 in the 16C450 mode--FCR bit 0 low).
1=Error in FIFO - set when one of the
following data errors is present in the
FIFO: parity error, framing error, or break
interrupt indication. Cleared by a host
CPU read of the LSR if there are no
subsequent errors in the FIFO.
Note that LSR Bits 1-4 (OE, PE, FE, BI) are the error conditions
that produce a receiver-line-status interrupt (a priority 1 interrupt in
the IIR register when any one of these conditions are detected).
This interrupt is enabled by setting IER bit 2 to 1.
A power-up or system reset sets all LSR bits to 0, except bits 5
and 6 which are high.
LCR - Line Control Register, Ports A-D (Read/Write)
The individual bits of this register control the format of the data
character as follows:
Line Control Register
LCR
Bit FUNCTION PROGRAMMING
1
and
0
Word
Length
Select
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
2StopBit
Select 0=1 Stop Bit
1=1.5 Stop Bits if 5 data bits selected; 2
Stop Bits if 6, 7, or 8 data bits selected.
3Parity
Enable 0=Parity Disabled
1=Parity Enabled-A parity bit is generated
and checked for between the last data
word bit and the stop bit.
4Even-Parity
Select 0=Odd Parity
1=Even Parity
5 Stick Parity 0=Stick Parity Disabled
1=Stick Parity Enabled-When parity is
enabled, stick parity causes the
transmission and reception of a parity bit
to be in the opposite state from the value
selected via bit 4. This is used as a
diagnostic tool to force parity to a known
state and allow the receiver to check the
parity bit in a known state.
6 Break
Control 0= Break Disabled 1= Break Enabled-When break is enabled,
the serial output line (TxD) is forced to
the space state (low). This bit acts only
on the serial output and does not affect
transmitter logic. For example, if the
following sequence is used, no invalid
characters are transmitted due to the
presence of the break.
1. Load a zero byte in response to the
Transmitter Holding Register Empty
(THRE) status indication.
2. Set the break in response to the next
THRE status indication.
3. Wait for the transmitter to become idle
when the Transmitter Empty status
signal is set high (TEMT=1); then
clear the break when normal
transmission has to be restored.
7 Divisor
Latch
Access Bit
0=Access Receiver Buffer
1=Allow Access to Divisor Latches

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Note that bit 7 must be set high to access the divisor latch
registers DLL & DLM of the baud rate generator during a read/write
operation. Bit 7 must be low to access the receiver-buffer register
(RBR), the Transmitter-Holding Register (THR), or the Interrupt-
Enable Register (IER). A power-up or system reset sets all LCR
bits to 0.
A detailed discussion of word length, stop bits, parity, and the
break signal is included in Section 4.0, Theory of Operation.
SCR - Scratch Pad/Interrupt Pointer Register, Ports A-D (R/W)
This 8-bit read/write register has no effect on the operation of
either serial channel. It is provided as an aide to the programmer to
temporarily hold data. Alternately, if interrupt generation is desired,
then this port is used to store the interrupt vector for the port. In
response to an interrupt select cycle, the IP module will execute a
read of this register for the interrupting port (see Interrupt Generation
section for more details).
IP Identification PROM - (Read Only, 32 Odd-Byte Addresses)
Each IP module contains an identification (ID) PROM that
resides in the ID space per the IP module specification. This area of
memory contains 32 bytes of information at most. Both fixed and
variable information may be present within the ID PROM. Fixed
information includes the "IPAC" identifier, model number, and
manufacturer's identification codes. Variable information includes
unique information required for the module. The IP502 ID PROM
does not contain any variable (e.g. unique calibration) information.
ID PROM bytes are addressed using onlythe odd addresses in a 64
byte block (on the “Big Endian” VMEbus). Even addresses are used
on the “Little Endian” PC ISA bus. The IP502 ID PROM contents
are shown in Table 3.2. Note that the base-address for the IP
module ID space (see your carrier board instructions) must be
added to the addresses shown to properly access the ID PROM.
Execution of an ID PROM Read requires 1 wait state.
Table 3.2: IP502 ID Space Identification (ID) PROM
Hex Offset
From ID
PROM Base
Address
ASCII
Character
Equivalent
Numeric
Value
(Hex) Field Description
01 I 49 All IP's have 'IPAC'
03 P 50
05 A 41
07 C 43
09 A3 Acromag ID Code
0B 06 IP Model Code1
0D 00 Not Used
(Revision)
0F 00 Reserved
11 00 Not Used (Driver
ID Low Byte)
13 00 Not Used (Driver
ID High Byte)
15 0C Total Number of ID
PROM Bytes
17 65 CRC
19 to 3F yy Not Used
Notes (Table 3.2):
1. The IP model number is represented by a two-digit code within
the ID PROM (the IP502 model is represented by 06 Hex).
THE EFFECT OF RESET
A software or hardware reset puts the serial channels into an
idle-mode until initialization (programming). A reset initializes the
receiver and transmitter clock counters. It also clears the Line-
Status Register (LSR), except for the transmitter shift-register empty
(TEMT) and transmit holding-register empty (THRE) bits which are
set to 1 (note that when interrupts are subsequently enabled, an
interrupt will occur due to THRE being set). The Modem Control
Register (MCR) and the Transmitter Enable Always Register (TEA)
are also cleared. All of the discrete signal lines, memory elements,
and miscellaneous logic associated with these register bits are
cleared, de-asserted, or turned off. However, the Line Control
Register (LCR), divisor latches, Receiver Buffer Register (RBR),
and Transmitter Holding Register (THR) are not affected. The
following table summarizes the effect of a reset on the various
registers and internal and external signals:
The Effect of Reset
REGISTER/
SIGNAL RESET CONTROL STATE/EFFECT
REGISTERS:
IER Reset All Bits low (Bits 0-3 low,
Bits 4-7 permanently low)
IIR Reset Bit 0 high, Bits 1,2,3,6,7
low, Bits 4 & 5 permanently
low
LCR Reset All bits low
MCR Reset All bits low (bits 5-7
permanently low)
FCR Reset All bits low
LSR Reset All bits low, except bits 5 &
6 are high
MSR Reset Bits 0-3 low, bits 4-7 per
corresponding input signal
SIGNALS (INTERNAL & EXTERNAL):
TxD Reset High
Interrupt (RCVR
errors) Read LSR/ Reset Low
Interrupt (RCVR
data ready) Read RCVR Buffer Register/
Reset
Low
Interrupt
(THRE) Read IIR/Write THR/Reset Low
Interrupt
(Modem Status
Changes)
Read MSR/
Reset Low
RTS* Reset High
DTR* Reset High
OUT1* Reset High
OUT2* Reset High
IP502 PROGRAMMING
Each serial channel of this module is programmed by the control
registers: LCR, IER, DLL, DLM, MCR, and FCR. These control
words define the character length, number of stop bits, parity, baud
rate, and modem interface. The control registers can be written in
anyorder, but the IER register should bewritten last since it controls
the interrupt enables. The contents of these registers can be
updated any time when not transmitting or receiving data.

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The complete status of each channel can be read by the host
CPU at any time during operation. Two registers are used to report
the status of a particular channel: the Line Status Register (LSR)
and the Modem Status Register (MSR).
Serial channel data is read from the Receiver Buffer Register
(RBR), and written to the Transmitter Holding Register (THR).
Writing data to the THR initiates the parallel-to-serial transmitter shift
register to the TxD line. Likewise, input data is shifted from the RxD
pin to the Receiver Buffer Register. Note that control of the
transceiver for data transmission and data receiving is required via
the RTS and DTR control bits of the Modem control register.
The Scratchpad Register is used to store the interrupt vector for
the port. In response to an interrupt select cycle, the IP module will
provide a read of this port. As such, each port may have a unique
interrupt vector assigned. Interrupts are served in a shifting-priority
fashion as a function of the last interrupt serviced to prevent
continuous interrupts from a higher-priority interrupt channel from
freezing out service of a lower priority channel.
This board operates in two different modes. In one mode, this
device remains software compatible with the industry standard
16C450 familyof UART’s, and provides double-buffering of data
registers. In the FIFO Mode (enabled via bit 0 of the FCR register),
data registers are FIFO-buffered so that read and write operations
can be performed while the UART is performing serial-to-parallel
and parallel-to-serial conversions.
Two FIFO modes of operation are possible: FIFO Interrupt
Mode and FIFO Polled Mode. In FIFO Interrupt Mode, data transfer
is initiated by reaching a pre-determined trigger-level or generating
time-out conditions. In FIFO-Polled Mode, there is no time-out
condition indicated or trigger-level reached. The transmit and the
receive FIFO’s simply hold characters and the Line Status Register
must be read to determine the channel status.
Acromag provides an Industrial I/O Pack Software Library
diskette (Model IPSW-LIB-M03, MSDOS format) to simplify
communication with the board. Example software functions are
provided for both ISA bus (PC/AT) and VMEbus applications. All
functions are written in the “C” programming language and can be
linked to your application. For more details, refer to the
“README.TXT” file in the root directory on the diskette and the
“INFO502.TXT” file in the appropriate “IP502” subdirectory off of
“\VMEIP” or “\PCIP”, according toyour carrier.
FIFO Polled-Mode
Resetting Interrupt Enable Register Bit 0, Bit 1, Bit 2, Bit 3, or all
four to 0, with FIFO Control Register (FCR) Bit 0 =1, puts the
channel into the polled-mode of operation. The receiver and
transmitter are controlled separately and either one or both may be in
the polled mode. In FIFO-Polled Mode, there is no time-out
condition indicated or trigger-level reached, the transmit and the
receive FIFO’s simply hold characters and the Line Status Register
must be read to determine the channel status.
FIFO-Interrupt Mode
In FIFO Interrupt Mode, data transfer is initiated byreaching a
pre-determined trigger-level or generating a time-out condition.
Please note the following with respect to this mode of operation.
When the receiver FIFO and receiver interrupts are enabled, the
following receiver status conditions apply:
1. LSR Bit 0 is set to 1 when a character is transferred from the
shift register to the receiver FIFO. It is reset to 0 when the FIFO
is empty.
2. The receiver line-status interrupt (IIR=06) has a higher priority
than the received data-available interrupt (IIR=04).
3. The receive data-available interrupt is issued to the CPU when
the programmed trigger level is reached by the FIFO. It is
cleared when the FIFO drops below its programmed trigger
level. The receive data-available interrupt indication (IIR=04)
also occurs when the FIFO reaches its trigger level, and is
cleared when the FIFO drops below its trigger level.
When the receiver FIFO and receiver interrupts are enabled, the
following receiver FIFO character time-out status conditions apply:
1. A FIFO character time-out interrupt occurs if:
•A minimum of one character is in the FIFO.
•The last received serial character is longer than four
continuous prior character times ago (if 2 stop bits are
programmed, the second one is included in the time delay).
•The last CPU read of the FIFO is more than four
continuous character times earlier. At 300 baud, and with
12-bit characters, the FIFO time-out interrupt causes a
latency of 160ms maximum from received character to
interrupt issued.
2. From the clock signal input, the character times can be
calculated. The delay is proportional to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver
FIFO or after a new character is received when there has been
no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the
CPU reads a character from the receiver FIFO.
When the transmit FIFO and transmit interrupts are enabled
(FCR Bit 0 = 1 and IER=01), a transmitter interrupt will occur as
follows:
1. When the transmitter FIFO is empty, the transmitter holding
register interrupt (IIR=02) occurs. The interrupt is cleared when
the Transmitter Holding Register (THR) is written toor the
Interrupt Identification Register (IIR) is read. One to sixteen
characters can be written to the transmit FIFO when servicing
this interrupt.
2. The transmit FIFO empty indications are delayed one character
time minus the last stop bit time when the following occurs:
Bit 5 of the LSR (THRE) is 1 and there is not a minimum of two
bytes at the same time in the transmit FIFO since the last time
THRE=1. The first transmitter interrupt after changing FCR Bit
0 is immediate, assuming it is enabled.
The receiver FIFO trigger level and character time-out interrupts
have the same priority as the received data-available interrupt. The
Transmitter Holding-Register-Empty interrupt has the same priority
as the Transmitter FIFO-Empty interrupt.

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Interrupt Generation
This model provides individual control for generation of transmit,
receive, line status, and data set interrupts on each of four channels.
Each channel shares interrupt request line 0 (INTREQ0*) according
to a unique priority shifting scheme that prevents the continuous
interrupts of one channel from freezing out another channels’
interrupt requests.
After pulling the INTREQ0* line low and in response to an
Interrupt Select cycle, the current highest priority interrupt channel
will serve up its interrupt vector first. Interrupt serving priority will
shift as a function of the last port served. A unique interrupt vector
maybe assigned to each communication port and is loaded into the
Scratchpad Register (SCR) for the port. The IP module will thus
execute a read of the Scratchpad Register in response to an
interrupt select cycle. Two wait states are required to complete this
cycle.
Interrupt priority is assigned as follows. Initially, with no prior
interrupt history, Port A has the highest priority and will be served
first, followed by port B, followed by port C, then followed by port D.
However, if port A was the last interrupt serviced, then port B will
have the highest priority, followed by port C, followed by port D, then
port A, in a last-serviced last-out fashion. Priority continues to shift
in the same fashion if port B or port C was the last interrupt serviced.
This is useful in preventing continuous interrupts on one channel
from freezing out interrupt service for other channels.
Loopback Mode Operation
This device can be operated in a “loopback mode”, useful for
troubleshooting a serial channel without physically wiring to the
channel. Bit 4 of the Modem Control Register (MCR) is used to
program the local loopback feature for the UART channel. When
set high, the UART channel’s serial output line (Transmit Data Path)
is set to the marking (logic 1 state), and the UART receiver serial
data input lines are disconnected from the RxD receiver path. The
output of the UART transmitter shift register is then looped back into
the receiver shift register input. Thus, a write to the Transmitter
Holding Register is automatically looped back to the corresponding
Receiver Buffer Register. Additionally, the four modem control
inputs (CTS, DSR, DCD, and RI) aredisconnected from their
receiver input paths. With modem status interrupts enabled in the
Loopback Mode, theCTS*, DSR*, RI*, and DCD* inputs are
ignored. Instead, the four modem control outputs (DTR, RTS,
OUT1, and OUT2 of the MCR Register) are internally connected to
the corresponding four modem control inputs (monitored via the
Modem Status Register), while their associated pins are forced to
their high/ inactive state. Thus, in the loopback diagnostic mode,
transmitted data is immediately received permitting the host
processor to verify the transmit and receive data paths of the
selected serial channel. Further, modem status interrupt generation
is controlled manually in loopback mode by controlling the state of
the four lower order MCR bits internally, instead of by the external
hardware paths. However, in loopback mode, no interrupt requests
or interrupt vectors will actually be served, the UART onlyreflects
that an interrupt is pending.
Programming Example
The following example will demonstrate data transfer between
one channel of the IP502 and another node. Both nodes will use the
FIFO modeof operation with a FIFO threshold set at 14 bytes. The
data format will use 8-bit characters, odd-parity, and 1 stop bit.
Please refer to Table 3.1 for address locations. The “H” following
data below refers to the Hexadecimal data format.
1. Write 80H to the Line Control Register (LCR).
This sets the Divisor Latch Access bit to permit access to the
two divisor latch bytes used to set the baud rate. These bytes
share addresses with the Receive and Transmit buffers, and the
Interrupt Enable Register (IER).
2. Write 00H to the Divisor Latch MSB (DLM). Write 34H to the
Divisor Latch LSB (DLL).
This sets the divisor to 52 for 9600 baud (i.e. 9600 = 8MHz ÷
[16*52] ).
3. Write 0BH to the Line Control Register (LCR).
This first turns off the Divisor Latch Access bit to cause
accesses to the Receiver and Transmit buffers and the Interrupt
Enable Register. It also sets the word length to 8 bits, the
number of stop bits to one, and enables odd-parity.
4. (OPTIONAL) Write xxH to the Scratch Pad Register.
This has no effect on the operation, but is suggested to illustrate
that this register can be used as a 1-byte memory cell.
Alternately, the interrupt vector for the port may be written to this
register and a read will be executed on this register in response
to an interrupt select cycle.
5. Write 07H to the Interrupt Enable Register (IER).
This enables the receiver line status, received data available,
and transmit holding buffer empty interrupts. The line status
interrupt is used to signal error cases, such as parity or overrun
errors. The modem status interrupts are expected, but the line
status interrupts are not. The received data available and
transmit holding buffer empty aide control by the host CPU in
moving data back and forth.
6. Write C7H to the FIFO Control Register (FCR).
This enables and initializes the transmit and receive FIFO’s, and
sets the trigger level of the receive FIFO interrupt to 14 bytes.
7. Read C1H from the Interrupt Identification Register (IIR).
This is done to check that the device has been programmed
correctly. The upper nibble “C” indicates that the FIFO’s have
been enabled and the lower nibble “1” indicates that no
interrupts are pending.
8. Write 02H to the Modem Control Register (MCR).
This sets the Request-To-Send bit and asserts the RTS* signal
line. It is used to enable the transceiver for data output.

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9. The host should begin writing data repeatedly to the Transmitter
Holding Register.
This loads the transmit FIFO and initiates transmission of serial
data on the TxD line. The first serial byte will take about 100us
to transmit, so it is likely that the transmit FIFO will fill before the
first byte has been sent.
10. Stop loading the transmit buffer, then write 00H to the Modem
Control Register (MCR).
This clears the Request-To-Send bit and releases the RTS*
signal line, disabling the transceiver for data output.
11. Read data repeatedly from the Receiver Buffer Register.
Provided data has been received.
After 14 bytes have been received (or fewer bytes with a
timeout), an interrupt will be generated if the host CPU has not
unloaded the receive FIFO.
4.0 THEORY OF OPERATION
This section contains information regarding the EIA-485 serial
data interface. A description of the basic functionality of the circuitry
used on the board is also provided. Refer to the Block Diagram
shown in Drawing 4501-557 as you review this material.
EIA-RS485 SERIAL INTERFACE
The Electronic Industries Association (EIA) introduced EIA-
RS485 as a balanced (differential) serial data transmission interface
standard for the interchange of binary signals in multipoint
interconnection of digital equipments. Multiple generators and
receivers may be attached to a common interconnecting cable as
shown in Drawing 4501-558.
The EIA-RS485 interface specifies a balanced driver with
balanced receivers. Balanced data transmission refers to the fact
that two conductors are switched per signal and the logical state of
the data is referenced by the difference in potential between the two
conductors, not with respect to signal ground. The differential
method of data transmission makes EIA-RS485 ideal for noisy
environments since it minimizes the effects of coupled noise and
ground potential differences. That is, since these effects are seen
as common-mode voltages (common to both lines), not differential,
they are rejected by the receivers. Additionally, balanced drivers
have generally faster transition times and allow operation at higher
datarates over longer distances.
The EIA-RS485 standard defines a bi-directional, terminated,
multiple driver and multiple receiver configuration. Half-duplex
operation is provided by the sharing of a single data path for transmit
and receive. The maximum data transmission cable length is
generally limited to 4000 feet without a signal repeater installed.
EIA-RS485 is electrically similar to EIA/TIA-422B, except that
EIA/TIA-422B supports full-duplexed single driver multiple receiver
operation (see Acromag Model IP501).
With respect to EIA-485, logic states are represented by
differential voltages from 1.5 to 5V. The polarity of the differential
voltage determines the logical state. A logic is represented by a
negative differential voltage between the terminals (measured A to B,
or + to -). A logic 1 is represented by a positive differential voltage
between the terminals (measured A to B, or + to -). The line
receivers convert these signals to the conventional TTL level.
Start and stop bits are used to synchronize the receiver to the
asynchronous serial data of the transmitter. The transmit data line is
normally held in the mark state (logical 1). The transmission of a
data byte requires that a start bit (a logical 0 or a transition from
mark to space) be sent first. This tells the receiver that the next bit
is a data bit. The data bits are followed by a stop bit (a logical 1 or a
return to the mark state). The stop bit tells the receiver that a
complete byte has been received. Thus, 10 bits make up a data byte
if the data character is 8 bits long (and no parity is assumed). Nine
bits are required if only standard ASCII data is being transmitted (1
start bit + 7 data bits + 1 stop bit). The character size for this
module is programmable between 5 and 8 bits.
Parity is a method of judging the integrity of the data. Odd,
even, or no parity may be configured for this module. If parity is
selected, then the parity bit precedes transmission of the stop bit.
The parity bit is a 0 or 1 bit appended to the data to make the total
number of 1 bits in a byte even or odd. Parity is not normally used
with 8-bit data. Even parityspecifies that an even number of logical
1’s be transmitted. Thus, if the data byte has an odd number of 1’s,
then the parity bit is set to 1 to make the parity of the entire character
even. Likewise, if the transmitted data has an even number of 1’s,
then the parity bit is set to 0 tomaintain even parity. Odd parity
works the same way using an odd number of logical 1’s. Thus, both
the transmitter and receiver must have the same parity. If a byte is
received that has the wrong parity, an error is assumed and the
sending system is typically requested to retransmit the byte. Two
other parity formats not supported by this module are mark parity
and space parity. Mark parity specifies that the parity bit will always
be a logical 1, space parity requires the parity bit will always be 0.
The most common asynchronous serial data format is 1 start bit,
8 data bits, and 1 stop bit, with no parity. The following table
summarizes the available data formats:
START BIT Binary 0 (a shift from “Mark” to “Space”)
DATA BITS 5,6,7, or 8 Bits
PARITY Odd, Even, or None
STOP BIT Binary 1 (1, 1-1/2, or 2 Bit times)
With start, stop, and parity in mind, for an asynchronous data
byte, note that at least one bit will be a 1 (the stop bit). This defines
the break signal (all 0 bits with a 1 stop bit lasting longer than one
character). A break signal is a transfer from “mark” to “space” that
lasts longer than the time it takes to transfer one character.
Because the break signal doesn’t contain any logical 1’s, it cannot be
mistaken for data. Typically, whenever a break signal is detected,
the receiver will interpret whatever follows as a command rather than
data. The break signal is used whenever normal signal processing
must be interrupted. In the case of a modem, it will usuallyprecede
a modem control command. Do not confuse the break signal with
the ASCII Null character, since a break signal is longer than one
character time. That is, it is any “space” condition on the line that
lasts longer than a single character (including its framing bits) and is
usually 1-1/2 to 2 character times long.

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The baud rate is a unit of transmission speed equal to the
number of electrical signals (signal level changes) sent on a line in
one second. It is thus, the electrical signaling rate or frequency at
which electrical impulses are transmitted on a communication line.
The baud rate is commonly confused with the bit transfer rate (bits-
per-second), but baud rate does not equate to the number of bits
transmitted per second unless one bit is sent per electrical signal.
However, one electrical signal (change in signal level) maycontain
more than one bit (as is the case with most phone modems). While
bits-per-second (bps) refers to the actual number of bits transmitted
in one second, the baud rate refers to the number of signal level
changes that may occur in one second. Thus, 2400 baud does not
equal 2400 bits per second unless 1 bit is sent per electrical signal.
Likewise, a 1200bps or 2400bps modem operates at a signaling rate
of only 600 baud since they encode 2 and 4 bits, respectively, in one
electrical impulse (through amplitude, phase, and frequency
modulation techniques). However, for this device, the baud rate is
considered equivalent to the bit rate.
The IP502 model uses a single differential data path for
Transmit and Receive, providing half-duplex communication. No
handshake signals are supported.
Pins 1-18 and pins 26-43 of the field I/O connector P2 provides
connectivity to serial Ports A-D of this module (Refer to Table 2.1 for
pin assignments). Note that a suffix of ‘_A’, ‘_B’, ‘_C’, or ‘_D’ is
appended to the signal names to indicate their port association.
These signals are described in Table 2.2.
Note that not all UART signal paths are used by this model and
their corresponding UART pins are tied high (+5V). This includes,
CTS (Clear To Send), RI (Ring Indicator), DSR (Data Set Ready),
and DCD (Data Carrier Detect). In addition, the UART DTR (Data
Terminal Ready) signal path is used to control the receiver enables
for the port and the RTS signal is used to control the transmitter
enables for the port.
IP502 OPERATION
Connection to each serial port is provided through connector P2
(refer to Table 2.1). These pins are tied to the inputs and outputs of
EIA RS-485 line transceivers. Signals received are converted from
the required EIA RS-485 voltages signals to the TTL levels required
by the UART (Universal Asynchronous Receiver/Transmitter).
Likewise TTL signals from the UART are converted to the EIA RS-
485 voltages for data transmission. The UART provides the
necessary conversion from serial-to-parallel (receive) and parallel-to-
serial (transmit) for interfacing to the data bus. Additionally, it
provides data buffering and data formatting capabilities. A
programmable logic device is used to control the interface between
the UART, the IP bus, the line drivers and receivers, and the
IDPROM.
Note that the field serial interface to the carrier board provided
through connector P2 (refer to Table 2.1) is NON-ISOLATED. This
means that the field signal return and logic common have a direct
electrical connection to each other. As such, care must be taken to
avoid ground loops (see Section 2 for connection
recommendations). Ignoring this effect may cause operation errors,
and with extreme abuse, possible circuit damage. Refer to Drawing
4501-556 for example communication wiring and grounding
connections.
LOGIC/POWER INTERFACE
The logic interface to the carrier board is made through
connector P1 (refer to Table 2.3). Not all of the IP logic P1 pin
functions are used. P1 also provides +5V power the module (±12V
is not used).
A programmable logic device installed on the IP Module
provides the control signals required to operate the board. It
decodes the selected addresses in the I/O and ID spaces and
produces the chip selects, control signals, and timing required by
the communication registers and ID PROM, as well as, the
acknowledgment signal required by the carrier board per the IP
specification. It also prioritizes the interrupt requests coming from
the serial ports in a shifting priority fashion, based on the last
interrupt serviced.
The ID PROM (read only) registers of the IP’s Programmable
Logic Device module provides the identification for the individual
module per the IP specification. The ID PROM, configuration
control registers, and FIFO buffers are all accessed through an 8-bit
data bus interface to the carrier board.
5.0 SERVICE AND REPAIR
SERVICE AND REPAIR ASSISTANCE
Surface-Mounted Technology (SMT) boards are generally
difficult to repair. It is highly recommended that a non-functioning
board be returned to Acromag for repair. The board can be easily
damaged unless special SMT repair and service tools are used.
Further, Acromag has automated test equipment that thoroughly
checks the performance of each board. When a board is first
produced and when any repair is made, it is tested, placed in a burn-
in room at elevated temperature, and retested before shipment.
Please refer to Acromag's Service Policy Bulletin or contact
Acromag for complete details on how to obtain parts and repair.
PRELIMINARY SERVICE PROCEDURE
Before beginning repair, be sure that all of the procedures in
Section 2, Preparation For Use, have been followed. Also, refer to
the documentation of your carrier board to verify that it is correctly
configured. Replacement of the module with one that is known to
work correctly is a good technique to isolate a faultymodule.
CAUTION: POWER MUST BE TURNED OFF BEFORE
REMOVING OR INSERTING BOARDS
Acromag’s Applications Engineers can provide further technical
assistance if required. When needed, complete repair services are
also available from Acromag.

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6.0 SPECIFICATIONS
GENERAL SPECIFICATIONS
UART.....................................Texas Instruments TL16C554FN
Operating Temperature..........0 to +70°C.
Relative Humidity. ..................5-95% non-condensing.
Storage Temperature. ............-40°C to +125°C.
Physical Configuration............Single Industrial I/O Pack Module.
Length....................................3.880 inches (98.5 mm).
Width.......................................1.780 inches (45.2 mm).
Board Thickness.....................0.062 inches (1.59 mm).
Max Component Height...........0.314 inches (7.97 mm).
Connectors:
P1 (IP Logic Interface)............50-pin female receptacle header
(AMP 173279-3 or equivalent).
P2 (Field I/O)..........................50-pin female receptacle header
(AMP 173279-3 or equivalent).
Power:
+5 Volts (±5%)........................170mA, Typical with transmitter
terminating resistors removed;
380mA, Typical with all Termination &
Bias Resistors installed; 425mA,
Maximum.
+12 Volts (±5%) from P1.........0mA (Not Used).
-12 Volts (±5%) from P1..........0mA (Not Used).
Non-Isolated............................Logic and field commons have a
direct electrical connection.
Resistance to RFI...................No data upsets occur for field
strengths up to 10V per meter at
27MHz, 151MHz, & 460MHz per
SAMA PMC 33.1 test procedures.
Resistance to EMI..................Unit has been tested with no data
upsets under the influence of EMI
from switching solenoids, commutator
motors, and drill motors.
ESD Protection.......................EIA RS-485 lines are protected from
ESD voltages to ≥±10KV
EIA RS-485 PORTS
Configuration..........................Four independent, non-isolated, EIA
RS-485 serial ports with a common
signal return connection.
Data Rate................................Programmable to 512K bits/sec using
internal baud rate generator and
carrier 8MHz clock. Maximum 1M
bits/sec with optional 16MHz crystal
oscillator.
Interface..................................Asynchronous serial only.
Maximum Cable Length...........1200M (4000 feet) typical. Use of
signal repeater can extend
transmission distances beyond this
limit.
Character Size........................Software programmable 5-8 bits.
Parity.......................................Software Programmable odd, even,
or no parity.
Stop Bits.................................Software programmable 1, 1-1/2, or 2
bits.
Data Register Buffers ............ The data registers are double-
buffered (16C450 mode), or 16-byte
FIFO buffered (FIFO mode).
Interrupts............................... Receiver Line Status Interrupt (i.e.
Overrun error, Parity error, Framing
error, or Break Interrupt); Received
Data Available (FIFO level reached)
or Character Time-Out; Transmitter
Holding Register Empty. Multiple port
Interrupts share the INTREQ0* line
according to a shifting-priority scheme
based on the last interrupting port
serviced.
Transceiver:
Termination Resistors............ 120ΩTermination Resistors Installed
in sockets on board at network ends
only (see Drawing 4501-559 for
location).
Bias Resistors........................560Ωpullup to +5V on (+) output
lines, 560Ωpull-down to COM on (-)
lines, installed in sockets on board.
Only one set per line pair (see
Drawing 4501-559 for location).
Transceiver............................ Linear Technology LTC1481,
designed for EIA/TIA-422B or EIA
RS485 applications.
Differential Output Voltage .....5V Maximum (Unloaded); 2V
Minimum (EIA/TIA-422B, 50Ωload);
1.5V Minimum (EIA-485, 27Ωload).
Common Mode Output Voltage. 3V Maximum
Output Short Circuit Current ...250mA Maximum
Rise or Fall Time. ..................10ns Minimum, 30ns Typical,
60ns Maximum (RDIFF = 54Ω,
CL =100pF).
High-Z State Output Current.. .±1uA Maximum.
Differential Input Threshold.... -0.2V Minimum to +0.2V Maximum.
Input Hysteresis..................... 45mV (VCM=0V).
Input Resistance.................... 12KΩ
INDUSTRIAL I/O PACK COMPLIANCE
Specification.......................... .This module meets or exceeds all
written Industrial I/O Pack
specifications per revision 0.7.1.
Electrical/Mech. Interface ......Single-Size IP Module.
IP Data Transfer Cycle Types Supported:
Input/Output (IOSel*)............. .D16 or D08 Least Significant Byte
read/write of data.
ID Read (IDSel*).................... 32 x 8 ID PROM read on D0..D7.
Interrupt Select (INTSel*)........8-bits (D08) read of Scratch Pad/
Interrupt Vector Register contents.
Access Times (8MHz Clock):
ID PROM Read...................... 1 wait state (375ns cycle).
Channel Register Read.......... 2 wait states (500ns cycle).
Channel Register Write.......... 2 wait states (500ns cycle).
Interrupt Select Read............. 2 wait states (500ns cycle).

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APPENDIX
CABLE: MODEL 5025-550-x (Non-Shielded)
MODEL 5025-551-x (Shielded)
Type: Flat Ribbon Cable, 50-wires (female connectors at both
ends). The ‘-x’ suffix designates the length in feet (12 feet
maximum). Choose shielded or unshielded cable according to
model number. The unshielded cable is recommended for
digital I/O, while the shielded cable is recommended for
optimum performance with precision analog I/O applications.
Application: Used to connect a Model 5025-552 termination panel to
the AVME9630/9660 non-intelligent carrier board A-D
connectors (both have 50-pin connectors).
Length: Last field of part number designates length in feet (user-
specified, 12 feet maximum). It is recommended that this length
be kept to a minimum to reduce noise and power loss.
Cable: 50-wire flat ribbon cable, 28 gage. Non-Shielded cable
model uses Acromag Part 2002-211 (3M Type C3365/50 or
equivalent). Shielded cable model uses Acromag Part 2002-261
(3M Type 3476/50 or equivalent).
Headers (Both Ends): 50-pin female header with strain relief.
Header - Acromag Part 1004-512 (3M Type 3425-6600 or
equivalent). Strain Relief - Acromag Part 1004-534 (3M Type
3448-3050 or equivalent).
Keying: Headers at both ends have polarizing key to prevent
improper installation.
Schematic and Physical Attributes: For Non-Shielded cable model,
see Drawing 4501-462. For Shielded cable model, see Drawing
4501-463.
Shipping Weight: 1.0 pound (0.5Kg) packaged.
CABLE: MODEL 5029-943
Type: Model 5029-943 IP500 Communication Cable: A five foot
long, flat 50-pin cable with a female connector on one end (for
connection to AVME9630/9660 or other compatible carrier
boards) and four DE-9P connectors (serial ports) on the other
end.
Application: Used to connect up to four DB-9 serial ports to
AVME9630/9660 non-intelligent carrier board A-D connectors.
It is used primarily with Acromag Model IP500, IP501, & IP502
serial communication modules.
Length: 5 feet.
Cable: 50-wire flat ribbon cable, 28 gage. Non-Shielded cable model
uses Acromag Part 2002-211 (3M Type C3365/50 or
equivalent).
Headers: 50-pin female header with strain relief. Header - Acromag
Part 1004-512 (3M Type 3425-6600 or equivalent). Strain Relief
-Acromag Part 1004-534 (3M Type 3448-3050 or equivalent).
Port Connectors: Four DE-9P (9-pin, D-SUB, Male) connectors with
strain relief (3M connector U89809-9000 with 3448-8D09A
strain relief, or equivalent).
Keying: 50-pin Header at one end has polarizing key to prevent
improper installation.
Schematic and Physical Attributes: See Drawing 4501-556.
Shipping Weight: 1.0 pound (0.5Kg) packaged.
CABLE: MODEL 5029-900
Type: Model 5029-900 APC8600 High-Density Cable: A 36-inch
long interface cable that mates the high-density (25mil pitch) 50-
pin I/O connectors of the APC8600 PC/AT ISA bus carrier
board, to the high density connectors on the APC8600
Termination Panels (described below).
Application: Used with the APC8600 PC carrier and termination
panel. It mates the high-density (25mil pitch) 50-pin I/O
connectors of the APC8600 PC/AT ISA bus carrier board, to the
high density connectors on the APC8600 Termination Panel
(described below).
Length: 36-inches
Cable: 50-wire flat ribbon cable, 28 gage, Non-Shielded,
T&B/Ansley Part 135-050 or equivalent.
Headers: 50-pin, high-density, 25-mil pitch, female header. Header-
T&B Ansley Part 311-050302 or equivalent.
Keying: Headers at both ends have polarizing key to prevent
improper installation.
Shipping Weight: 1.0 pound (0.5Kg) packaged.
TERMINATION PANEL: MODEL 5025-552
Type: Termination Panel For AVME9630/9660 Boards
Application: To connect field I/O signals to the Industrial I/O
Pack (IP). Termination Panel: Acromag Part 4001-040
(Phoenix Contact Type FLKM 50). The 5025-552 termination
panel facilitates the connection of up to 50 field I/O signals and
connects to the AVME9630/9660 3U/6U non-intelligent carrier
boards (A-D connectors only) via a flat ribbon cable (Model
5025-550-x or 5025-551-x). The A-D connectors on the carrier
board connect the field I/O signals to the P2 connector on each
of the Industrial I/O Pack modules. Field signals are accessed
via screw terminal strips. The terminal strip markings on the
termination panel (1-50) correspond to P2 (pins 1-50) on the
Industrial I/O Pack (IP). Each Industrial I/O Pack (IP) has its
own unique P2 pin assignments. Refer to the IP module manual
for correct wiring connections to the termination panel.
Schematic and Physical Attributes: See Drawing 4501-464.
Field Wiring: 50-position terminal blocks with screw clamps. Wire
range 12 to 26 AWG.
Connections to AVME9630/9660: P1, 50-pin male header with
strain relief ejectors. Use Acromag 5025-550-x or 5025-551-x
cable to connect panel to VME board. Keep cable as short as
possible to reduce noise and power loss.
Mounting: Termination panel is snapped on the DIN mounting rail.
Printed Circuit Board: Military grade FR-4 epoxy glass circuit board,
0.063 inches thick.
Operating Temperature: -40°C to +100°C.
Storage Temperature: -40°C to +100°C.
Shipping Weight: 1.25 pounds (0.6kg) packaged.

SERIES IP502 INDUSTRIAL I/O PACK QUAD EIA RS-485 SERIAL COMMUNICATION MODULE
___________________________________________________________________________________________
- 19 -
TERMINATION PANEL: MODEL 5029-910
Type: Screw-Terminal Termination Panel For Acromag APC8600
PC/AT ISA bus Carrier Boards.
Application: This panel converts the high-density ribbon-cable
connectors coming from the APC8600 carrier board (Acromag
cable Model 5029-900) to screw terminals, for direct-wired
interfaces. This panel facilitates the connection of up to 50 field
I/O signals and connects to the APC8600 PC/AT ISA bus
carrier board via high-density (25-mil pitch) flat ribbon cable and
connectors (see cable Model 5029-900). The A & B connectors
on the carrier board connect the field I/O signals to the P2
connector on each of the Industrial I/O Pack modules. Field
signals are accessed via screw terminal strips. Each Industrial
I/O Pack (IP) has its own unique P2 pin assignments. Refer to
the IP module manual for correct wiring connections to the
termination panel.
Field Wiring: 50-position terminal blocks with screw clamps. Wire
range 12 to 26 AWG.
Connections to APC8600: P1, 50-pin, high-density male header
with strain relief.
Mounting: Termination Panel includes mounting holes.
Printed Circuit Board: Military grade FR-4 epoxy glass circuit board,
0.063 inches thick.
Operating Temperature: -40°C to +85°C.
Storage Temperature: -55°C to +125°C.
Shipping Weight: 1.25 pounds (0.6kg) packaged.
TRANSITION MODULE: MODEL TRANS-GP
Type: Transition module for AVME9630/9660 boards.
Application: To repeat field I/O signals of IP modules A through D
for rear exit from VME card cages. This module is available for
use in card cages which provide rear exit for I/O connections via
transition modules (transition modules can onlybe used in card
cages specifically designed for them). It is a double-height
(6U), single-slot module with front panel hardware adhering to
the VMEbus mechanical dimensions, except for shorter printed
circuit board depth. Connects to Acromag termination panel
5025-552 from the rear of the card cage, and to
AVME9630/9660 boards within card cage, via flat 50-pin ribbon
cable (cable Model 5025-550-X or 5025-551-X).
Schematic and Physical Attributes: See Drawing 4501-465.
Field Wiring: 100-pin header (male) connectors (3M 3433-D303 or
equivalent) employing long ejector latches and 30 micron gold in
the mating area (per MIL-G-45204, Type II, Grade C).
Connects to Acromag termination panel 5025-552 from the rear
of the card cage via flat 50-pin ribbon cable (cable Model
5025-550-X or 5025-551-X).
Connections to AVME9630/9660: 50-pin header (male) connectors
(3M 3433-1302 or equivalent) employing long ejector latches
and 30 micron gold in the mating area (per MIL-G-45204, Type
II, Grade C). Connects to AVME9630/9660 boards within the
card cage via flat 50-pin ribbon cable (cable Model 5025-550-X
or 5025-551-X).
Mounting: Transition module is inserted into a 6U-size, single-width
slot at the rear of the VMEbus card cage.
Printed Circuit Board: Six-layer, military-grade FR-4 epoxyglass
circuit board, 0.063 inches thick.
Operating Temperature: -40°C to +85°C.
Storage Temperature: -55°C to +105°C.
Shipping Weight: 1.25 pounds (0.6Kg) packaged.