Acromag AcroPack AP513 User manual

AP513 AcroPack
Isolated RS-232 Serial Communication Module
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
Wixom, MI 48393-2417 U.S.A.
Tel: [phone]
Email: [email protected]
Copyright 2019, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8501146B

AP513 ACROPACK
USER’S MANUAL
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Table of Contents
1.0 GENERAL INFORMATION............................................................................................5
1.1 Intended Audience .......................................................................................................5
1.2 Preface.........................................................................................................................5
1.2.1 Trademark, Trade Name and Copyright Information .................................................................. 5
1.2.2 Class A Product Warning............................................................................................................. 5
1.2.3 Environmental Protection Statement ......................................................................................... 5
1.3 AcroPack Information –All Models ...............................................................................6
Figure 1.1 - AP513 Block Diagram ................................................................................................. 6
1.3.1 Ordering Information ................................................................................................................. 6
Table 1.1 Ordering Options ........................................................................................................... 6
1.3.2Key Features ............................................................................................................................... 6
1.3.3 Key Features PCIe Interface ........................................................................................................ 7
1.4 Signal Interface Products ..............................................................................................7
1.5 Software Support .........................................................................................................8
Windows............................................................................................................................................ 8
VxWorks............................................................................................................................................ 8
Linux.................................................................................................................................................. 8
1.6 References ...................................................................................................................8
2.0 PREPARATION FOR USE..............................................................................................9
2.1 Unpacking and Inspecting.............................................................................................9
2.2 Installation Considerations .........................................................................................10
2.3 Board Configuration ...................................................................................................10
2.4 Field I/O Connector ....................................................................................................10
Table 2.1 Field I/O Connector Pin Assignments .......................................................................... 11
2.5 Isolation .....................................................................................................................14
2.6 Logic Interface Connector ...........................................................................................14
Table 2.2 Logic Interface Connections......................................................................................... 14

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3.0 PROGRAMMING INFORMATION........................................................................... 16
3.1 PCIe Configuration Registers.......................................................................................16
Table 3.1 PCI Configuration Registers ......................................................................................... 17
3.2 UART and Device Configuration Registers ...................................................................17
Table 3.2 UART and Device Configuration Registers ................................................................... 18
Table 3.3 Device Configuration Registers in Byte Alignment ...................................................... 18
Table 3.4 Device Configuration Registers in DWORD Alignment ................................................ 19
3.2.1 The Global Interrupt Registers –INT0, INT1, INT2 and INT3.......................................................19
Table 3.5 UART Channel Interrupt Source Encoding ................................................................... 20
3.2.1.1 Interrupt Clearing .......................................................................................................... 20
3.2.2 General Purpose 16-bit Timer/Counter [TimerMSB, TimerLSB, TIMER, TIMECNTL] ...................21
3.2.2.1 TIMERMSB[31:24] and TIMERLSB[23:16] ...................................................................... 21
3.2.2.2 TIMERCNTL[7:0] Register............................................................................................... 21
Table 3.6 Timer Control Register................................................................................................. 21
3.2.2.3 Timer Operation ............................................................................................................ 22
3.2.3 8XMODE[7:0] (default 0x00)......................................................................................................23
3.2.4 4XMODE[15:8] (default 0x00) ....................................................................................................23
3.2.5RESET[23:16] (default 0x00).......................................................................................................23
3.2.6SLEEP[31:24] (default 0x00) .......................................................................................................24
3.2.7DVID[15:8].................................................................................................................................24
3.2.8DREV[7:0] ..................................................................................................................................24
3.2.9REGB[23:16] (default 0x00)........................................................................................................24
Table 3.7 REGB Register .............................................................................................................. 24
3.2.10 MPIO Registers ........................................................................................................................25
3.3 Transmit and Receive Data .........................................................................................25
3.3.1 FIFO Data Loading and Unloading in 32-bit Format....................................................................26
3.3.2 FIFO Data Loading/Unloading Through the UART Channel Registers, THR and RHR, in 8-Bit
Format .................................................................................................................................................26
3.4 UART Channel Configuration Registers........................................................................27
Table 3.8 UART Channel Configuration Registers........................................................................ 27
3.4.1 Receiver.....................................................................................................................................28
3.4.2 Transmitter................................................................................................................................28
3.4.2.1 Transmit Holding Register (THR).................................................................................... 28
3.4.2.2 Transmitter Operation in non-FIFO mode ..................................................................... 28
3.4.2.3 Transmitter Operation in FIFO mode............................................................................. 29
3.4.3 Baud Rate Generator Divisors (DLM, DLL and DLD)....................................................................29
3.4.3.1 DLM[7:0], DLL[7:0] and DLD[3:0] ................................................................................... 29
Table 3.9 Typical Data Rates with Internal 125MHz Clock at 16X Sampling ............................... 30
3.4.3.2 DLD[7:4] ......................................................................................................................... 30
Table 3.10 DLD Register[7:4] ....................................................................................................... 30
3.4.4 Interrupt Enable Register (IER) –Read/Write ............................................................................31

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3.4.4.1 IER versus Receive FIFO Interrupt Mode Operation ...................................................... 31
3.4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation........................................... 31
Table 3.11 Interrupt Enable Register........................................................................................... 31
3.4.5 Interrupt Status Register (ISR) –Read Only ...............................................................................33
3.4.5.1 Interrupt Generation ..................................................................................................... 34
3.4.5.2 Interrupt Clearing .......................................................................................................... 34
Table 3.12 Interrupt Source and Priority Level............................................................................ 34
3.4.6 FIFO Control Register (FCR) –Write Only ...................................................................................35
Table 3.13 FIFO Control Register................................................................................................. 35
Table 3.14 Transmit and Receive FIFO Trigger Table and Level Selection................................... 36
3.4.7 Line Control Register (LCR) –Read/Write ..................................................................................37
Table 3.15 Line Control Register.................................................................................................. 37
3.4.8 Modem Control Register (MCR) –Read/Write...........................................................................38
Table 3.16 Modem Control Register............................................................................................ 38
3.4.9 Line Status Register (LSR) –Read Only.......................................................................................39
Table 3.17 Line Status Register.................................................................................................... 40
3.4.10 Modem Status Register (MSR) –Read Only .............................................................................41
Table 3.18 Modem Status Register.............................................................................................. 41
3.4.11 Modem Status Register (MSR) –Write Only ............................................................................42
Table 3.19 Modem Status Register.............................................................................................. 42
3.4.12 Scratch Pad (SCR) –Read/Write...............................................................................................44
3.4.13 Feature Control Register (FCTR) –Read/Write.........................................................................44
Table 3.20 FCTR –Feature Control Register ................................................................................ 44
3.4.14 Enhanced Feature Register (EFR) –Read/Write .......................................................................45
Table 3.21 EFR - Enhanced Feature Register ............................................................................... 45
3.4.15 Transmit FIFO Level Counter –Read Only ................................................................................47
3.4.16 Transmit FIFO Trigger Level –Write Only.................................................................................47
3.4.17 Receive FIFO Level Counter –Read Only..................................................................................47
3.4.18 Receive FIFO Trigger Level –Write Only...................................................................................47
3.4.19 XOFF1, XOFF2, XON1 and XON2 Registers –Write Only...........................................................47
3.4.20 XCHAR Register –Read Only....................................................................................................47
Table 3.22 XCHAR Register .......................................................................................................... 47
4.0 SERVICE AND REPAIR ............................................................................................... 49
4.1 Service and Repair Assistance .....................................................................................49
4.2 Preliminary Service Procedure ....................................................................................49
4.3 Where to Get Help......................................................................................................49
5.0 SPECIFICATIONS......................................................................................................... 50
5.1 Physical ......................................................................................................................50

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5.2 Power Requirements ..................................................................................................50
Table 5.1 Power Requirements ................................................................................................... 50
5.3 Environmental Considerations ....................................................................................50
5.3.1 Operating Temperature.............................................................................................................50
5.3.2 Other Environmental Requirements ..........................................................................................51
5.3.2.1 Relative Humidity .......................................................................................................... 51
5.3.2.2 Isolation ......................................................................................................................... 51
5.3.3Vibration and Shock Standards..................................................................................................51
5.3.4EMC Directives ..........................................................................................................................51
5.4 Reliability Prediction ..................................................................................................51
Table 5.4 MTBF............................................................................................................................ 51
5.5 PCIe Bus Specifications ...............................................................................................52
APPENDIX A .......................................................................................................................... 53
AP-CC-01 Heatsink Kit Installation......................................................................................53
CERTIFICATE OF VOLATILITY ........................................................................................ 56
REVISION HISTORY ............................................................................................................ 57

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1.0 GENERAL INFORMATION
1.1 Intended Audience
This user's manual was written for technically qualified personnel who will
be working with I/O devices using the AcroPack module. It is not intended
for a general, non-technical audience that is unfamiliar with AcroPack
devices and their application.
1.2 Preface
The information contained in this manual is subject to change without
notice, and Acromag, Inc. (Acromag) does not guarantee its accuracy.
Acromag makes no warranty of any kind with regard to this material,
including, but not limited to, the implied warranties of merchantability and
fitness for a particular purpose. Further, Acromag assumes no responsibility
for any errors that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual. No part
of this manual may be copied or reproduced in any form, without the prior
written consent of Acromag.
1.2.1 Trademark, Trade Name and Copyright Information
© 2019 by Acromag Incorporated.
All rights reserved. Acromag and Xembedded are registered trademarks of
Acromag Incorporated. All other trademarks, registered trademarks, trade
names, and service marks are the property of their respective owners.
1.2.2 Class A Product Warning
This is a Class A product. In a domestic environment this product may cause
radio interference, in which case the user may find it necessary to take
adequate corrective measures.
1.2.3 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection
requirements where possible. Many components used (structural parts,
circuit boards, connectors, etc.) are capable of being recycled. Final
disposition of this product after its service life must be conducted in
accordance with applicable country, state, or local laws or regulations.

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1.3 AcroPack Information –All Models
The AcroPack IO modules are based on the PCI Express Mini Card
Electromechanical specification and are 70mm in length with an additional
100 pin field I/O connector.
The AcroPack is 19.05mm longer than the full length mini PCIe card at
50.95mm. It has the same mPCIe board width of 30mm and uses the same
mPCIe standard board hold down standoff and screw keep out areas.
The AP513 uses the 16550-compatible Exar 17v354 UART and contains four
isolated RS-232 serial communication ports that provide EIA/TIA-232-F
modem line support, including RTS and CTS. Each port has 250V of isolation
from digital circuitry and 100V of isolation from the other 3 ports.
Figure 1.1 - AP513 Block Diagram
1.3.1 Ordering Information
The AcroPack ordering options are given in the following table.
Table 1.1 Ordering Options
Model Number
#/Type of
Serial Ports
Operational Temperature
Range
AP513E-LF1,2
4x RS-232
-40oC to 85°C1,2
Note 1: For all models listed - all standoffs and screws required for an air cooled
application are provided with the carrier.
Note 2: A conduction cooled application will require purchase of AcroPack
Accessory AP-CC-01 (Conduction Cool Kit).
1.3.2 Key Features
•High Density –Provides 4 serial ports on each module.
•Isolation –Each port has 250V of isolation from digital circuitry and
100V of isolation from the other 3 ports.
•Internal Isolated Power –Isolated power is created onboard using
Analog Devices LTM2882 Dual Isolated RS232 µModule Transceiver +
Power, so isolated power does not need to be supplied externally.
•16550 compatible –Exar Quad UART with 16550-compatible
register set.

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•256-Byte FIFO Buffers –256-byte TX and RX FIFOs with
programmable trigger levels.
•Programmable Baud Rate –Each individual channel has its own
programmable baud rate generator with fractional divisor. While the
UART supports data rates up to 25Mbps, the serial transceivers only
support data rates up to 1Mbps.
•Interrupt Support –Individually controlled transmit, receive, line
status, and data set interrupts may be generated.
•General Purpose Timer/Counter –This 16-bit timer/counter uses an
internal 125MHz clock as the clock source and can be set to be a
single-shot or re-triggerable and can generate an interrupt.
1.3.3 Key Features PCIe Interface
•PCIe Bus –The AP module includes a PCI Express Generation 1
interface operating at a bus speed of 2.5 Gbps with one lane in each
direction.
•Compatibility –PCI Express Base Specification v2.0 compliant PCI
Express Endpoint.
1.4 Signal Interface Products
This AcroPack module will mate directly to all Acromag AP carriers. Once
connected, the module is accessed via a front panel connector.
The cables and termination panels are also available. For optimum
performance with the AP513 communication module, use of the shortest
possible length of shielded I/O cable is recommended.

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1.5 Software Support
The AcroPack series products require support drivers specific to your
operating system. Supported operating systems include: Linux, Windows,
and VxWorks.
Windows
Acromag provides software products (sold separately) to facilitate the
development of Windowsapplications interfacing with AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. This software (model APSW-
API-WIN) consists of low-level drivers and Dynamic Link Libraries (DLLs) that
are compatible with a number of programming environments. The DLL
functions provide a high-level interface to boards eliminating the need to
perform low-level reads/writes of registers, and the writing of interrupt
handlers.
VxWorks
Acromag provides a software product (sold separately) consisting of
VxWorkssoftware. This software (Model APSW-API-VXW) is composed of
VxWorks(real time operating system) libraries for all AcroPack modules,
VPX I/O board products, and PCIe I/O Cards. The software is implemented
as a library of “C” functions which link with existing user code to make
possible simple control of all Acromag AcroPack modules.
Linux
Acromag provides a software product consisting of Linuxsoftware. This
software (Model APSW-API-LNX) is composed of Linuxlibraries for all
AcroPack modules, VPX I/O board products, and PCIe I/O Cards. The
software is implemented as a library of “C” functions which link with existing
user code to make possible simple control of all Acromag AcroPack modules.
1.6 References
The following resources regarding AcroPack modules are available for
download on Acromag’s website or by contacting your sales representative.
•PCI Express MINI Card Electromechanical Specification, REV 1.2
http://www.pcisig.com
•Exar 17v354 High Performance Quad PCI Express UART datasheet

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2.0 PREPARATION FOR USE
IMPORTANT PERSONAL AND PRODUCT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible safety implications
of power, wiring, component, sensor, or software failures in designing any
type of control or monitoring system. This is especially important where
personal injury or the loss of economic property or human life is possible. It
is important that the user employ satisfactory overall system design. It is
understood and agreed by the Buyer and Acromag that this is the Buyer's
responsibility.
WARNING: This board utilizes static sensitive components and should only
be handled at a static-safe workstation. This product is an electrostatic
sensitive device and is packaged accordingly. Do not open or handle this
product except at an electrostatic-free workstation. Additionally, do not
ship or store this product near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its
original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the Acromag Limited Warranty.
2.1 Unpacking and Inspecting
Upon receipt of this product, inspect the shipping carton for evidence of
mishandling during transit. If the shipping carton is badly damaged or water
stained, request that the carrier's agent be present when the carton is
opened. If the carrier's agent is absent when the carton is opened and the
contents of the carton are damaged, keep the carton and packing material
for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service
Policy to obtain return instructions. It is suggested that salvageable shipping
cartons and packing material be saved for future use in the event the
product must be shipped.
This board is physically protected with packing material and electrically
protected with an anti-static bag during shipment. However, it is
recommended that the board be visually inspected for evidence of
mishandling prior to applying power.
The board utilizes static-sensitive components and should only be handled at
a static-safe workstation.

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2.2 Installation Considerations
IMPORTANT: Adequate air
circulation must be provided to
prevent a temperature rise
above the maximum operating
temperature.
Refer to the specifications section for loading and power requirements. Be
sure that the system power supplies are able to accommodate the power
requirements of the system boards, plus the installed Acromag board,
within the voltage tolerances specified.
In an air cooled assembly, adequate air circulation must be provided to
prevent a temperature rise above the maximum operating temperature and
to prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
In a conduction cooled assembly, adequate thermal conduction must be
provided to prevent a temperature rise above the maximum operating
temperature.
2.3 Board Configuration
Power should be removed from the board when installing AP modules,
cables, termination panels, and field wiring. The AP513 Isolated RS232
communication board has no hardware jumpers or switches to configure.
2.4 Field I/O Connector
A field I/O interface connector provides a mating interface between the AP
modules and the carrier board. The 100 pin ST5-50-1.50-L-D-P-TR Samtec
connector is used on the AcroPack module as board to board interconnect.
This connector will mate with the 100 pin SS5-50-3.00-L-D-K-TR Samtec
connector on the carrier. The stack height is 4.5mm.
Threaded metric M2.5 screws and spacers are supplied with the AcroPack
carriers to provide additional stability for harsh environments.
Table 2.1 lists signal pin assignments for the 100-pin module/carrier field I/O
connectors, as well as the 50-pin/68-pin CHAMP and ribbon I/O connectors
on the carrier.

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Table 2.1 Field I/O Connector Pin Assignments
Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 50-pin
Ribbon I/O
Connector
Pin#
Carrier 50-pin
CHAMP I/O
Connector
Pin#
Carrier 68-pin
CHAMP I/O
Connector
Pin#
AP513
Module
Function
2
Field I/O 1
1
1
1
Isolated GND_A
1
RSVD/ISOL
4
RSVD/ISOL
3
RSVD/ISOL
6
Field I/O 3
3
2
2
RXD_A
5
RSVD/ISOL
8
RSVD/ISOL
7
RSVD/ISOL
10
Field I/O 5
5
3
3
TXD_A
9
RSVD/ISOL
12
RSVD/ISOL
11
RSVD/ISOL
14
Field I/O 7
7
4
4
CTS_A*
13
RSVD/ISOL
16
RSVD/ISOL
15
RSVD/ISOL
18
Field I/O 9
9
5
5
RTS_A*
17
Field I/O 10
10
30
39
Isolated GND_B
20
RSVD/ISOL
19
RSVD/ISOL
22
RSVD/ISOL
21
Field I/O 12
12
31
40
RXD_B
24
RSVD/ISOL
23
RSVD/ISOL
26
RSVD/ISOL
25
Field I/O 14
14
32
41
TXD_B
28
RSVD/ISOL
27
RSVD/ISOL
30
RSVD/ISOL
29
Field I/O 16
16
33
42
CTS_B*
32
RSVD/ISOL
31
RSVD/ISOL
34
RSVD/ISOL
33
Field I/O 18
18
34
43
RTS_B*

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Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 50-pin
Ribbon I/O
Connector
Pin#
Carrier 50-pin
CHAMP I/O
Connector
Pin#
Carrier 68-pin
CHAMP I/O
Connector
Pin#
AP513
Module
Function
36
RSVD/ISOL
35
RSVD/ISOL
38
RSVD/ISOL
37
RSVD/ISOL
40
RSVD/ISOL
39
RSVD/ISOL
42
RSVD/ISOL
41
RSVD/ISOL
44
RSVD/ISOL
43
RSVD/ISOL
46
RSVD/ISOL
45
RSVD/ISOL
48
RSVD/ISOL
47
RSVD/ISOL
50
RSVD/ISOL
49
Field I/O 26
26
38
47
Isolated GND_C
52
RSVD/ISOL
51
RSVD/ISOL
54
RSVD/ISOL
53
Field I/O 28
28
39
48
RXD_C
56
RSVD/ISOL
55
RSVD/ISOL
58
RSVD/ISOL
57
Field I/O 30
30
40
49
TXD_C
60
RSVD/ISOL
59
RSVD/ISOL
62
RSVD/ISOL
61
Field I/O 32
32
41
50
CTS_C*
64
RSVD/ISOL
63
RSVD/ISOL
66
RSVD/ISOL
65
Field I/O 34
34
42
51
RTS_C*
68
RSVD/ISOL
67
RSVD/ISOL
70
Field I/O 35
35
18
18
Isolated GND_D

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Module/Carrier
Field I/O
Connector Pin #
Generic
Field I/O
Connector
Pin Name
Carrier 50-pin
Ribbon I/O
Connector
Pin#
Carrier 50-pin
CHAMP I/O
Connector
Pin#
Carrier 68-pin
CHAMP I/O
Connector
Pin#
AP513
Module
Function
69
RSVD/ISOL
72
RSVD/ISOL
71
RSVD/ISOL
74
Field I/O 37
37
19
19
RXD_D
73
RSVD/ISOL
76
RSVD/ISOL
75
RSVD/ISOL
78
Field I/O 39
39
20
20
TXD_D
77
RSVD/ISOL
80
RSVD/ISOL
79
RSVD/ISOL
82
Field I/O 41
41
21
21
CTS_D*
81
RSVD/ISOL
84
RSVD/ISOL
83
RSVD/ISOL
86
Field I/O 43
43
22
22
RTS_D*
85
RSVD/ISOL
88
RSVD/ISOL
87
RSVD/ISOL
90
RSVD/ISOL
89
RSVD/ISOL
92
RSVD/ISOL
91
RSVD/ISOL
94
RSVD/ISOL
93
RSVD/ISOL
96
RSVD/ISOL
95
RSVD/ISOL
98
RSVD/ISOL
97
RSVD/ISOL
100
RSVD/ISOL
99
RSVD/ISOL
Note: An asterisk (*) is used to indicate an active-low signal.

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2.5Isolation
The RS-232 ports are individually isolated from digital circuitry and from
each other. They maintain 250V working (AC rms or DC) of isolation from
digital and 100V working (AC rms or DC) isolation from each other.
Note: Not all AcroPack carriers are able to maintain this level of isolation.
Consult the AcroPack carrier documentation for supported isolation
voltages.
2.6Logic Interface Connector
The AP module logic edge connector interfaces to the mating connector
on the carrier board. The pin assignments of this connector are standard
for all AP modules according to the PCI Express MINI Card
Electromechanical Specification, REV 1.2 (with exceptions shown in Table
2.2 and noted below).
Threaded metric M2.5 screws and spacers are supplied with the AP
carriers to provide additional stability for harsh environments (see carrier
documentation for assembly details).
Table 2.2 Logic Interface
Connections
Pin #
Name
Pin #
Name
51
N.C. (+5V)3
52
+3.3V4
49
N.C. (+12V)3
50
GND
47
N.C. (-12V)3
48
N.C(+1.5V)
45
Present3
46
N.C. (LED_WPAN#)1
43
GND
44
N.C. (LED_WLAN#)1
41
+3.3V4
42
N.C. (LED_WWAN#)1
39
+3.3V4
40
GND
37
GND
38
N.C. (USB_D+)1
35
GND
36
N.C. (USB_D-)1
33
PETp0
34
GND
31
PETn0
32
SMB_DATA5
29
GND
30
SMB_CLK5
27
GND
28
N.C. (+1.5V)
25
PERp0
26
GND
23
PERn0
24
+3.3V4
21
GND
22
PERST#
19
TDI (UIM_C4)1,6
20
N.C. (W_DISABLE#)1
17
TDO (UIM_C8)1,6
18
GND
15
GND
16
N.C. (UIM_VPP)2
13
RECLK+
14
N.C. (UIM_RESET)2
11
REFCLK-
12
N.C. (UIM_CLK)2
9
GND
10
N.C. (UIM_DATA)2
7
N.C. (CLKREQ#)
8
N.C. (UIM_PWR)2
5
N.C. (TCK) [COEX2]1
6
N.C. (+1.5V)
3
N.C. (TMS) [COEX1]1
4
GND

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1
N.C. (WAKE#)1
2
+3.3V4
Note 1: The following mini-PCIe signals are not supported: USB_D+, USB_D-, WAKE#,
LED_WPAN#, LED_WLAN#, LED_WWAN#, W_DISABLE#, COEX1, COEX2,
UIM_C4, UIM_C8.
Note 2: UIM_PWR, UIM_RESET, UIM_CLK, UIM_VPP, UIM_DATA –SIM card for cell
signals may be available on some AcroPack carriers. See carrier
documentation for more information.
Note 3: +5, +12, and -12 Volt power supplies have been assigned to pins that are
reserved in the mini-PCIe specification. Use of fuses on these power supplies,
along with new Present signal on pin 45, to allow support of mini-PCIe cards
from other vendors that cannot tolerate power applied to these reserved
pins. The Present signal must be grounded on the AP modules. The +12V, -
12V, and +5V voltages are needed to power the proposed Analog AcroPack
modules.
Note 4: All +3.3Vaux power pins are changed to system +3.3V power.
Note 5: The SM bus signals SMB_CLK and SMB_DATA will be used to clock a carrier
location serial stream from the carrier, however this is not supported on the
AP513 module.
Note 6: TDI is tied to TDO on the AP513 module as it does not use JTAG.

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3.0 PROGRAMMING INFORMATION
This section provides an overview of the AP513 module's registers. Once the
driver is loaded the modules will be identified by the operating system as a
standard serial port so low-level programming is not required for normal
operation in a supported operating system.
More detailed register information can be found in the Exar17v354 UART
datasheet, referenced in Section 1.6.
3.1 PCIe Configuration Registers
The PCIe bus is defined to address three distinct address spaces: I/O,
memory, and configuration space. The AcroPack module can be accessed via
the PCIe bus memory space and configuration spaces only.
The AcroPack configuration registers are initialized by system software at
power-up to configure the card. The AcroPack module is a Plug-and-Play
PCIe card. As a Plug-and-Play card the board’s base address and system
interrupt request are not selected via jumpers but are assigned by system
software upon power-up via the configuration registers. A PCIe bus
configuration access is used to access the AcroPack’s configuration registers.
When the computer is first powered-up, the computer’s system
configuration software scans the PCIe bus to determine what PCIe devices
are present. The software also determines the configuration requirements
of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the module requires. It then programs the
board’s configuration registers with the unique memory base address.
Since this board is not fixed in address space, its device driver must use the
mapping information stored in the board’s Configuration Space registers to
determine where the board is mapped in memory space.
The configuration registers are also used to indicate that the board requires
an interrupt request. The system software then programs the configuration
registers with the interrupt request for the board.
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers shown in the following table to facilitate
Plug-and-Play compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers and the Interrupt Register which must be read to

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determine the base address assigned to the board and the interrupt request
that goes active on a board interrupt request.
Table 3.1 PCI Configuration
Registers
Address
Offset
D31 D24
D23 D16
D15 D8
D7 D0
0x00
Device ID
0x0354
Vendor ID
0x13A8
0x04
Status
Command
0x08
Class Code=0x070002
Rev ID=
Current REV
0x0C
BIST
Header
Latency
Cache
0x10
Memory Base Address for Memory Accesses
to PCIe interrupt and I/O registers
16K Space (BAR0)
0x14-
0x28
Not Used
0x2C
Subsystem ID
0x0000
Subsystem Vendor ID
0x0000
0x30
Not Used
0x34-
0x38
Reserved
0x3C
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 16K byte block of memory (BAR0), to access UART
and device configuration registers. Only 4K is used, as the upper 12K is for
channels 4-7 and a second 'slave' UART' connected to the master that does
not exist on the AP513 module.
3.2 UART and Device Configuration Registers
The Device Configuration Registers and the four individual UART
Configuration Registers occupy 4K of PCI bus memory address space. These
registers are offset from the BAR0 address as identified in the PCIe
Configuration Registers in the previous section.
Each UART Configuration Register occupies 1K byte of memory space that
include the 16550 compatible registers.
The Device Configuration Registers are accessible from all UART channels,
however not all bits can be controlled by all channels. The control of the
8XMODE, 4XMODE, RESET, and SLEEP bits are only available for that
particular channel.

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Table 3.2 UART and Device
Configuration Registers
Address Offset
Register Function
Comment
0x0000-0x000F
UART 0 Registers
See Table 3.8
0x0010-0x007F
Reserved
0x0080-0x009A
Device Configuration
Registers
See Table 3.3
0x009B-0x00FF
Reserved
Reserved
0x0100-0x01FF
UART 0 FIFOs
256 bytes of FIFO data
0x0200-0x03FF
UART 0 Read FIFO
with errors
256 bytes of RX FIFO data +
LSR
0x0400-0x07FF
Repeat above registers for UART 1
0x0800-0x0BFF
Repeat above registers for UART 2
0x0C00-0x0FFF
Repeat above registers for UART 3
Table 3.3 Device Configuration
Registers in Byte Alignment
Address
Offset
Register
Read/Write Comments
Reset
State
0x0080
INT0 [7:0]
Read-only Interrupt
0x00
0x0081
INT1[15:8]
Read-only
0x00
0x0082
INT2[23:16]
Read-only
0x00
0x0083
INT3[31:24]
Read-only
0x00
0x0084
TIMERCNTL
Read/Write Timer Control
0x00
0x0085
REGA
Reserved
0x00
0x0086
TIMERLSB
Read/Write Timer LSB
0x00
0x0087
TIMERMSB
Read/Write Timer MSB
0x00
Individual UART channels can only control the bit
pertaining to that channel in the registers at address
offset 0x088-0x08B
0X088
8XMODE
Read/Write
0x00
0x089
4XMODE
Read/Write
0x00
0x08A
RESET
Write-only Self clear bits
after executing Reset
0x00
0x08B
SLEEP
Read/Write Sleep mode
0x00
0x08C
DREV
Read-only Device revision
Current
Rev.
0x08D
DVID
Read-only Device
identification
0x88
0x08E
REGB
Read/Write EEPROM control
0x00
0x08F
MPIOINT[7:0]
Not Used.
0x00
0x090
MPIOLVL[7:0]
Read/Write MPIO[7:0] level
control
0x00
0x091
MPIO3T[7:0]
Not Used.
0x00
0x092
MPIOINV[7:0]
Not Used.
0x00
0x093
MPIOSEL[7:0]
Not Used.
0XFF
0x094
MPIOOD[7:0]
Not Used.
0x00
0x095
MPIOINT[15:8]
Not Used.
0x00

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0x096
MPIOLVL[15:8]
Read/Write MPIO[15:8]
level control
0x00
0x097
MPIO3T[15:8]
Not Used.
0x00
0X098
MPIOINV[15:8]
Not Used.
0x00
0x099
MPIOSEL[15:8]
Not Used.
0xFF
0x09A
MPIOOD[15:8]
Not Used.
0x00
0x09B
Reserved
0x00
Table 3.4 Device Configuration
Registers in DWORD Alignment
Address
Offset
Register
BYTE 3
[31:24]
BYTE 2
[32:16]
BYTE 1
[15:8]
BYTE 0
[7:0]
0x0080–
0x0083
INTERRUPT
(read only)
INT3
INT2
INT1
INT0
0x0084–
0x0087
TIMER
(read/write)
TIMERMSB
TIMERLSB
Reserved
TIMERCTL
0x0088–
0x008B
ANCILLARY1
(read/write)
SLEEP
RESET
4XMODE
8XMODE
0x008C–
0x008F
ANCILLARY2
(read only)
Not used.
REGB
DVID
DREV
0x0090–
0x0093
MPIO1
(read/write)
Not Used.
Not Used.
Not
Used.
MPIOLVL
[7:0]
0x0094–
0x0097
MPIO2
(read/write)
Not Used.
MPIOLVL
[15:8]
Not
Used.
Not Used.
0x0098–
0x009B
MPIO3
(read/write)
Reserved
Not Used.
Not
Used.
Not Used.
3.2.1 The Global Interrupt Registers –INT0, INT1, INT2 and INT3
The XR17V354 can support two different interrupt schemes with a 32-bit
wide register [INT3, INT2, INT1 and INT0]. The first scheme uses INT0 (bits
[7:0]) along with the Interrupt Status Register (ISR) of the individual UART
channels. Each bit gives an indication of the channel that has requested for
service. Bit [0] represents channel 0 and bit [3] indicates channel 3. The
upper four bits INT0[7:4] are reserved. Logic 1 is an indication that the
corresponding channel has called for service. The interrupt bit clears after
reading the appropriate register of the interrupting channel register, see
Interrupt Clearing section.
The second interrupt scheme uses INT3 –INT1 to provide details about the
source of the interrupts for each UART channel. Interrupts are encoded into
a 3-bit code where bits [10:8] represent channel 0 and bits [19:17] represent
channel 3, respectively. Using this scheme, the highest pending interrupt for
all 4 channels are available with a single DWORD read operation without
having to read the ISR register of the individual UART channels. The 3-bit
encoding and their priority order are shown in the table below. If there is a
global interrupt such as the wake-up interrupt, timer/counter interrupt or
MPIO interrupt, then they would be reported in the 3-bit code for channel 0