ARM ARM946E-S Product manual

ARM DDI 0155A
ARM946E-S
Technical Reference Manual

ii Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
ARM946E-S
Technical Reference Manual
Copyright © ARM Limited 2000. All rights reserved.
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ARM, the ARM Powered logo, Thumb and StrongARM are registered trademarks of ARM Limited.
The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, PrimeCell,
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Figure 8-4 on page 8-7 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port
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Change history
Date Issue Change
11th August 2000 A First release
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ARM DDI 0155A-04 Copyright © ARM Limited 2000. All rights reserved. iii
Limited Confidential
Contents
ARM946E-S Technical Reference Manual
Preface
About this document .....................................................................................................xii
Further reading..............................................................................................................xv
Feedback .....................................................................................................................xvi
Chapter 1 Introduction
1.1 About the ARM946E-S..................................................................................1-2
1.2 Microprocessor block diagram......................................................................1-3
Chapter 2 Programmer’s Model
2.1 About the ARM94E-S programmer’s model..................................................2-2
2.2 About the ARM9E-S programmer’s model....................................................2-3
2.3 CP15 register map summary........................................................................2-4
Chapter 3 Caches
3.1 Cache architecture........................................................................................3-2
3.2 ICache...........................................................................................................3-6
3.3 DCache.........................................................................................................3-8
3.4 Cache lockdown..........................................................................................3-12

iv Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A-04
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Chapter 4 Protection Unit
4.1 About the protection unit............................................................................... 4-2
4.2 Memory regions............................................................................................ 4-3
4.3 Overlapping regions ..................................................................................... 4-6
Chapter 5 Tightly-coupled SRAM
5.1 ARM946E-S SRAM requirements................................................................ 5-2
5.2 Using CP15 control register.......................................................................... 5-3
Chapter 6 Bus Interface Unit and Write Buffer
6.1 About the BIU and write buffer ..................................................................... 6-2
6.2 AHB bus master interface............................................................................. 6-3
6.3 Noncached Thumb instruction fetches......................................................... 6-8
6.4 AHB clocking................................................................................................ 6-9
6.5 The write buffer........................................................................................... 6-12
Chapter 7 Coprocessor Interface
7.1 About the coprocessor interface................................................................... 7-2
7.2 LDC/STC...................................................................................................... 7-4
7.3 MCR/MRC.................................................................................................... 7-8
7.4 Interlocked MCR......................................................................................... 7-10
7.5 CDP............................................................................................................ 7-11
7.6 Privileged instructions................................................................................. 7-12
7.7 Busy-waiting and interrupts........................................................................ 7-13
Chapter 8 Debug Support
8.1 About the debug interface ............................................................................ 8-2
8.2 Debug systems............................................................................................. 8-4
8.3 The JTAG state machine.............................................................................. 8-7
8.4 Scan chains................................................................................................ 8-12
8.5 Debug access to the caches ...................................................................... 8-17
8.6 Debug interface signals.............................................................................. 8-19
8.7 ARM9E-S core clock domains.................................................................... 8-24
8.8 Determining the core and system state...................................................... 8-25
8.9 Overview of EmbeddedICE-RT.................................................................. 8-26
8.10 Disabling EmbeddedICE-RT ...................................................................... 8-28
8.11 The debug communications channel.......................................................... 8-29
8.12 Real-time debug......................................................................................... 8-33
Chapter 9 ETM Interface
9.1 About the ETM interface............................................................................... 9-2
9.2 Enabling the ETM interface.......................................................................... 9-4
Chapter 10 Test Support
10.1 About the ARM946E-S test methodology................................................... 10-2
10.2 Scan insertion and ATPG........................................................................... 10-3
10.3 BIST of memory arrays............................................................................... 10-5

ARM DDI 0155A-04 Copyright © ARM Limited 2000. All rights reserved. v
Limited Confidential
Appendix A AC Parameters
A.1 Timing diagrams ...........................................................................................A-2
A.2 AC timing parameter definitions....................................................................A-9
Appendix B Signal Descriptions
B.1 Signal properties and requirements..............................................................B-2
B.2 Clock interface signals..................................................................................B-3
B.3 AHB signals ..................................................................................................B-4
B.4 Coprocessor interface signals.......................................................................B-6
B.5 Debug signals ...............................................................................................B-8
B.6 JTAG signals...............................................................................................B-10
B.7 Miscellaneous signals.................................................................................B-11
B.8 ETM interface signals .................................................................................B-12
B.9 INTEST wrapper signals.............................................................................B-14
Index

vi Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A-04
Limited Confidential

ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. vii
Limited Confidential
List of Tables
ARM946E-S Technical Reference Manual
Table 1-1 Location of block descriptions...............................................................1-4
Table 2-1 CP15 register map................................................................................2-4
Table 2-2 CP15 abbreviations...............................................................................2-5
Table 2-3 Register 0, ID code ...............................................................................2-7
Table 2-4 Cache type register format....................................................................2-7
Table 2-5 Cache size encoding.............................................................................2-8
Table 2-6 Cache associativity encoding................................................................2-9
Table 2-7 Tightly-coupled memory size register ................................................2-10
Table 2-8 Memory size field ...............................................................................2-10
Table 2-9 Register 1, control register..................................................................2-11
Table 2-10 Programming instruction/data cachable bits.......................................2-15
Table 2-11 Programming data bufferable bits ......................................................2-16
Table 2-12 Programming instruction and data access
permission bits (extended)..................................................................2-17
Table 2-13 Access permission encoding (extended) ............................................2-17
Table 2-14 Instruction and data access permission bits (standard) ....................2-18
Table 2-15 Access permission encoding (standard).............................................2-19
Table 2-16 Accessing protection region/base size registers.................................2-20
Table 2-17 Protection region/base size register format.........................................2-20
Table 2-18 Area size encoding..............................................................................2-21
Table 2-19 Cache operations ...............................................................................2-22
Table 2-20 Index fields for supported cache sizes................................................2-23
Table 2-21 Lockdown register format....................................................................2-25

viii Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
Limited Confidential
Table 2-22 Protection region/base size register format........................................ 2-26
Table 2-23 Tightly-coupled memory area size encoding...................................... 2-27
Table 2-24 Register 15, BIST instructions............................................................ 2-29
Table 2-25 Register 15, implementation-specific BIST instructions ..................... 2-29
Table 2-26 Test state register bit assignments .................................................... 2-30
Table 2-27 Additional operations ......................................................................... 2-31
Table 2-28 Index fields for supported cache sizes ............................................... 2-33
Table 3-1 TAG and index fields for supported cache sizes.................................. 3-4
Table 3-2 Meaning of Cd bit values...................................................................... 3-9
Table 3-3 Calculating index addresses............................................................... 3-11
Table 4-1 Protection register format..................................................................... 4-3
Table 4-2 Region size encoding........................................................................... 4-4
Table 6-1 Supported burst types .......................................................................... 6-4
Table 6-2 Data write modes................................................................................ 6-12
Table 7-1 Handshake encoding............................................................................ 7-7
Table 8-1 Public instructions................................................................................. 8-9
Table 8-2 ARM946E-S scan chain allocations ................................................... 8-12
Table 8-3 Scan chain 1 bits................................................................................ 8-13
Table 8-4 Scan chain 15 addressing mode bit order.......................................... 8-14
Table 8-5 Mapping of scan chain 15 address field to CP15 registers ................ 8-14
Table 8-6 Coprocessor 14 register map............................................................. 8-29
Table 10-1 Instruction BIST address and general registers ................................. 10-7
Table 10-2 Data BIST address and general registers .......................................... 10-7
Table A-1 Timing parameter definitions ..............................................................A-9
Table B-1 Clock interface signals .........................................................................B-3
Table B-2 AHB signals .........................................................................................B-4
Table B-3 Coprocessor interface signals .............................................................B-6
Table B-4 Debug signals ......................................................................................B-8
Table B-5 JTAG signals .....................................................................................B-10
Table B-6 Miscellaneous signals ........................................................................B-11
Table B-7 ETM interface signals ........................................................................B-12
Table B-8 INTEST wrapper signals ....................................................................B-14

ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. ix
Limited Confidential
List of Figures
ARM946E-S Technical Reference Manual
Figure 1-1 ARM946E-S block diagram...................................................................1-3
Figure 2-1 CP15 MRC and MCR bit pattern...........................................................2-6
Figure 2-2 Index and segment format ..................................................................2-23
Figure 2-3 ICache address format........................................................................2-24
Figure 2-4 Process ID format ...............................................................................2-29
Figure 2-5 Index/segment format .........................................................................2-32
Figure 2-6 Data format TAG read/write operations ..............................................2-32
Figure 3-1 Example 8K cache................................................................................3-3
Figure 3-2 Access address for a 4KB cache..........................................................3-5
Figure 3-3 Register 7, Rd format..........................................................................3-10
Figure 4-1 ARM946E-S protection unit...................................................................4-2
Figure 4-2 Overlapping memory regions................................................................4-6
Figure 5-1 SRAM read cycle ..................................................................................5-2
Figure 6-1 Linefetch transfer ..................................................................................6-4
Figure 6-2 Back to back linefetches.......................................................................6-5
Figure 6-3 Nonsequential uncached accesses.......................................................6-6
Figure 6-4 Data burst followed by instruction fetch ................................................6-6
Figure 6-5 Crossing a 1KB boundary.....................................................................6-7
Figure 6-6 AHB clock relationships ......................................................................6-10
Figure 6-7 ARM946E-S CLK to AHB HCLK sampling..........................................6-11
Figure 7-1 Coprocessor clocking............................................................................7-2
Figure 7-2 LDC/STC cycle timing...........................................................................7-4
Figure 7-3 MCR/MRC transfer timing with busy-wait .............................................7-8

x Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
Limited Confidential
Figure 7-4 Interlocked MCR/MRC timing with busy-wait ..................................... 7-10
Figure 7-5 Late cancelled CDP............................................................................ 7-11
Figure 7-6 Privileged instructions......................................................................... 7-12
Figure 7-7 Busy-waiting and interrupts................................................................ 7-13
Figure 8-1 Clock synchronization........................................................................... 8-3
Figure 8-2 Typical debug system........................................................................... 8-4
Figure 8-3 ARM9E-S block diagram...................................................................... 8-6
Figure 8-4 Test access port (TAP) controller state transitions............................... 8-7
Figure 8-5 TAG address format ........................................................................... 8-17
Figure 8-6 Cache index register format ............................................................... 8-18
Figure 8-7 Breakpoint timing................................................................................ 8-19
Figure 8-8 Watchpoint entry with data processing instruction ............................. 8-21
Figure 8-9 Watchpoint entry with branch............................................................. 8-22
Figure 8-10 The ARM9E-S, TAP controller, and EmbeddedICE-RT..................... 8-26
Figure 8-11 Debug comms channel status register............................................... 8-30
Figure 8-12 Coprocessor 14 debug status register format .................................... 8-31
Figure 9-1 ARM946E-S ETM interface .................................................................. 9-3
Figure A-1 Clock, reset, and AHB enable timing ...................................................A-2
Figure A-2 AHB bus request and grant related timing ...........................................A-2
Figure A-3 AHB bus master timing ........................................................................A-3
Figure A-4 Coprocessor interface timing ...............................................................A-4
Figure A-5 Debug interface timing .........................................................................A-5
Figure A-6 JTAG interface timing ..........................................................................A-6
Figure A-7 DBGSDOUT to DBGTDO timing .........................................................A-6
Figure A-8 Exception and configuration timing ......................................................A-7
Figure A-9 INTEST wrapper timing .......................................................................A-7
Figure A-10 ETM interface timing ............................................................................A-8

ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. xi
Preface
This preface introduces the ARM946E-S and its reference documentation. It contains
the following sections:
•About this document on page xii
•Further reading on page xv
•Feedback on page xvi.

xii Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
About this document
This document is a reference manual for the ARM946E-S.
Intended audience
This document has been written for hardware and software engineers who want to
design or develop products based upon the ARM946E-S processor. It assumes no prior
knowledge of ARM products.
Using this manual
This document is organized into the following chapters:
Chapter 1 Introduction
This chapter provides an introduction to the ARM946E-S.
Chapter 2 Programmer’s Model
This chapter describes the programmer’s model of the ARM946E-S and
includes a summary of the ARM946E-S coprocessor registers.
Chapter 3 Caches
This chapter describes the ARM946E-S cache implementation.
Chapter 4 Protection Unit
This chapter describes the ARM946E-S protection unit.
Chapter 5 Tightly-coupled SRAM
This chapter describes the requirements and operation of the
tightly-coupled SRAM.
Chapter 6 Bus Interface Unit and Write Buffer
This chapter describes the operation of the Bus Interface Unit and write
buffer.
Chapter 7 Coprocessor Interface
This chapter describes the coprocessor interface and the operation of
common coprocessor instructions.

ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. xiii
Chapter 8 Debug Support
This chapter describes the debug support for the ARM946E-S and the
EmbeddedICE-RT logic.
Chapter 9 ETM Interface
This chapter describes the ETM interface, including details of how to
enable the interface.
Chapter 10 Test Support
This chapter describes the test methodology used for the ARM946E-S
synthesized logic and tightly-coupled SRAM.
Appendix A AC Parameters
This appendix describes the timing parameters applicable to the
ARM946E-S.
Appendix B Signal Descriptions
This appendix describes the signals used in the ARM946E-S.
Typographical conventions
The following typographical conventions are used in this document:
bold HighlightsARMprocessor signalnames withintext,andinterface
elements such as menu names. Can also be used for emphasis in
descriptive lists where appropriate.
italic Highlights special terminology, cross-references and citations.
typewriter Denotes text that can be entered at the keyboard, such as
commands, file names and program names, and source code.
typewriter Denotes a permitted abbreviation for a command or option. The
underlined text may be entered instead of the full command or
option name.
typewriter italic
Denotesargumentstocommandsor functionswhere theargument
is to be replaced by a specific value.
typewriter bold Denotes language keywords when used outside example code.

xiv Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
Timing diagram conventions
This manual contains a number of timing diagrams. The following key explains the
components used in these diagrams. Any variationsare clearly labeled whenthey occur.
Therefore, no additional meaning should be attached unless specifically stated.
Key to timing diagram conventions
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Clock
Bus stable
HIGH to LOW
Transient
Bus to high impedance
Bus change
HIGH/LOW to HIGH
High impedance to stable bus
Valid (correct) sampling point

ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. xv
Further reading
This section lists publications by ARM Limited, and by third parties.
If you would like further information on ARM products, or if you have questions not
answered by this document, please contact [email protected] or visit our web site at
http://www.arm.com.
ARM publications
ARM Architecture Reference Manual (ARM DDI 0100).
ARM9E-S Technical Reference Manual (ARM DDI 0165).
AMBA Specification (Rev 2.0) (ARM IHI 0011).
Other publications
IEEE Std. 1149.1-1990, Standard Test Access Port and Boundary-Scan Architecture.

xvi Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
Feedback
ARM Limited welcomesfeedback both on the ARM946E-S, andon the documentation.
Feedback on the ARM946E-S
If you have any comments or suggestions about this product, please contact your
supplier giving:
• the product name
• a concise explanation of your comments
Feedback on the document
If you have any comments about this document, please send email to
[email protected] giving:
• the document title
• the document number
• the page number(s) to which your comments refer
• a concise explanation of your comments.
General suggestions for additions and improvements are also welcome.

ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. 1-1
Chapter 1
Introduction
This chapter introduces the ARM946E-S processor. It contains the following sections:
•About the ARM946E-S on page 1-2
•Microprocessor block diagram on page 1-3.

Introduction
1-2 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
1.1 About the ARM946E-S
The ARM946E-S is a synthesizable macrocell combining an ARM processor. It is a
member of the ARM9 Thumb family of high-performance, 32-bit system-on-chip
processor solutions.
The ARM946E-S has tightly-coupled SRAM memory, and instruction and data caches
and is targeted at a wide range of embedded applications where high-performance, low
system cost, small die size and low power are all important.
The ARM946E-S processor macrocell is a Harvard architecture cached processor that
provides a complete high-performance processor subsystem, including:
• An ARM9E-S RISC integer CPU core featuring:
— ARMv5TExP 32-bit instruction set with improved ARM/Thumb code
interworking and enhanced multiplier designed for improved DSP
performance.
— ARM debug architecture with additional support for real-time debug. This
allows critical exception handlers to execute while debugging the system.
• Tightly-coupled SRAM for each of the instruction and data CPU interfaces. The
size of both the instruction and data SRAM are implementor-configurable.
• Instruction and data caches. The design can be easily modified to allow any
combination of caches from 4 Kbytes to 1 Mbyte.
• A protection unit that allows the memory to be segmented and protected in a
simple manner, ideal for embedded control applications.
• An AMBA AHB bus interface. ARM946E-S interfaces to the rest of the system
are through use of unified address and data buses. This interface is compatible
with the AMBA AHB bus standard.
• Support for external coprocessors allowing floating point or other application
specific hardware acceleration to be added. For coprocessor support, the
instruction and data buses are exported along with simple handshaking signals.
• Support for the use of a scan test methodology for the standard cell logic and
Built-In-Self-Test (BIST) for the tightly-coupled SRAM and caches.
• An interface to an external Embedded Trace Macrocell (ETM) to support
real-time tracing of instructions and data.
Providing this complete high frequency subsystem frees the system-on-a-chip designer
to concentrate on design issues unique to their system. The synthesizable nature of the
device eases integration into ASIC technologies.

Introduction
ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. 1-3
1.2 Microprocessor block diagram
The ARM946E-S block diagram is shown in Figure 1-1.
Figure 1-1 ARM946E-S block diagram
ARM9E-S
Instruction
SRAM
Data
SRAM System control
coprocessor
(CP15)
External
coprocessor
interface
AHB
Bus interface unit
and write buffer
ETM
interface
IA DA
WDATA
RDATAINSTR
Addr Din Addr Din
Data
cache
Instruction
cache
Memory
protection
unit
System
controller
Data
cache
control
Instruction
cache
control

Introduction
1-4 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A
The blocks shown in Figure 1-1 on page 1-3 are described in the locations listed in
Table 1-1.
Table 1-1 Location of block descriptions
Block Location of description
ARM9E-S ARM9E-S Technical Reference Manual
AHB bus interface unit and write
buffer Chapter 6 Bus Interface Unit and Write Buffer
Instruction SRAM Chapter 5 Tightly-coupled SRAM
Data SRAM Chapter 5 Tightly-coupled SRAM
System control coprocessor
(CP15) Chapter 2 Programmer’s Model
External coprocessor interface Chapter 7 Coprocessor Interface
ETM interface Chapter 9 ETM Interface
System controller Chapter 2 Programmer’s Model
Memory protection unit Chapter 4 Protection Unit
Instruction cache Chapter 3 Caches
Data cache Chapter 3 Caches
Instruction cache control Chapter 2 Programmer’s Model and Chapter 3 Caches
Data cache control Chapter 2 Programmer’s Model and Chapter 3 Caches