Alpha Data ADA-VPX3-7V1 User manual

ADA-VPX3-7V1
User Manual
Document Revision: 2.1
6th anuary 2016

ADA-VPX3-7V1 User Manual
V2.1 - 6th anuary 2016
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ADA-VPX3-7V1 User Manual
V2.1 - 6th anuary 2016
Table Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 References & Specifications .......................................................................................................... 2
2 Installation ........................................................................................................................................ 2
2.1 Software Installation ...................................................................................................................... 2
2.2 Hardware Installation ..................................................................................................................... 2
2.2.1 Handling Instructions ................................................................................................................. 2
2.2.2 Cooling Requirements ............................................................................................................... 2
3 Functional Description .................................................................................................................... 4
.1 Overview ........................................................................................................................................ 4
.1.1 Switch Definitions ...................................................................................................................... 5
.1.2 LED Definitions .......................................................................................................................... 6
.2 VPX P0 Interface ........................................................................................................................... 7
.2.1 MVMRO ..................................................................................................................................... 7
.2.2 SYSRESET# .............................................................................................................................. 7
.2. AUXCLK ..................................................................................................................................... 7
. JTAG Interface ............................................................................................................................... 8
. .1 On-board Interface ..................................................................................................................... 8
. .2 VPX Interface ............................................................................................................................. 8
. . JTAG Voltages ........................................................................................................................... 8
.4 Clocks ............................................................................................................................................ 9
.4.1 200MHz Reference Clock (REFCLK200M) ............................................................................... 9
.4.2 PCIe Reference Clock 0 (PCIEREFCLK0) .............................................................................. 10
.4. PCIe Reference Clock 1 (PCIEREFCLK1) .............................................................................. 10
.4.4 AUXCLK ................................................................................................................................... 11
.4.5 Programmable Clocks (LCLK, PROGCLK 0- ) ........................................................................ 11
.4.6 Module-Carrier Global Clock (GCLK_M2C) ............................................................................. 11
.4.7 Module-Carrier MGT Clock (MGTCLK_M2C) .......................................................................... 11
.4.8 XRM LVDS Clock (XRM_LVDS_CLK) ..................................................................................... 12
.5 Flash Memory .............................................................................................................................. 1
.6 Configuration ............................................................................................................................... 14
.6.1 Power-Up Sequence ................................................................................................................ 14
.6.2 Bridge-Less Mode .................................................................................................................... 14
.7 Health Monitoring ......................................................................................................................... 15
.7.1 Automatic Temperature Monitoring .......................................................................................... 16
.7.2 Microcontroller Status LEDs .................................................................................................... 16
.8 Local Bus ..................................................................................................................................... 17
.9 Target FPGA ................................................................................................................................ 17
.9.1 I/O Bank Voltages .................................................................................................................... 17
.9.2 Target MGT Links .................................................................................................................... 17
.10 Memory Interfaces ....................................................................................................................... 18
.11 XRM Interface and Front-Panel I/O ............................................................................................. 20
.11.1 XRM Connector, CN1 .............................................................................................................. 20
.11.2 XRM Connector CN2 ............................................................................................................... 20
.11. XRM I/F - GPIO ....................................................................................................................... 20
.11.4 XRM I/F - High-speed Serial Links .......................................................................................... 21
Appendix A VPX Backplane Pinouts ................................................................................................................ 23
Appendix B Front (XRM) Connector Pinouts ................................................................................................... 24

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B.1 XRM Connector CN1, Field 1 ...................................................................................................... 25
B.2 XRM Connector CN1, Field 2 ...................................................................................................... 26
B. XRM Connector CN1, Field ...................................................................................................... 27
B.4 XRM Connector CN2 ................................................................................................................... 28
List of Tables
Table 1 References ........................................................................................................................................ 2
Table 2 XMC SW1 efinitions ........................................................................................................................ 5
Table 3 LE efinitions .................................................................................................................................. 6
Table 4 REFCLK200M Connections ............................................................................................................. 10
Table 5 PCIEREFCLK Connections ............................................................................................................. 10
Table 6 AUXCLK Connections ...................................................................................................................... 11
Table 7 PROGCLK Connections .................................................................................................................. 11
Table 8 GCLK_M2C Connections ................................................................................................................. 11
Table 9 MGTCLK_M2C Connections ........................................................................................................... 11
Table 10 XRM_LV S_CLK Connections ........................................................................................................ 12
Table 11 Voltage and Temperature Monitors .................................................................................................. 15
Table 12 Temperature Limits .......................................................................................................................... 16
Table 13 Status LE efinitions ..................................................................................................................... 16
Table 14 Target FPGA IO Banks .................................................................................................................... 17
Table 15 Target MGT Links ............................................................................................................................ 17
Table 16 Maximum Memory Speeds .............................................................................................................. 19
Table 17 XRM GPIO Groups .......................................................................................................................... 20
Table 18 XRM Connector CN1, Field 1 .......................................................................................................... 25
Table 19 XRM Connector CN1, Field 2 .......................................................................................................... 26
Table 20 XRM Connector CN1, Field 3 .......................................................................................................... 27
Table 21 XRM Connector CN2 ....................................................................................................................... 28
List of Figures
Figure 1 A A-VPX3-7V1 Block iagram ......................................................................................................... 4
Figure 2 XMC LE Locations .......................................................................................................................... 6
Figure 3 JTAG Header XMC-J1 ....................................................................................................................... 8
Figure 4 JTAG Boundary Scan Chain .............................................................................................................. 8
Figure 5 Clocks ................................................................................................................................................ 9
Figure 6 Flash Memory Map .......................................................................................................................... 13
Figure 7 MGT Links ....................................................................................................................................... 18
Figure 8 RAM Banks ................................................................................................................................... 19

ADA-VPX3-7V1 User Manual
V2.1 - 6th anuary 2016
1 Introduction
The A A-VPX3-7V1 is a high-performance 3U OpenVPX Card for applications using Virtex-7 and Virtex-6
FPGAs from Xilinx. This card supports Virtex-7 devices available in the FF(G), 1761 package.
The A A-VPX3-7V1 includes separate FPGA with a PCIe bridge developed by Alpha ata. Using a separate
device allows high performance operation without the need to integrate proprietary cores in the user (target)
FPGA.
With the release of 7series FPGA boards, Alpha ata has introduced a new build option to allow the mezzanine
card to be assembled without the bridge to reduce power and cost.
The A A-VPX3-7V1 is available in air-cooled and conduction-cooled configurations. View the A A-VPX3-7V1
Ordering Info tab at A A-VPX3-7V1 Product Page on www.alpha-data.com.
1.1 Key Features
Key Features
Open VPX Compliance List
• 3U OpenVPX, compliant to VITA Standard 46.0 and 65
• edicated 4-lane PCI-Express Gen 2 interface with high-performance MA controllers
• Two VPX control planes connected to target FPGA
• VPX User I/O interface with 78 GPIO (64 can be driven differentially) signals and up to 14 Multi-Gigabit
(MGT) links
• Two mSATA sites linked to target FPGA
• Rear Transition Module (RTM) breaks out all signals for accelerated development
• Support for Virtex-7 FPGA in FF(G) 1761 package
• 4 independent banks of R3-1600 S RAM, 512MB/bank, 2GB total (4GB option)
• Front-panel (XRM) interface with adjustable voltage, 146 GPIO signals and 8 GTX links to user FPGA
• On-board programmable clocks enable multiple protocols to be implemented on the user FPGA's
high-speed links
• Voltage and temperature monitoring
• Air-cooled and conduction-cooled configurations
• SLT3-PAY-2F2U-14.2.3
• SLT3-PAY-1F1F2U-14.2.4
• SLT3-PAY-1 -14.2.6
• SLT3-PAY-2F-14.2.7
• SLT3-PAY-1F4U-14.2.8
• SLT3-PAY-8U-14.2.9
• SLT3-PER-2F-14.3.1
• SLT3-PER-1F-14.3.2
• SLT3-PER-1U-14.3.3
• SLT3-STO-2U-14.5.1
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1.2 References & Specifications
ANSI/VITA 42.0 XMC Standard, ecember 2008, VITA, ISBN 1-885731-49-3
ANSI/VITA 42.3 XMC PCI Express Protocol Layer Standard, June 2006, VITA, ISBN 1-885731-43-4
ANSI/VITA 46.0 VPX Baseline Standard, October 2007, VITA, ISBN 1-885731-44-2
ANSI/VITA 46.9 PMC/MXC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules Standard,
November 2010, VITA, ISBN 1-885731-63-9
ANSI/VITA 48.2 Mechanical Specifications for Microcomputers Using RE I Conduction Cooling
Applied to VITA VPX, July 2010, VITA, ISBN 1-885731-60-4
ANSI/VITA 65 OpenVPX™ System Specification, June 2010, VITA, ISBN 1-885731-58-2
ANSI/IEEE 1386-2001 IEEE Standard for a Common Mezzanine Card (CMC) Family, October 2001, IEEE,
ISBN 0-7381-2829-5
ANSI/IEEE 1386.1-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC),
October 2001, IEEE, ISBN 0-7381-2831-7
ANSI/VITA 20-2001
(R2005) Conduction Cooled PMC, February 2005, VITA, ISBN 1-885731-26-4
Table 1 : References
2 Installation
2.1 Software Installation
Please refer to the Software evelopment Kit (S K) installation C . The S K contains drivers, examples for
host control and FPGA design and comprehensive help on application interfacing.
2.2 Hardware Installation
2.2.1 Handling Instructions
The components on this board can be damaged by electrostatic discharge (ES ). To prevent damage, observe
SS precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ES safe bag.
2.2.2 Cooling Requirements
The power dissipation of the board is highly dependent on the Target FPGA application. A power estimator
spreadsheet is available on request from Alpha ata. This should be used in conjunction with Xilinx power
estimation tools to determine the exact current requirements for each power rail.
The board is supplied with a passive air cooled or conduction cooled heatsink according to the order number
given at time of purchase. It is the users responsibility to ensure sufficient airflow for air cooled applications and
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metalwork for conduction cooled applications.
For more details on heatsinks supplied with Alpha ata boards, please view A -AN-0018 A M-XRC Cooling
Solutions.
The board features system monitoring that measures the board and FPGA temperature. It also includes a
self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is
detected.
See Section 3.7 for further details.
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3 Functional Description
3.1 Overview
P0
16
PCIe / DMA
Bridge
(Virtex 6)
VIRTEX 7
XC7V585T
XC7VX330T
XC7VX485T
XC7VX6 0T
MGTGPIO
XRM
Modular Front Panel
I/O Interface
GPIO, Video, Optical, ADC, DAC
GPIOMGT
4 Banks
DDR3
SDRAM
2GB Total
P1P2
Data or
Expansion
GPIO (SE)
Control
Power
+
System
Controller
GPIO
(Single Ended or Diff Pairs)
15
Data
1413121110 8765432187654321
x4
PCIe
Dual
mSATA
Sites
FLASH
Config
16 15 14 13 12 11 10 6 5 4 3 2 18 7
Bridge Bypass
Expansion
MGT GPIO
1000Base-X
SPI Config
Figure 1 : ADA-VPX3-7V1 Block Diagram
Note:
The A A-VPX3-7V1 is comprised of an A M-XRC-7V1 XMC card mounted to an A C-VPX3-XMC VPX
carrier specifically designed to host Alpha ata XMCs. All reference to "XMC" refer to the A M-XRC-7V1,
while all references to "Carrier" refer to the A C-VPX3-XMC.
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3.1.1 Switch Definitions
There are three sets of eight IP switches. One is placed on the XMC card and the other two are on the VPX
Carrier. Their functions are described in tables below.
Note:
All switches are OFF by default. Factory Configuration switch must be in the OFF position for normal
operation.
Switch Ref. Function ON State Off State
SW1-1 User Switch to
Target FPGA 0 1
SW1-2 Reserved - Normal Operation
SW1-3 Bridge Bypass Bridge FPGA is bypassed - PCIe lanes (3:0) are connected directly to the user
FPGA.
Bridge FPGA is used. PCIe lanes (3:0)
are connected to the bridge.
SW1-4 Flash Boot
Inhibit Target FPGA is not configured from onboard flash memory. Target FPGA is configured from on- board flash memory.
SW1-5 XMC JTAG Connect JTAG chain to P5 Isolate JTAG chain from P5
SW1-6 E-Fuse Enable E-Fuse programming voltage
(VccEFuse = 2.5V) isable E-Fuse programming voltage (VccEFuse = 0V)
SW1-7 <i>Factory Configuration</
i> - Normal Operation
SW1-8 Bridge-Less
Mode Bridge-Less Mode Active - User bitstream loaded from SPI flash PCIe Bridge Mode Active - User bitstream loaded from Bridge
Table 2 : XMC SW1 Definitions
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3.1.2 LED Definitions
There are eight LE s placed on the rear of the XMC board to indicate status:
D7 Status 1
D8 Status 2
D9 Target Done
D10 Bridge Done
D11 Bridge-Bypass
D10 Bridge-Less
D13 NVMR D14 XMC JTAG
Figure 2 : XMC LED Locations
Comp. Ref. Function ON State Off State
7 Status 1 See Table Status LE efinitions
8 Status 2 See Table Status LE efinitions
9 Target one Target FPGA is configured Target FPGA is unconfigured
10 Bridge one Bridge FPGA is configured Bridge FPGA is unconfigured
11 Bridge Bypass Bridge FPGA is bypassed - PCIe lanes (3:0) are connected directly to the user
FPGA
Bridge FPGA is used. PCIe lanes (3:0)
are connected to the bridge.
12 Bridge-Less Target is configured through Auxiliary
SPI memmory Target is configured by Bridge
13 NVMRO Inhibit writes to non-volatile memories Enable writes to non-volatile memories
14 XMC JTAG On-board JTAG chain connected to P5 On-board JTAG chain is isolated from
P5
Table 3 : LED Definitions
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3.2 VPX P0 Interface
3.2.1 MVMRO
Non-Volatile Memory Read Only. This signal is an input from the system. When asserted (high), all writes to
non-volatile memories are inhibited. This is indicated by the Amber LE , XMC- 7.
This signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the target
FPGA.
3.2.2 SYSRESET#
XMC Reset In. This signal is an active low input from the system. When asserted, the bridge FPGA will be
reset. This also acts and PCI Reset.
The SYSRESET# signal is translated to 1.8V levels and connected to the target FPGA at pin AF30.
3.2.3 AUXCLK
Auxiliary Clock. This clock is a direct input to the target FPGA. In OpenVPX this clock line is used for 1PPS
synchronization signaling.
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3.3 TAG Interface
3.3.1 On-board Interface
A JTAG boundary scan chain is connected to header XMC-J1. This allows the connection of the Xilinx JTAG
cable for FPGA debug using the Xilinx ChipScope tools.
The JTAG Header pinout is shown in Figure JTAG Header XMC-J1:
VCC
GND
TCK
TDO
TDI
TMS
Figure 3 : TAG Header XMC- 1
The scan chain is shown in Figure JTAG Boundary Scan Chain:
Bridge FPGA
XC6VLX130T
FFG484
Control CPLD
XC2C64A
CP56
Target FPGA
XC7VxxxxT
FFG1759
XRM
I/F
PRESENT#
VREF (1.8V)
Level Shift
1.8V - XRM VIO
En#
XRM TDI
XRM TDO
HDR TDI
HDR TDO
Level Shift
3.3V – 1.8V
En#
XMC
Con
(Pn5
Header
J3
XMC TDI
XMC TDO
XMC JTAG EN# SW1-5
Figure 4 : TAG Boundary Scan Chain
If the boundary scan chain is connected to the interface at the XMC connector (XMC-SW1-4 is ON), Header
XMC-J1 should not be used.
3.3.2 VPX Interface
The JTAG interface on the VPX connector is normally unused with XMC_T I and XMC_T O floating.
The interface can be connected to the on-board interface (through level-translators) by switching XMC-SW1-4
ON. See Section Switch efinitions
3.3.3 TAG Voltages
The on-board JTAG scan chain uses 1.8V. The Vcc supply provided on XMC-J1 to the JTAG cable is +1.8V and
is protected by a poly fuse rated at 350mA. 3.3V signals must not be used at header XMC-J1.
The JTAG signals at the VPX interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
The JTAG signals at the XRM interface use the adjustable voltage XRM_VIO.
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3.4 Clocks
The A A-VPX3-7V1 provides a wide variety of clocking options. On top of a fixed 200MHz oscillator and clocks
routed from the rear and front panel connectors, the board has 4 user-programmable clocks. These clocks can
be combined with the FPGA's internal PLLs to suit a wide variety of communication protocols.
A complete overview of the clock routing on the A A-VPX3-7V1 is given in Figure Clocks. A description of each
clock follows.
7 Series
MGT/ Banks
MGT111
REFCLK0
REFCLK1
MGT112
REFCLK0
REFCLK1
MGT113
REFCLK0
REFCLK1
MGT114
REFCLK0
REFCLK1
MGT115
REFCLK0
REFCLK1
MGT116
REFCLK0
REFCLK1
MGT117
REFCLK0
REFCLK1
MGT118
REFCLK0
REFCLK1
100MHz
S urce
PCIe
REFCLK
Buffer
PCIe
Bridge
200MHZ
Buffer
200MHZ
S urce
XRM Interface
User
Pr grammable
S urce
MGT119
REFCLK0
REFCLK1
REFCLK
Buffer
250MHZ
S urce
DDR3
Banks
19 35
37 39
Bank 14
P0
AUXCLK
REFCLK
Bank 33
Figure 5 : Clocks
Note:
Clock Termination
The LV S clocks do not have termination resistors on the circuit board. On-die terminations in the FPGA must
be enabled by setting the attribute " IFF_TERM = TRUE". This can either be set in the source code when
instantiating the buffer, or in the User Constraints File (UCF). See the Xilinx Virtex-7 Libraries Guide and
Constraints Guide for further details.
3.4.1 200MHz Reference Clock (REFCLK200M)
The fixed 200MHz reference clock REFCLK200M is a differential clock signal using LV S. This signal is widely
distributed throughout the board.
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It is connected to a MRCC inputs on the Target FPGA on Bank 14.
REFCLK200M is also converted to HSTL signaling and used as the input clock for the RAM interface.
This clock can be used to generate application-specific clock frequencies using the PLLs within the Virtex-7
FPGA. It is also suitable as the reference clock for the IO delay control block (I ELAYCTRL).
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
REFCLK200M 200 MHz IO_L12_T2_MRCC_14 LV S AK34 AL34
REFCLK200M_HSTL 200 MHz IO_L12_T1_MRCC_19 HSTL_I L39 L40
REFCLK200M_HSTL 200 MHz IO_L12_T1_MRCC_35 HSTL_I E34 E35
REFCLK200M_HSTL 200 MHz IO_L12_T1_MRCC_37 HSTL_I 27 28
REFCLK200M_HSTL 200 MHz IO_L12_T1_MRCC_39 HSTL_I H15 H14
REFCLK200M 200 MHz MGTREFCLK0_115 LV S Y8 Y7
REFCLK200M 200 MHz MGTREFCLK0_118 LV S G10 G9
Table 4 : REFCLK200M Connections
3.4.2 PCIe Reference Clock 0 (PCIEREFCLK0)
The 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector,
P5 at pins A19 and B19. This clock is buffered into two PLE Express reference clocks that are forwarded to the
Bridge and User FPGA respectively.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
PCIEREFCLK 100 MHz MGTREFCLK0_117 LV S K8 K7
Table 5 : PCIEREFCLK Connections
3.4.3 PCIe Reference Clock 1 (PCIEREFCLK1)
The reference clock "PCIEREFCLK1" is a differential clock provided by a carrier card through the Secondary
XMC connector P6 at pins A19 and B19. The efault build configuration for this board connects this pair to the
MGT signal inputs. Most needed reference clocks can be generated through the User Programmable clocking
options. If it is a requirement that this differential pair be utilized as a clock signal to an MGT bank, a resistor fit
option is available. Please contact Alpha ata for detials.
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3.4.4 AUXCLK
Auxiliary Clock. This clock is a direct input to the target FPGA. In OpenVPX this clock line is used for 1PPS
synchronization signaling.
Signal Target FPGA Input IO Standard "P" pin "N" pin
1PPS or AUXCLK IO_L9_MRCC_33 LV S AV21 AW21
Table 6 : AUXCLK Connections
3.4.5 Programmable Clocks (LCLK, PROGCLK 0-3)
There are two programable clock sources that are forwarded throughout the FPGA. These clocks are
programmable through the Alpha ata A M-XRC Gen 3 S K. LCLK is generated in the Bridge FPGA by the the
Alpha ata A B3 driver and offers a less accurate frequency resolution, but with a wider programmable
frequency range. PROGCLK[3:0] is generated by a dedicated programmable clock generator IC and offer
extremely high frequency resolutions (1ppm increments). PROGCLK[3:0] is generated by a single source and
buffered to all MGT tiles.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
LCLK 5 - 700 MHz IO_L13_MRCC_14 LV S AJ32 AK32
PROGCLK0 5 - 312.5 MHz MGTREFCLK1_113 LV S AK8 AK7
PROGCLK1 5 - 312.5 MHz MGTREFCLK1_115 LV S AB8 AB7
PROGCLK2 5 - 312.5 MHz MGTREFCLK1_117 LV S M8 M7
PROGCLK3 5 - 312.5 MHz MGTREFCLK1_119 LV S C10 C9
Table 7 : PROGCLK Connections
3.4.6 Module-Carrier Global Clock (GCLK_M2C)
The clock "GCLK_M2C" is a differential clock signal using LV S. It is provided by an XRM module through the
XRM connector, CN1, at pins 110 & 108. It is connected to an MRCC input on the Target FPGA.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
GCLK_M2C Variable IO_L13_T2_MRCC_17 LV S AF39 AF40
Table 8 : GCLK_M2C Connections
3.4.7 Module-Carrier MGT Clock (MGTCLK_M2C)
The reference clock "MGTCLK_M2C" is a differential clock signal using LV S. The clock is provided by an XRM
module through the XRM connector, CN1, at pins 109 & 111. It is first buffered and fanned out, then connected
to GTX Quads 113 and 114 on the Target FPGA for application specific frequencies / line rates.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
MGTCLK_M2C Variable MGTREFCLK0_113 LV S AH8 AH7
MGTCLK_M2C Variable MGTREFCLK0_114 LV S A 8 A 7
Table 9 : MGTCLK_M2C Connections
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3.4.8 XRM LVDS Clock (XRM_LVDS_CLK)
The clock "XRM_LV S_CLK" is a differential clock signal using LV S levels. The clock is provided by the target
FPGA and connected to an XRM module through the XRM connector, CN1, at pins 113 & 115.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
XRM_PECL_CLK Variable IO_L13_T2_MRCC_15 LV S AV40 AW40
Table 10 : XRM_LVDS_CLK Connections
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3.5 Flash Memory
A 512Mb Flash Memory (Intel / Numonyx PC28F512P30EF) is used to store board Vital Product ata (VP ),
programmable clock parameters and configuration bitstreams for the Bridge and Target FPGAs.
The flash memory cannot be accessed by the target FPGA. Host access is only possible through the FLCTL,
FLPAGE and FL ATA registers in the Bridge FPGA.
The region of memory between addresses 0x11000000 and 0x11FFFFF is allocated for custom data to be stored
by the A A-VPX3-7V1 user.
Utilities for erasing, programming and verification of the flash memory are provided in the A MXRC S K.
Write Protect
The Flash Write Protect (WP#) pin is connected to an inverted version of the NVMRO signal at the XMC
interface. When the NVMRO signal is active (High), all writes to the flash will be inhibited. This state will be
indicated by the Amber LE as shown in Figure XMC LE Locations.
0x0000_0000
0x007F_FFFF
Alternate Bridge FPGA Bitstream
Default Bridge FPGA Bitstream
0x0080_0000
0x00FF_FFFF
0x0100_0000
0x010F_FFFF
B0 Length(7:0) Boot Flag 0
Bitstream 0 Length(23:8)
reser ed
Default Target FPGA Bitstream
(Target Bitstream 0)
0x0122_0000
0x028F_FFFF
0x0120_0000
0x0120_0002
B1 Length(7:0) Boot Flag 1
Bitstream 1 Length(23:8)
reser ed
Alternate Target FPGA Bitstream
(Target Bitstream 1)
0x0292_0000
0x03FF_FFFF
0x0290_0000
0x0290_0002
0x0110_0000
0x011F_FFFF
Alpha Data Vital Product Data
(Alpha Data VPD)
User Vital Product Data
(User VPD)
Figure 6 : Flash Memory Map
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3.6 Configuration
3.6.1 Power-Up Sequence
If valid data is stored in the flash memory, the bridge will automatically configure the Target FPGA at power-up.
This sequence can be inhibited by turning the Flash Boot Inhibit (FBI) switch, SW1-5 to ON. (See Table XMC
SW1 efinitions).
Note:
If an over-temperature alert is detected from the System Monitor, the target will be cleared by pulsing its
PROG signal. See Section Automatic Temperature Monitoring.
3.6.2 Bridge-Less Mode
When operating in bridgeless mode, the Target FPGA will be configured directly by a Quad SPI connection to a
1Gb FLASH memory device. This memory device is re-programable over a Xilinx JTAG cable.
This mode is not available in Revision 2 and earlier boards.
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ADA-VPX3-7V1 User Manual
V2.1 - 6th anuary 2016
3.7 Health Monitoring
The A A-VPX3-7V1 has the ability to monitor temperature and voltage to maintain a check on the operation of
the board. The monitoring is implemented using the ATMEGA128 microcontroller.
Control algorithms within the microcontroller automatically check line voltages and on board temperaturs and
shares the information with blockram in the Bridge FPGA.
The following voltage rails and temperatures are monitored:
Monitor Purpose
1.0V FPGA Core Supply (VccINT)
1.0V Target Tranceiver Power (AVCC)
1.0V Bridge Tranceiver Power (AVCC)
1.2V Target Tranceiver Power (AVTT)
1.2V Bridge Tranceiver Power (AVTT)
1.5V R3 S RAM, Target FPGA memory I/O
XRM_VIO (Front-Panel) I/O voltage
1.8V Target Tranceiver Power (AVCC_AUX)
1.8V Flash Memory, FPGA IO Voltage (VCCO)
2.0V Target FPGA Auxiliary Supply AUX (VccAUX)
2.5V Level Translation, Bridge FPGA Auxiliary Supply
(VccAUX)
3.3V Board Input Supply
5.0V Internally generated 5V supply
VPWR Board Input Supply (either 5.0V or 12.0V)
Temp1 Target FPGA on-die temperature
Temp2 Board temperature sensor on-die temperature
Temp3 Bridge FPGA on-die temperature
Table 11 : Voltage and Temperature Monitors
An example application that reads the system monitor ("sysmon") is available within the S K.
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3.7.1 Automatic Temperature Monitoring
At power-up, the control logic sets the temperature limits and resets the LM87's over-temperature interrupt.
The temperature limits are shown in Table Temperature Limits:
.Target FPGA Bridge FPGA Board
Min Max Min Max Min Max
Commercial 0 degC +85 degC 0 degC +85 degC 0 degC +85 degC
Extended 0 degC +100 degC 0 degC +100 degC 0 degC +100 degC
Industrial -40 degC +100 degC -40 degC +100 degC -40 degC +100 degC
Table 12 : Temperature Limits
Important:
If any temperature limit is exceeded, the Target FPGA is automatically cleared. This is indicated by the Green
LE (Target Configured) switching off and the two status LE s showing a temperature fault indication.
The purpose of this mechanism is to protect the card from damage due to over-temperature. It is possible that it
will cause the user application and, possibly, the host computer to "hang".
3.7.2 Microcontroller Status LEDs
LE s XMC- 7 (Red) and XMC- 8 (Green) indicate the microcontroller status.
LE s Status
Green Running and no alarms
Green + Red Standby (Powered off)
Flashing Green + Flashing Red
(together) Attention - critical alarm active
Flashing Green + Flashing Red
(alternating) Service Mode
Flashing Green + Red Attention - alarm active
Red Missing application firmware or
invalid firmware
Flashing Red FPGA configuration cleared to
protect board
Table 13 : Status LED Definitions
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