Alpha Data ADM-SDEV-CFG1 User manual

ADM-SDEV-CFG1
User Manual
Document Revision: 1.2
18t Marc 2020

ADM-SDEV-CFG1 User Manual
V1.2 - 18t Marc 2020
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ADM-SDEV-CFG1 User Manual
V1.2 - 18t Marc 2020
able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 References & S ecifications .......................................................................................................... 2
2 Installation ........................................................................................................................................ 3
2.1 Software Installation ...................................................................................................................... 3
2.2 Hardware Installation ..................................................................................................................... 3
2.2.1 Handling Instructions ................................................................................................................. 3
2.2.2 Configuration FMC Board .......................................................................................................... 3
3 Functional Description .................................................................................................................... 4
3.1 Overview ........................................................................................................................................ 4
3.1.1 LED Definitions .......................................................................................................................... 4
3.2 JTAG Interface ............................................................................................................................... 5
3.2.1 On-board Interface ..................................................................................................................... 5
3.2.2 JTAG Voltages ........................................................................................................................... 5
3.3 Clocks ............................................................................................................................................ 6
3.4 IPASS Connector ........................................................................................................................... 6
3.5 SATA Connectors ........................................................................................................................... 6
3.6 Health Monitoring ........................................................................................................................... 6
3.7 GPIO Loo back ............................................................................................................................. 7
List of ables
able 1 References ........................................................................................................................................ 2
able 2 LED Definitions .................................................................................................................................. 5
able 3 Input CLK_M2C Connections ............................................................................................................ 6
able 4 Output Clock Connection ................................................................................................................... 6
able 5 IPASS PCIe Connections .................................................................................................................. 6
able 6 SA A Connections ............................................................................................................................. 6
List of Figures
Figure 1 ADM-SDEV-CFG1 op and Bottom Views ......................................................................................... 1
Figure 2 ADM-SDEV-CFG1 Block Diagram ..................................................................................................... 4
Figure 3 LED Locations ................................................................................................................................... 4
Figure 4 J AG Boundary Scan Chain .............................................................................................................. 5

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1 Introduction
he ADM-SDEV-CFG1 configuration module board forms part of the ADA-SDEV-KI 1 space FPGA
development kit.
he ADM-SDEV-CFG1 board connects to the configuration FMC socket of the ADM-SDEV-BASE board, allowing
the Xilinx tools to interrogate and configure its FPGA.
Figure 1 : ADM-SDEV-CFG1 Top and Bottom Views
1.1 Key Features
Key Features
• 1x FMC form factor configuration interface
• 2x 256MB QSPI Flash devices, connected to the configuration bank of the Base board FPGA
• IPASS Connector, allowing remote PCIe connection to the Base board FPGA
• A J AG header to allow Vivado Hardware Manager configuration and debug
• USB connection to the Base boards system monitor, to allow reporting of system monitor values
• 2x SA A sockets, allows access to 2 high speed serial lanes of the Base board FPGA.
• Fixed LVDS clock output to the Base board FPGA.
• 2x UFL connectors, allows an external clock to be transmitted / received / looped back by the Base board
FPGA.
• GPIO loopbacks on the remaining FMC signals.
Page 1Introduction
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1.2 References & Specifications
ANSI/VI A 57.1 FPGA Mezzanine Card (FMC) Standard, July 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 57.4 FPGA Mezzanine Card Plus(FMC+) Standard, March 2016, VI A, Draft
Table 1 : References
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2 Installation
2.1 Software Installation
Please refer to the ADA-SDEV-KI 1 area on the Alpha-Data support site for access to system monitoring utilities,
documentation and FPGA reference designs.
2.2 Hardware Installation
2.2.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
2.2.2 Configuration FMC Board
Prior to applying power to the ADM-SDEV-BASE board, the ADM-SDEV-CFG1 board should be fitted into the
Config FMC Socket (J2).
it is recommended that the PMC keying pillar should be fitted to the ADM-SDEV-BASE board. his will ensure
that only an ADM-SDEV-CFG1 can be fitted to the config FMC Socket.
Page 3Installation
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3 Functional Description
3.1 Overview
USB
SOCKET
FMC CONNECTOR
DP_(3:2)
SATA
Connector
(x2)
SYSMON USB
PCIe
IPASS
Connector
DP_(0) JTAG
XILINX
JTAG
SOCKET
I2C
EEPROM
I2C
QSPI
F ash
256M x2
CONFIG BUS
C ock
Generator
CLK1_M2C
C ock
Output
Connector
DP_(1)
C ock
Input
Connector
CLK0_M2C
POWER
GPIO
Loopbacks
LA_(16:0)
LA_(33:17)
CONFIG GPIO CLOCKS HSSIO
Figure 2 : ADM-SDEV-CFG1 Block Diagram
3.1.1 LED Definitions
he position and description of the board status LED is shown in LED Locations:
D1
Figure 3 : LED Locations
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Comp. Ref. Function ON State Off State
D1(Green) 3.3V Supply
Status Normal operation Power Off
Table 2 : LED Definitions
3.2 JTAG Interface
3.2.1 On-board Interface
he J AG boundary scan chain can be accessed via a standard header (J2).
his allows the connection of the Xilinx J AG cable for FPGA debug and QSPI Flash programming via the Xilinx
toolchain.
he J AG chain starts on the config FMC board and through the Base board, passing through the FPGA, the
LPC FMC (if fitted) and the FMC+ (if fitted).
he scan chain is shown in J AG Boundary Scan Chain:
FPGA
XCKU060
LPC
FMC
(J1)
FMC1_PRESENT#
Level Shift
FMC2_VIO –> 3V3
En#
FMC1_TDI
FMC1_TDO
FPGA_TDI
HDR_TDO
Level Shift
3V3 -> FMC2_VIO
FMC2_TDI
FMC2_TDO
Config
FMC
(J2)
FMC+
(J3)
FMC3_PRESENT#
Level Shift
FMC2_VIO –> 3V3
En#
FMC3_TDI
FMC3_TDO
FPGA_TDO
Figure 4 : JTAG Boundary Scan C ain
3.2.2 JTAG Voltages
he Vcc supply provided to the J AG cable on the config header is +3.3V and is protected by a poly fuse rated at
375mA.
he voltage level of the J AG chain on the ADM-SDEV-BASE board is set to the config FMC adjustable voltage
FMC2_VIO.
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3.3 Clocks
he ADM-SDEV-CFG1 board can provide two different clock sources to the Base board FPGA.
One clock source is generated by an on board oscillator and the other can be input via connector J4.
Source Signal Frequency FPGA Input IO
Standard "P" pin "N" pin
External (J5) CLK2_M2C_0 Variable Bank 24 LVDS AM32 AN32
Oscillator CLK2_M2C_1 150MHz Fixed Bank 24 LVDS AM31 AN31
Table 3 : Input CLK_M2C Connections
he ADM-SDEV-CFG1 board can also output a clock signal via connector J4.
his clock is generated by the FPGA on the base board.
Source Signal Frequency FPGA Input IO
Standard "P" pin "N" pin
FPGA DP1_C2M_1 Variable MG Quad 224 LVDS AV6 AV5
Table 4 : Output Clock Connection
3.4 IPASS Connector
One of the high speed serial lanes is connected to an IPASS connector for remote PCIe connection.
Connector Signal FPGA Bank "P" pin "N" pin
IPASS (J6)
DP0_C2M MG Quad 224 AW8 AW7
DP0_M2C MG Quad 224 AW4 AW3
GB CLK0_M2C MG Quad 224 A 10 A 9
Table 5 : IPASS PCIe Connections
3.5 SATA Connectors
he ADM-SDEV-CFG1 board has two standard right angle SA A receptacles for use with SA A compliant
storage devices.
Connector Signal FPGA Bank "P" pin "N" pin
SA A_1 (J7) DP2_C2M MG Quad 224 AU8 AU7
DP2_M2C MG Quad 224 AU4 AU3
SA A_2 (J8) DP3_C2M MG Quad 224 A16 A15
DP3_M2C MG Quad 224 A12 A11
Table 6 : SATA Connections
3.6 Healt Monitoring
he ADM-SDEV-BASE has the ability to monitor temperature and voltage to maintain a check on the operation
of the board. he monitoring is implemented using the Atmel AVR microcontroller.
he system monitor microcontroller can be accessed via the USB connector (J3), please refer to the
Page 6 Functional Description
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ADM-SDEV-BASE user manual for more information.
3.7 GPIO Loopback
Many of the unused FMC GPIO signals are looped back on the ADM-SDEV-CFG1 board for test purposes.
Page 7Functional Description
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ADM-SDEV-CFG1 User Manual
V1.2 - 18t Marc 2020
Revision History
Date Revision Nature of Change
12 Sep 2018 0.1 Initial Draft
21 Nov 2018 0.2 Updated LED definition
27 Nov 2018 1.0 First Release
13 May 2019 1.1 Removed reference to CDROM in section 2.1
18 Mar 2020 1.2 Corrected typos
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
elephone: [phone]
Fax: [phone]
email: [email protected]
website: http://www.alpha-data.com
Address: 611 Corporate Circle, Suite H
Golden, CO 80401
elephone: [phone]
Fax: [phone] - toll free
email: [email protected]
website: http://www.alpha-data.com
5.0