Alpha Data ADM-SDEV-BASE/XCKU060 User manual

ADM-SDEV-BASE/XCKU060
User Manual
Document Revision: .0
27th November 20 8

ADM-SDEV-BASE/XCKU060 User Manual
V .0 - 27th November 20 8
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ADM-SDEV-BASE/XCKU060 User Manual
V .0 - 27th November 20 8
Table Of Contents
Introduction ......................................................................................................................................
1.1 Key Features .................................................................................................................................
1. References & Specifications ..........................................................................................................
1.3 Environmental & Specifications .....................................................................................................
2 Installation ........................................................................................................................................ 3
.1 Software Installation ...................................................................................................................... 3
. Hardware Installation ..................................................................................................................... 3
. .1 Handling Instructions ................................................................................................................. 3
. . Power Supply ............................................................................................................................. 3
. .3 Cooling Requirements ............................................................................................................... 3
. .4 Configuration FMC Board .......................................................................................................... 3
3 Functional Description .................................................................................................................... 4
3.1 Overview ........................................................................................................................................ 4
3.1.1 Switch Definitions ...................................................................................................................... 5
3.1. LED Definitions .......................................................................................................................... 6
3. JTAG Interface ............................................................................................................................... 7
3. .1 On-board Interface ..................................................................................................................... 7
3. . JTAG Voltages ........................................................................................................................... 7
3.3 Clocks ............................................................................................................................................ 8
3.3.1 Reference Clocks (REFCLK400M and FABRIC_CLK) .............................................................. 9
3.3. Programmable Clocks (PROGCLK0 and PROGCLK1) ............................................................. 9
3.3.3 Module to Carrier Global Clocks (CLK_M C) ............................................................................ 9
3.3.4 Module to Carrier MGTREF Clocks (GBTCLK_M C) .............................................................. 10
3.4 Configuration ................................................................................................................................ 11
3.4.1 Configuration From ADM-SDEV-CFG1 Flash Memory ............................................................ 11
3.4.1.1 Building and Programming Configuration Images ............................................................... 11
3.4. Configuration via JTAG ............................................................................................................ 1
3.5 Health Monitoring ......................................................................................................................... 13
3.5.1 Automatic Temperature Monitoring .......................................................................................... 14
3.5. Microcontroller Status LEDs .................................................................................................... 14
3.6 FPGA ........................................................................................................................................... 15
3.6.1 I/O Bank Voltages .................................................................................................................... 15
3.6. Target MGT Links .................................................................................................................... 15
3.7 Memory Interfaces ....................................................................................................................... 17
3.8 FMC Interfaces ............................................................................................................................ 18
3.8.1 Low Pin Count (LPC) FMC, J1 ................................................................................................ 18
3.8. Configuration FMC, J ............................................................................................................. 18
3.8.3 High Pin Count FMC+, J3 ........................................................................................................ 18
List of Tables
Table 1 References ........................................................................................................................................ 2
Table 2 Switch efinitions .............................................................................................................................. 5
Table 3 LE efinitions .................................................................................................................................. 6
Table 4 R REFCLK Connections ............................................................................................................... 9
Table 5 PROGCLK0 Connections .................................................................................................................. 9
Table 6 PROGCLK1 Connections .................................................................................................................. 9
Table 7 CLK_M2C Connections ................................................................................................................... 10
Table 8 GCLK_M2C Connections ................................................................................................................ 10
Table 9 Voltage and Temperature Monitors .................................................................................................. 13

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Table 10 Temperature Limits .......................................................................................................................... 14
Table 11 Status LE efinitions ..................................................................................................................... 14
Table 12 Target FPGA IO Banks .................................................................................................................... 15
Table 13 Target MGT Links ............................................................................................................................ 15
Table 14 LPC FMC Groups (J1) ..................................................................................................................... 18
Table 15 Config FMC Groups (J2) .................................................................................................................. 18
Table 16 FMC+ Groups (J3) ........................................................................................................................... 18
List of Figures
Figure 1 A M-S EV-BASE/XCKU060 Top View ............................................................................................. 1
Figure 2 A M-S EV-BASE/XCKU060 Block iagram .................................................................................... 4
Figure 3 LE Locations ................................................................................................................................... 6
Figure 4 JTAG Boundary Scan Chain .............................................................................................................. 7
Figure 5 Clocks ................................................................................................................................................ 8
Figure 6 Flash Address Map .......................................................................................................................... 11
Figure 7 MGT Links ....................................................................................................................................... 16
Figure 8 RAM Banks ................................................................................................................................... 17

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Introduction
The ADM-SDEV-BASE/XCKU060 shall be the base board at the core of the A A-S EV-KIT1 space FPGA
development kit, enabling customers interested in space grade FPGAs to prototype their applications on a
compatible XCKU060-1I device.
LPC
FMC
Socket
CONFIG
FMC
Socket
KU060
FPGA
HPC
FMC+
Socket
DDR3
SODIMM
Socket
ATX
Power
Connector
Switches
Figure : ADM-SDEV-BASE/XCKU060 Top View
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. Key Features
Key Features
• Custom Form Factor
• Modular design structure
• Powered via an external power supply
• Fitted with XCKU060-1FFVA1517I FPGA device as standard
• PCB footprint compatible with QRKU060-CNA1509 (Contact factory for details)
• 1x FMC+ HPC and 1x FMC LPC interfaces
• 1x FMC form factor configuration interface - clearly labelled "XRTC-Standard Config-FMC Only"
• R3 (with ECC) SO IMM connector to banks 66,67,68 for R3 support
• A JTAG header to allow Vivado Hardware Manager configuration and debug (requires A M-S EV-CFG1
board)
• Programmable clock generation, controlled by I2C connected to the FMC config daughter base board and
the FPGA
• Heatsink and Fan on top of KU060 FPGA
.2 References & Specifications
ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard, July 2008, VITA, ISBN 1-885731-49-3
ANSI/VITA 57.4 FPGA Mezzanine Card Plus(FMC+) Standard, March 2016, VITA, raft
Table : References
.3 Environmental & Specifications
The operational temperature range of the A A-S EV-BASE board is outlined in Temperature Limits.
Note: The A A-S EV-KIT1 is designed for use as a development platform only, is not a space graded platform
and is not suitable for flight or radiation testing.
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2 Installation
2. Software Installation
Please refer to the A A-S EV-KIT1 area on the Alpha- ata support site for access to system monitoring utilities,
documentation and FPGA reference designs.
2.2 Hardware Installation
2.2. Handling Instructions
The components on this board can be damaged by electrostatic discharge (ES ). To prevent damage, observe
SS precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ES safe bag.
2.2.2 Power Supply
The base board is designed to be powered via an external ATX power supply, connected via the standard 24-pin
ATX12V 2.x power connector J5.
This external ATX power supply must be capable of providing a minimum of 20A (100W) on the +5V rail.
In its default configuration the A A-S EV-BASE board draws all of its power from the +5V rail.
Some ATX power supplies may not operate without a minimum load on the +3.3V rail, which will require a
configuration change on the A A-S EV-BASE board. Please contact the factory for further details.
2.2.3 Cooling Requirements
The power dissipation of the board is highly dependent on the Target FPGA application. A power estimator
spreadsheet is available on request from Alpha ata. This should be used in conjunction with Xilinx power
estimation tools to determine the exact current requirements for each power rail.
The board is supplied with an active air cooled heatsink.
The board features system monitoring that measures the board and FPGA temperature. It also includes a
self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is
detected.
See Section 3.5 for further details.
2.2.4 Configuration FMC Board
Prior to applying power the configuration FMC board (A M-S EV-CFG1 or similar) should be fitted into the
Config FMC Socket (J2).
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3 Functional Description
3. Overview
XCKU060-FFVA1517-1-I
Or
XQRKU060-CNA1509
FMC+
#3
HPC
FMC
#1
LPC
Q227
Q228
Q224
Q225
Q226
Q128
Q127
Q126
J AG
45
44
66 67 68
47
24
48
25
46
64 65
x2
x4
x4
x3
x4
x4
x4
x4
x1
Power
Supplies
Programmable
Clock
Generator
DDR3 SODIMM
FMC #2 Config
x4
Serial IO
IPASS PCIe x1
2x SA A
Clock SMA
System
Monitor
USB
QSPI
Figure 2 : ADM-SDEV-BASE/XCKU060 Block Diagram
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3. . Switch Definitions
There is a sliding switch situated on the bottom right corner of the board, plus a set of eight IP switches and a
push button switch placed on the top right corner of the board. Their functions are described in Switch
efinitions.
Note:
All switches are OFF by default. Factory Configuration switch must be in the OFF position for normal
operation.
Switch Ref. Function ON State Off State
SW1 (push
button) Reset System Reset Normal Operation
SW2-1 Reserved - Normal Operation
SW2-2 Reserved - Normal Operation
SW2-3 Config isable Configuration of the FPGA is disabled. Normal Operation.
SW2-4 FPGA User 1 -
FPGA Bank 64 User defined User defined.
SW2-5 FPGA User 2 -
FPGA Bank 24 User defined User defined.
SW2-6 Reserved - Normal Operation
SW2-7 Factory
Configuration - Normal Operation
SW2-8 Reserved - Normal Operation
SW3 (sliding) POWER ON/
OFF PSU ON (position A) PSU OFF (position B)
Table 2 : Switch Definitions
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3. .2 LED Definitions
The position and description of the board status LE s are shown in LE Locations:
D1 D2 D3 D4 D5 D6 D7
Figure 3 : LED Locations
Comp. Ref. Function ON State Off State
1(Green) Status 0 See Status LE efinitions
2(Red) Status 1 See Status LE efinitions
3(Red) Internal Power
Fault Internal Power supply fault Normal operation
4(Green) FPGA one FPGA is configured FPGA is unconfigured
5(Red) Reserved for
future use - -
6(Green) Reserved for
future use - -
7(Green) ATX PSU
Status Normal operation ATX PSU Off
Table 3 : LED Definitions
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3.2 JTAG Interface
3.2. On-board Interface
A JTAG boundary scan chain can be accessed via a standard connector on the config FMC (J2). This allows the
connection of the Xilinx JTAG cable for FPGA debug using the Xilinx toolchain.
The JTAG chain starts on the config FMC board and passes through the FPGA, the LPC FMC (J1) (if fitted) and
the FMC+ (J3) (if fitted).
The scan chain is shown in JTAG Boundary Scan Chain:
FPGA
XCKU060
LPC
FMC
(J1)
FMC1_PRESENT#
Level Shift
FMC2_VIO –> 3V3
En#
FMC1_TDI
FMC1_TDO
FPGA_TDI
HDR_TDO
Level Shift
3V3 -> FMC2_VIO
FMC2_TDI
FMC2_TDO
Config
FMC
(J2)
FMC+
(J3)
FMC3_PRESENT#
Level Shift
FMC2_VIO –> 3V3
En#
FMC3_TDI
FMC3_TDO
FPGA_TDO
Figure 4 : JTAG Boundary Scan Chain
At each stage the clock signal on this JTAG interface (TCK) has a parallel termination (49.9Ω + 22pF to ground)
located at the far end of the line.
3.2.2 JTAG Voltages
The Vcc supply provided to the JTAG cable on the config FMC is +3.3V and is protected by a poly fuse rated at
375mA.
The JTAG signals on all of the FMC boards use 3.3V signals and are connected through level translators to the
A M-S EV-BASE board scan chain.
The voltage level of the JTAG chain on the A M-S EV-BASE board is set to the config FMC adjustable voltage
FMC2_VIO.
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3.3 Clocks
The ADA-SDEV-BASE board provides a wide variety of clocking options. In addition to the and clocks routed
from the FMC connectors, the board has 2 user-programmable clock generators. These clocks can be combined
with the FPGA's internal PLLs to suit a wide variety of communication protocols.
A complete overview of the clock routing on the ADA-SDEV-BASE is given in Clocks. A description of each
clock follows.
Ultrascale
MGT/ Banks
MGT228
REFCLK0
REFCLK1
MGT227
REFCLK0
REFCLK1
MGT226
REFCLK0
REFCLK1
MGT225
REFCLK0
REFCLK1
MGT224
REFCLK0
REFCLK1
MGT128
REFCLK0
REFCLK1
MGT127
REFCLK0
REFCLK1
User
Pr grammable
S urce 0
MGT126
REFCLK0
REFCLK1
Bank 67
(DDR
Banks
66,67,68)
Bank 25
Bank 46
200MHz
S urce
400MHz
S urce
FABRIC_CLK
REFCLK_400
Bank 44
Bank 45
Bank 24
Bank 64
Bank 65
Bank 47
Bank 48
User
Pr grammable
S urce 1
LPC
FMC
(J1)
CFG
FMC
(J2)
FMC+
(J3)
CLK1_M2C_0/1
PROGCLK0
PROGCLK1
GBTCLK1_0_M2C
CLK2_M2C_0/1
CLK2_M2C_2/3
GBTCLK2_0_M2C
CLK3_M2C_0/1
CLK3_M2C_2/3
GBTCLK3_3_M2C
GBTCLK3_4_M2C
GBTCLK3_5_M2C
GBTCLK3_0_M2C
GBTCLK3_1_M2C
GBTCLK3_2_M2C
Figure 5 : Clocks
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3.3. Reference Clocks (REFCLK400M and FABRIC_CLK)
The fixed reference clocks REFCLK400M and FABRIC_CLK are differential HSTL signals.
REFCLK400M is used as the input clock for the R S RAM interface.
FABRIC_CLK is used as the reference clock for the IO delay control block (I ELAYCTRL).
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
REFCLK400M 400 MHz IO BANK 67 HSTL H18 H17
FABRIC_CLK 200 MHz IO BANK 67 HSTL H19 G19
Table 4 : DDR REFCLK Connections
3.3.2 Programmable Clocks (PROGCLK0 and PROGCLK )
There are two programable clock sources that are forwarded throughout the FPGA. These clocks are
programmable through the Alpha ata A A-S EV-BASE S K. PROGCLK0 and PROGCLK1 are generated by a
dedicated programmable clock generator IC and offer extremely high frequency resolutions (1ppm increments).
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
PROGCLK0[0] 5 - 400 MHz IO BANK 45 LV S AL27 AL28
PROGCLK0[1] 5 - 400 MHz MGTREFCLK1_224 LV S AP10 AP9
PROGCLK0[2] 5 - 400 MHz MGTREFCLK1_127 LV S V32 V33
PROGCLK0[3] 5 - 400 MHz IO BANK25 LV S AN36 AN37
Table 5 : PROGCLK0 Connections
Note: PROGCLK0[3:0] are all buffered copies of the same clock signal. The default (factory set) frequency of
PROGCLK0 = 400MHz.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
PROGCLK1[0] 5 - 400 MHz MGTREFCLK1_225 LV S AK10 AK9
PROGCLK1[1] 5 - 400 MHz IO BANK 64 LV S AP19 AP18
PROGCLK1[2] 5 - 400 MHz IO BANK 48 LV S J26 H26
PROGCLK1[3] 5 - 400 MHz MGTREFCLK1_226 LV S AC8 AC7
Table 6 : PROGCLK Connections
Note: PROGCLK1[3:0] are all buffered copies of the same clock signal. The default (factory set) frequency of
PROGCLK1 = 150MHz.
3.3.3 Module to Carrier Global Clocks (CLK_M2C)
Each connected FMC board can generate a number of differential Global clocks (as per the FMC standard).
They each connect to an global clock input on the FPGA.
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FMC Signal Frequency FPGA Input IO Standard "P" pin "N" pin
1 CLK1_M2C_0 Variable Bank 44 LV S AM22 AN22
1 CLK1_M2C_1 Variable Bank 44 LV S AM21 AN21
2 CLK2_M2C_0 Variable Bank 24 LV S AM32 AN32
2 CLK2_M2C_1 Variable Bank 24 LV S AM31 AN31
2 CLK2_M2C_2 Variable Bank 64 LV S AL19 AL18
2 CLK2_M2C_3 Variable Bank 64 LV S AL17 AM17
3 CLK3_M2C_0 Variable Bank 46 LV S H36 G36
3 CLK3_M2C_1 Variable Bank 46 LV S G37 F37
3 CLK3_M2C_2 Variable Bank 47 LV S F32 E32
3 CLK3_M2C_3 Variable Bank 47 LV S F33 E33
Table 7 : CLK_M2C Connections
3.3.4 Module to Carrier MGTREF Clocks (GBTCLK_M2C)
Each connected FMC board can generate a number of differential MGT Reference clocks (as per the FMC
standard). They each connect to an MGTREFCLK input on the FPGA.
FMC Signal Frequency FPGA Input IO Standard "P" pin "N" pin
1 GBTCLK1_0_M2C Variable MGTREFCLK_225 LV S AM10 AM9
2 GBTCLK2_0_M2C Variable MGTREFCLK_224 LV S AT10 AT9
3 GBTCLK3_0_M2C Variable MGTREFCLK_226 LV S AH10 AH9
3 GBTCLK3_1_M2C Variable MGTREFCLK_227 LV S AE8 AE7
3 GBTCLK3_2_M2C Variable MGTREFCLK_228 LV S AA8 AA7
3 GBTCLK3_3_M2C Variable MGTREFCLK_126 LV S A 32 A 33
3 GBTCLK3_4_M2C Variable MGTREFCLK_127 LV S Y32 Y33
3 GBTCLK3_5_M2C Variable MGTREFCLK_128 LV S T32 T33
Table 8 : GCLK_M2C Connections
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3.4 Configuration
There are two main ways of configuring the FPGA on the A M-S EV-BASE:
• From Flash memory on the config FMC board, at power-on, as described in Section 3.4.1
• Using a Xilinx Platform JTAG cable connected to the programming header on the config FMC board
Section 3.4.2
3.4. Configuration From ADM-SDEV-CFG Flash Memory
The FPGA can be automatically configured at power-on from two 256 Mbit QSPI flash memory device configured
as an x8 SPI device (Micron part numbers MT25QU256ABA8E12-1SIT). These flash devices are typically
divided into two regions of 32 MiByte each, where each region is sufficiently large to hold an uncompressed
bitstream for the FPGA.
It is possible to use Multiboot with a fallback image on this hardware. The master SPI configuration interface and
the Fallback MultiBoot are discussed in detail in Xilinx UG570.
The flash address map is as detailed below:
Data Region
Region 0
Default
(32 MiB)
Region 1
Multi-boot
(32 MiB)
Start Address (Bytes)
0x000_0000
0x200_0000
Figure 6 : Flash Address Map
At power-on, the FPGA attempts to configure itself automatically in serial master mode based on the contents of
the header in the programing file. See Xilinx UG570 MultiBoot for details.
Note:
If an over-temperature alert is detected from the System Monitor, the FPGA will be cleared by pulsing its
PROG signal. See Automatic Temperature Monitoring.
3.4. . Building and Programming Configuration Images
Generate a bitfile with these constraints (see xapp1233):
• set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ]
• set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN { IV-1} [current_design]
• set_property BITSTREAM.CONFIG.SPI_32BIT_A R YES [current_design]
• set_property BITSTREAM.CONFIG.SPI_BUSWI TH 8 [current_design]
• set_property BITSTREAM.CONFIG.SPI_FALL_E GE YES [current_design]
• set_property BITSTREAM.CONFIG.UNUSE PIN {Pullnone} [current_design]
• set_property CFGBVS GN [ current_design ]
• set_property CONFIG_VOLTAGE 1.8 [ current_design ]
• set_property BITSTREAM.CONFIG.OVERTEMPSHUT OWN Enable [current_design]
Generate an MCS file with these properties (write_cfgmem):
• -format MCS
• -size 64
• -interface SPIx8
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• -loadbit "up 0x0000000 <directory/to/file/filename.bit>" (0th location)
• -loadbit "up 0x2000000 <directory/to/file/filename.bit>" (1st location, optional)
Program with vivado hardware manager with these settings (see xapp1233):
• SPI part: mt25qu256-spi-x1_x2_x4_x8
• State of non-config mem I/O pins: Pull-none
• Target the four files generated from the write_cfgmem tcl command.
3.4.2 Configuration via JTAG
A Xilinx Platform Programming Cable may be attached to the programming header on the Config FMC board.
This permits the FPGA to be reconfigured using the Xilinx Vivado Hardware Manager via JTAG. The device will
be automatically recognized in Vivado Hardware Manager.
For more detailed instructions, please see “Programming the FPGA evice” section of Xilinx UG908: https://
www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug908-vivado-programming-debugging.pdf
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3.5 Health Monitoring
The ADA-SDEV-BASE has the ability to monitor temperature and voltage to maintain a check on the operation
of the board. The monitoring is implemented using the Atmel AVR microcontroller.
Control algorithms within the microcontroller automatically checks line voltages and on board temperatures.
The following voltage rails and temperatures are monitored:
Monitor Purpose
12.0V Board Input Supply
5.0V Board Input Supply
3.3V Board Input Supply
FMC2_VIO Config FMC I/O voltage
2.5V Level Translation
1.8V FPGA IO Voltage (VCCO)
0.95V Target FPGA Core Supply (VccINT)
1.8V Target Transceiver Power (AVCC_AUX)
1.5V R S RAM, Target FPGA memory I/O
1.2V Target Transceiver Power (AVTT)
1.0V Target Transceiver Power (AVCC)
12.0V Current 12V Supply Current Reading
5.0V Current 5V Supply Current Reading
3.3V Current 3.3V Supply Current Reading
Temp1 micrcontroller on-die temperature
Temp2 Board temperature sensor on-die temperature
Temp3 FPGA on-die temperature
Table 9 : Voltage and Temperature Monitors
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3.5. Automatic Temperature Monitoring
At power-up, the control logic sets the temperature limits and resets the temperature sensor's over-temperature
interrupt.
The temperature limits are shown below :
.FPGA Board
Min Max Min Max
Industrial -40 degC +100 degC -40 degC +100 degC
Table 0 : Temperature Limits
Important:
If any temperature limit is exceeded, the FPGA is automatically cleared. This is indicated by the Green LE
(FPGA Configured) switching off and the two status LE s showing a temperature fault indication.
The purpose of this mechanism is to protect the card from damage due to over-temperature.
3.5.2 Microcontroller Status LEDs
LE s 2 (Red) and 1 (Green) indicate the microcontroller status.
LEDs Status
Green Running and no alarms
Green + Red Standby (Powered off)
Flashing Green + Flashing Red
(together) Attention - critical alarm active
Flashing Green + Flashing Red
(alternating) Service Mode
Flashing Green + Red Attention - alarm active
Red Missing application firmware or
invalid firmware
Flashing Red FPGA configuration cleared to
protect board
Table : Status LED Definitions
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3.6 FPGA
3.6. I/O Bank Voltages
The FPGA IO is arranged in banks, each with their own supply pins. The bank numbers, their voltage and
function are shown in Target FPGA IO Banks. Full details of the IOSTAN AR required for each signal are
given in the A A-S EV-BASE S K.
IO Banks Voltage Purpose
0, 65 FMC2_VIO_B Configuration, JTAG
44, 45 FMC1_VA J LPC FMC GPIO
24, 64 FMC2_VA J Config FMC GPIO
25, 46, 47 FMC3_VA J FMC+ GPIO
48 FMC3_VIO_B FMC+ GPIO
66, 67, 68 1.5V R SO IMM
Table 2 : Target FPGA IO Banks
3.6.2 Target MGT Links
There are a total of 32 Multi-Gigabit Transceiver (MGT) links connected to the FPGA:
Links Width Connection
FMC1_ P(3:0) 4 links to LPC FMC Socket (J1)
FMC2_ P(3:0) 4 links to Config FMC Socket (J2)
FMC3_ P(23:0) 24 links to FMC+ Socket (J3)
Table 3 : Target MGT Links
Note: link FMC2_ P(1) is unavailable on the CNA1509 package device.
The connections of these links are shown in MGT Links:
For MGT Clocking see Clocks:
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Kintex Ultrascale
MGT
MGT126
MGT127
MGT227
MGT226
MGT225
MGT224
Config
FMC
(J2)
FMC+
(J )
MGT128
MGT228
FMC2_DP( :0)
FMC1_DP( :0)
LPC
FMC
(J1)
FMC _DP( :0)
FMC _DP(7:4)
FMC _DP(11:8)
FMC _DP(15:12)
FMC _DP(19:16)
FMC _DP(2 :20)
Figure 7 : MGT Links
Page 6 Functional Description
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