Alpha Data ADM-VPX3-9V2 User manual

ADM-VPX3-9V2
User Manual
Document Revision: 1.2
13th Octo er 2020

ADM-VPX3-9V2 User Manual
© 2020 Copyright Alpha Data Parallel Systems Ltd.
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Data Parallel Systems Ltd.
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All trademarks are the property of their respective owners.

ADM-VPX3-9V2 User Manual
able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 2
2 Board Information ............................................................................................................................ 3
2.1 Physical Specifications .................................................................................................................. 3
2.2 Chassis Requirements ................................................................................................................... 4
2.2.1 PC Express ............................................................................................................................... 4
2.2.2 Mechanical Requirements ......................................................................................................... 4
2.2.3 Power Requirements ................................................................................................................. 4
2.3 Thermal Performance .................................................................................................................... 5
2.4 Customizations .............................................................................................................................. 5
3 Functional Description .................................................................................................................... 6
3.1 Overview ........................................................................................................................................ 6
3.1.1 Switches .................................................................................................................................... 8
3.1.2 LEDs .......................................................................................................................................... 9
3.2 VPX P0 ........................................................................................................................................ 10
3.2.1 Global Address ........................................................................................................................ 10
3.2.2 System Reset .......................................................................................................................... 10
3.2.3 REFCLK ................................................................................................................................... 10
3.2.4 AUXCLK ................................................................................................................................... 10
3.2.5 Management Bus (SM0-SM3) ................................................................................................. 10
3.2.6 NVMRO ................................................................................................................................... 10
3.3 VPX P1 and P2 ............................................................................................................................ 11
3.3.1 Differential Pairs ....................................................................................................................... 11
3.3.2 P1 GD SC1# ............................................................................................................................ 11
3.3.3 VBAT ........................................................................................................................................ 11
3.3.4 SYSCON# ................................................................................................................................ 11
3.3.5 MP01 ........................................................................................................................................ 11
3.3.6 AX_RESETL# .......................................................................................................................... 11
3.3.7 MSKRST# ................................................................................................................................ 11
3.3.8 P2 GP O .................................................................................................................................. 12
3.3.9 MP02 ....................................................................................................................................... 12
3.4 Clocking ....................................................................................................................................... 13
3.4.1 PC e Reference Clock ............................................................................................................. 14
3.4.2 Fabric Clock ............................................................................................................................. 14
3.4.3 Programming Clock (EMCCLK) ............................................................................................... 14
3.4.4 PROGCLK0 Clock ................................................................................................................... 14
3.4.5 PROGCLK1 Clock ................................................................................................................... 14
3.4.6 DDR4 SDRAM Reference Clocks ............................................................................................ 14
3.5 PC Express ................................................................................................................................. 15
3.6 FireFly .......................................................................................................................................... 16
3.7 DDR4 SDRAM ............................................................................................................................. 17
3.8 System Monitor ............................................................................................................................ 18
3.8.1 System Monitor Status LEDs ................................................................................................... 19
3.9 USB nterface .............................................................................................................................. 20
3.10 Configuration ............................................................................................................................... 20
3.10.1 Configuration From Flash Memory .......................................................................................... 20
3.10.1.1 Building and Programming Configuration mages ............................................................... 21
3.10.2 Configuration via JTAG ............................................................................................................ 21
3.11 User EEPROM ............................................................................................................................. 22
Appendix A Complete Pinout Ta le .................................................................................................................. 23

ADM-VPX3-9V2 User Manual
List of ables
able 1 Mechanical Dimensions ..................................................................................................................... 3
able 2 Available Power By Rail ..................................................................................................................... 4
able 3 Switch Functions ................................................................................................................................ 8
able 4 LED Details ........................................................................................................................................ 9
able 5 Voltage, Current, and emperature Monitors ................................................................................... 18
able 6 Status LED Definitions ..................................................................................................................... 19
able 7 Complete Pinout able ..................................................................................................................... 23
List of Figures
Figure 1 ADM-VPX3-9V2 Product Photo ......................................................................................................... 1
Figure 2 ADM-VPX3-9V2 op View ................................................................................................................. 3
Figure 3 hermal Performance ........................................................................................................................ 5
Figure 4 ADM-VPX3-9V2 VU9P Block Diagram .............................................................................................. 6
Figure 5 ADM-VPX3-9V2 VU13P Block Diagram ............................................................................................ 7
Figure 6 ADM-VPX3-9V2 with debug board .................................................................................................... 7
Figure 7 Switches ............................................................................................................................................ 8
Figure 8 Front Panel LEDs .............................................................................................................................. 9
Figure 9 Clock opology ................................................................................................................................ 13
Figure 10 FireFly Location ............................................................................................................................... 16
Figure 11 MPO with Conduction Cooled .......................................................................................................... 16
Figure 12 DDR4 bank locations by index ......................................................................................................... 17

ADM-VPX3-9V2 User Manual
1 Introduction
he ADM-VPX3-9V2 is a 3U VPX embedded high-performance reconfigurable computing card intended for high
speed switch applications. Featuring 28G transceivers in the Xilinx Virtex UltraScale+ Plus FPGA at all VPX P1
and P2 wafers, and two FireFly sites for rugged optical communications.
Figure 1 : ADM-VPX3-9V2 Product Photo
1.1 Key Features
Key Features
• PCIe Gen3 x1, x4, x8, or x16 capable
• Convection and conduction thermal management configuration
• 3U, 4HP VPX form factor
• Four banks of DDR4 SDRAM 72 bit wide memory (ECC), 16GB (4GB per bank) rated at 2666M /s.
• All 32 wafers of P1 and P2 are capable of 28 Gpbs operation (total 896 Gbps)
• 2 FireFly sites each capable of 4x28Gbps operation (total 224 Gbps)
• Option for MPO optical breakout through front panel
• Supports VU9P, VU13P Virtex UltraScale+ FPGAs in the B2104 package
• Debug board fits in 5HP slot profile for easy access to debug switches, LEDs, J AG, and system monitor
• FPGA configurable over J AG and SPI configuration flash
• Voltage, current, and temperature monitoring
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OpenVPX Compliant Slot Profiles
• SL 3-PAY-2F1F2U-14.2.1
• SL 3-PAY-1F2F2U-14.2.2
• SL 3-PAY-1D-14.2.6
• SL 3-PAY-1F1F2U-14.2.4
• SL 3-PAY-2F-14.2.7
• SL 3-PAY-1F4U-14.2.8
• SL 3-PAY-8U-14.2.9
• SL 3-PAY-1F1U-14.2.10
• SL 3-PAY-2F4F2U-14.2.11
• SL 3-PAY-1F2U-14.2.12
• SL 3-PAY-3F2U-14.2.13
• SL 3-PAY-2U2U-14.2.17
• SL 3-PER-2F-14.3.1
• SL 3-PER-1F-14.3.2
• SL 3-PER-1U-14.3.3
• SL 3-PER-1Q-14.3.4
• SL 3-SWH-6F6U-14.4.1
• SL 3-SWH-8F-14.4.2
• SL 3-SWH-2F24U-14.4.3
• SL 3-SWH-4F-14.4.4
• SL 3-SWH-2F8U-14.4.5
• SL 3-SWH-6F8U-14.4.9
• SL 3-SWH-6F8U-14.4.9
1.2 Order Code
See http://www.alpha-data.com/pdfs/adm-vpx3-9v2.pdf for complete ordering options.
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ADM-VPX3-9V2 User Manual
2 Board Information
2.1 Physical Specifications
he ADM-VPX3-9V2 complies with 4HP pitch slot profiles from AV48.1 and AV48.2 respectively
Description Measure
otal Dy 100 mm
PCB Dy 94 mm
otal Dx 171 mm
PCB Dx 160 mm
otal Dz 21.5 mm
Weight (no heat sink) 180g
Ta le 1 : Mechanical Dimensions
Figure 2 : ADM-VPX3-9V2 Top View
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2.2 Chassis Requirements
2.2.1 PCI Express
he ADM-VPX3-9V2 is capable of PCIe Gen 3 with up to 16 lanes, using the Xilinx Integrated Block for PCI
Express.
2.2.2 Mechanical Requirements
A 3U VPX compliant backplane is required for use with this module.
2.2.3 Power Requirements
he ADM-VPX3-9V2 draws power from only VS1 (12V) and the 3.3V auxiliary power. All other power rails are
unused and unconnected.
Power consumption estimation requires the use of the Xilinx XPE spreadsheet and a power estimator tool
available from Alpha Data. Please contact [email protected] to obtain this tool.
he power available to the rails calculated using XPE are as follows:
Voltage Source Name Current Capability
0.85-0.90 VCC_IN + VCCIN _IO + VCC_BRAM 105A
0.9 MG AVCC 7A
1.2 MG AV 12A
1.2 1V2_DIG (DDR4) 12A
1.8 VCCAUX + VCCAUX_IO + VCCO_1.8V 5.5A
1.8 MG VCCAUX 1A
3.3 3.3V (FireFly and logic ICs) 5A
Ta le 2 : Availa le Power By Rail
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ADM-VPX3-9V2 User Manual
2.3 Thermal Performance
If the FPGA core temperature exceeds 105 degrees Celsius, the FPGA design will be cleared to prevent the card
from over-heating.
he ADM-VPX3-9V2 comes with either a convection or conduction heat sink. he only part of the card monitored
for over-temperature shutdown is the FPGA, since it is typically the hottest point on the card. he FPGA die
temperature must remain under 100 degrees Celsius. o calculate the FPGA die temperature in a convection
application, take your application power, multiply by heta JA from the table below, and add to your system
internal ambient temperature. Conduction cards typically perform with a constant theta JC (chassis wall) of BD
degC/W.
Real time power measurements can be taken from the system monitor 12V voltage and current values. See
System Monitor for more details.
he power dissipation can be estimated by using the Alpha Data power estimator in conjunction with the Xilinx
Power Estimator (XPE) downloadable at http://www.xilinx.com/products/technology/power/xpe.html. Download
the UltraScale tool and set the device to Virtex UltraScale+, VU9P or VU13P, B2104 package, -2, Industrial. Set
the ambient temperature to your system ambient and select 'user override' for the effective theta JA and enter
the figure associated with your system LFM in the blank field. Proceed to enter all applicable design elements
and utilization in the following spreadsheet tabs. Next, acquire the 9V2 power estimator from Alpha Data by
contacting [email protected]. You will then plug in the FPGA power figures to get a board level estimate.
Figure 3 : Thermal Performance
2.4 Customizations
Alpha Data provides extensive customization options to existing commercial off-the-shelf (CO S) products.
Some options include, but are not limited to: custom Front IO, enhanced heat sinks, alternate FPGA part number
support, and circuit additions.
See https://www.alpha-data.com/mcots.php for more details.
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ADM-VPX3-9V2 User Manual
3 Functional Description
3.1 Overview
he ADM-VPX3-9V2 is a versatile reconfigurable computing platform with a Virtex UltraScale+ VU9P/VU13P
FPGA, 32 reconfigurable VPX lanes and 8 FireFly lanes all capable of 28G/lane, and four banks of 72 bits wide
(for 64 bits with 8 bits ECC) DDR4 memory. he 9V2 also comes with a compact debug board with LEDs, switch,
programming headers, and easy access to the powerful onboard system monitor features.
he ADM-VPX3-9V2 comes with a front access debug board which includes: 8 user LEDs, 4 status LEDs, DIP
switch, Xilinx J AG programing header, micro usb access to system montior, and factory programing headers.
GPIOGPIO GPIOGPIOGPIOGPIOGPIOGPIO
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
AVR
uC
PWR
Reg
VS1 VS2
P0
VS VS
SM2/
SM0/1
JTAGJTAG
JT
AG
GA
GA
REF AUX
AUX
R N
P1
GD1VBATMSKR SYSC2 2TD2 2RD
P2
JTAG
2 2TD/
GPIO
2 2RD/
GPIO
RSVD RSVD
FireFly
B04
Fat Pipe
Fat Pipe
Fat Pipe
FireFly
B04
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
Fat Pipe
Fat Pipe
Fat Pipe
Fat Pipe
Fat Pipe
SLRSLR
SLR
SLR
SLR
SLR
VU9P
B2104
121
12
40 41 42 64 65 66 67
68 47
224
225
226
227
228
229
2 0
2 1
2 2
2
122
120
124
125
126
127
128
46 48 7170 72
0
SLR
Figure 4 : ADM-VPX3-9V2 VU9P Block Diagram
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ADM-VPX3-9V2 User Manual
GPIOGPIO GPIOGPIOGPIOGPIOGPIOGPIO
SLR
SLR
SLR
SLR
SLR
SLR
SLR
VU13P
B2104
125
127
61 62 63 64 65 66 67
68 70
224
225
226
227
228
229
230
231
232
233
126
124
128
129
130
131
133 69 71 7372 74
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
AVR
C
PWR
Reg
0
VS1 VS2
P0
VS3 VS3
SM2/3
SM0/1
JTAGJTAG
JT
AG
GA
GA
REF AUX
AUX
R N
P1
GD1VBATMSKR SYSC232TD232RD
P2
JTAG
232TD/
GPIO
232RD/
GPIO
RSVD RSVD
FireFly
B04
Fat Pipe
Fat Pipe
Fat Pipe
FireFly
B04
SLR
SLR
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
4GB DDR4-2666
72 bits
(5x 16 bit BGA)
Fat Pipe
Fat Pipe
Fat Pipe
Fat Pipe
Fat Pipe
Figure 5 : ADM-VPX3-9V2 VU13P Block Diagram
Figure 6 : ADM-VPX3-9V2 with de ug oard
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ADM-VPX3-9V2 User Manual
3.1.1 Switches
he ADM-VPX3-9V2 has a quad DIP switch SW1, located on the debug board. he function of each switch in
SW1 is detailed below:
Figure 7 : Switches
Switch Factory
Default Function OFF State ON State
SW1-1 OFF User Switch 0 Net DBG_USER_IN_0 = '1' Net DBG_USER_IN_0 = '0'
SW1-2 OFF Service Mode System Monitor normal
operation System Monitor Service Mode (firmware update etc.)
SW1-3 OFF CLK_SEL Board synchronizes to
onboard 25MHz Board synchronizes to VPX REFCLK 25MHz
SW1-4 OFF Power Off Board will power up Immediately power down
Ta le 3 : Switch Functions
See Section Complete Pinout able for full list of user controlled switch nets and pins
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ADM-VPX3-9V2 User Manual
3.1.2 LEDs
here are 12 LEDs on the ADM-VPX3-9V2 debug board, 8 of which are general purpose and whose meaning
can be defined by the user. hese user LEDs do not have a default value, and could be in any state when the
FPGA is unconfigured, or these pins are unconstrained (i.e. they may be on/off/flickering). he other 4 have fixed
functions described below:
D3
D10 D11
NVMRO STAT_1
D12
STAT_0
Status LEDs
D9
DONE
D2
USER_LED_6_1V8
USER_LED_5_1V8
D4
USER_LED_4_1V8
User LEDs
D1
USER_LED_7_1V8
D7D6
USER_LED_2_1V8
USER_LED_1_1V8
D8
USER_LED_0_1V8
D5
USER_LED_3_1V8
Figure 8 : Front Panel LEDs
Comp.
Ref. Function / Net Name ON State OFF State
D8 USER_LED_0_1V8 User defined '0' User defined '1'
D7 USER_LED_1_1V8 User defined '0' User defined '1'
D6 USER_LED_2_1V8 User defined '0' User defined '1'
D5 USER_LED_3_1V8 User defined '0' User defined '1'
D4 USER_LED_4_1V8 User defined '0' User defined '1'
D3 USER_LED_5_1V8 User defined '0' User defined '1'
D2 USER_LED_6_1V8 User defined '0' User defined '1'
D1 USER_LED_7_1V8 User defined '0' User defined '1'
D9 DONE FPGA is configured FPGA is not configured
D10 NVMRO_L NVMRO signal active NVMRO signal inactive
D11 Status 1 See Status LED Definitions
D12 Status 0 See Status LED Definitions
Ta le 4 : LED Details
See Section Complete Pinout able for full list of user controlled LED nets and pins
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ADM-VPX3-9V2 User Manual
3.2 VPX P0
3.2.1 Glo al Address
All global address pins are available as inputs to the FPGA.
See net names FPGA_GA* in section Complete Pinout able for location details.
3.2.2 System Reset
SYSRESE # provides an input to the FPGA at the dedicated PERS N0 pin for use with PCIe or general resets.
SYSRESE # can also be driven through an open drain buffer by the FPGA at net SYSRESE _OU _L which can
be located in the section Complete Pinout able.
3.2.3 REFCLK
VPX REFCLK is an optional VPX input/output that should be either a 25MHz or a 100MHz reference clock. By
default this clock is forwarded to MG REFCLK0 of quad 224.
When REFCLK is 25MHz, it can be used as the clock source for all internally generated clocks. his is done by
setting SW1-3 on the debug board to ON, or through a build option.
he net REFCLK_OU _EN_1V8 when driven high, will change the external REFCLK transceiver into an output
driver, and forward the net SE_REFCLK_OU _1V8 onto the VPX backplane.
See net names in section Complete Pinout able for location details.
3.2.4 AUXCLK
VPX AUXCLK is an optional VPX input/output that can provide an external reference timing pulse or clock. By
default this clock is forwarded as net name AUXCLK_SE_1V8 GPIO in FPGA bank 64.
he net AUXCLK_DIR_1V8 when driven high, will change the external AUXCLK transceiver into an output driver,
and forward the net AUXCLK_SE_1V8 onto the VPX backplane.
See net names in section Complete Pinout able for location details.
3.2.5 Management Bus (SM0-SM3)
he default build option sends SM0-SM3 to the FPGA for user implementation at net locations
IPMB0_FPGA_SCL, IPMB0_FPGA_SDA, IPMB1_FPGA_SCL, IPMB1_FPGA_SDA found in Complete Pinout
able.
SM0-SM3 are buffered through a L C4309IDE I2C bus level translator to ensure high impedance isolation during
partial power-down.
SM0-SM3 can be controlled by the onboard system management microcontroller, but this requires a small
resistor population change controlled by a build modification.
See net names in section Complete Pinout able for location details.
3.2.6 NVMRO
NVMRO is available as an input at net NVMRO_FPGA.
NVMRO can also be connected to the configuration flash memory through a build option upon request. Note that
this will increase the power-on configuration time for the FPGA by a factor of 2.
See net names in section Complete Pinout able for location details.
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ADM-VPX3-9V2 User Manual
3.3 VPX P1 and P2
3.3.1 Differential Pairs
All differential wafers in P1 and P2 are connected directly to high speed transceivers on the FPGA. hese
connectors use R 3 VPX connectors which are capable of up to 28Gbps line rates. he FPGA is very flexible,
and these 32 lanes can be configured as any combination of 32 ultra-thin-pipes, 16 thin-pipes, 8 fat-pipes, or 4
ultra-fat-pipes as defined in the VPX specifications. hese wafers can support protocols like 100G ethernets,
SRIO, Infiniband, or any other protocol supported directly by the Xilinx G Y ransceivers. Please see Xilinx User
Guide UG578 for more details on the capabilities of the transceivers.
All VPX differential lines (both RX and X) have 220nF AC coupling capacitors in line for the most flexibility.
Alpha Data can change the value of these capacitors, or change them to 0 ohm resistors upon request.
See Overview for quad and wafer mapping. Net nomenclature is shown below:
Wafer connections
• P1 Wafers 1-8: PCIE_*
• P1 Wafers 9-14: P1_*
• P1 Wafer 15: E H2_*
• P1 Wafer 16: E H1_*
• P2 Wafers 1-16: P2_*
See net names in section Complete Pinout able for location details.
3.3.2 P1 GDISC1#
GDiscrete1 is an optional, bidirectional, open drain, IO pin defined in the VPX specification at P1 pin G1. It is
controlled at the FPGA by net GDiscrete1_OU and GDiscrete1_IN, both of which have external pull-ups. An
external open-drain buffer passes and receives logical low signals from the shared backplane bus to the FPGA.
Locations for these net names can be located in section Complete Pinout able.
3.3.3 VBAT
VBA is connected through a resistor divider to the FPGA VBA pin, and can provide voltage to hold encryption
keys for secure boot load.
3.3.4 SYSCON#
he system controller input is buffered and sent to the FPGA as net SYSCON_1V8_L. he ADM-VPX3-9V2 has
some system controller functionality build in (REFCLK, management bus flexibility, SYSRESE control, etc.), and
can perform this function in some chassis.
3.3.5 MP01
he OpenVPX MP01 serial port at P1.G9 and P1.G11 is configurable as either 3.3V UAR (default) or optionally
RS232 signaling levels (with build option). See net names UAR _0_* and RS232_0 in Complete Pinout able for
pin locations.
3.3.6 AX_RESETL#
his input is unused by default, and requires a build option to use this signal.
3.3.7 MSKRST#
he VPX maskable reset is combined with the system reset and sent to the dedicated PERS N0 pin of the
FPGA. his is an ideal way to perform PCIe reset, or general logic resets.
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ADM-VPX3-9V2 User Manual
3.3.8 P2 GPIO
All 8 user defined pins on row G of P2 are controllable through an SN74AVC4 774RSVR bidirectional buffer with
an external pull-up. he buffers are enabled with active low net P2_GPIO_EN_L (there is an external pull-up).
Each line has a directional control pin P2_GPIO_G*_DIR. DIR set high drives a GPIO out onto the backplane,
and logical low receives in from the backplane (there is an external pull-down). Nets P2_GPIO_*_1V8 are the
input/output pins to send and receive data.
MP02 at P1 pins G1 and G3 can be used as a serial 3.3V UAR interface as per OpenVPX when configured with
the appropriate input and output directions.
Locations for these net names can be located in section Complete Pinout able.
3.3.9 MP02
he OpenVPX MP02 serial port at P2.G1 and P2.G3 is configurable as either 3.3V UAR (default) or optionally
RS232 signaling levels (with build option). See net names GPIO_G1_1V8, GPIO_G3_1V8, and RS232_1* in
Complete Pinout able for pin locations.
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ADM-VPX3-9V2 User Manual
3.4 Clocking
he ADM-VPX3-9V2 provides flexible reference clock solutions for the many multi-gigabit transceiver quads and
FPGA fabric. Any programmable clock, from the SI5338 Clock Synthesizer, is re-configurable from the debug
board USB Interface by using Alpha Data’s avr2util utility. his allows the user to configure almost any arbitrary
clock frequency during application run time. he maximum clock frequency is 312.5MHz. Customers who utilize
Alpha Data SDK and API also have the option of embedding IP into their FPGA design that permits
programmable clock re-configuration via PCIe or from within the FPGA.
All clock names in the section below can be found in Complete Pinout able.
FABRIC_CLK 300MHz (IO Bank 66)
25MHz
30ppm
Sourc
Si5338
Clock
Synth
AUXCLK_SE_1V8 (BANK 64)
0
1
2
3
AUXCLK_DIR_1V8 (BANK 64)
VPX
REFCLK
M-LVDS Buff r
SN65MLVD201DR
Buff r
CDCLVD110ARHBT
PROGCLK_0
All Conn ct d MGTs
MGTREFCLK0 ( xc pt 224)
REFCLK300M_0 (BANK 61)
VPX
AUXCLK
M-LVDS Buff r
SN65MLVD201DR
SE_REFCLK_OUT_1V8 (BANK 64)
REFCLK_OUT_EN_1V8 (BANK 64)
NB6L72MN
Crosspoint
Switch
DEBUG
BRD
SW1-1
CLK_SEL
0
...
9
MGTREFCLK0_224
Must b
25MHz Buff r
CDCLVD110ARHBT
PROGCLK_1
All Conn ct d MGTs
MGTREFCLK1
0
...
9
Buff r
NB6L14S
REFCLK300M_1 (BANK 65)
REFCLK300M_2 (BANK 71)
REFCLK300M_3 (BANK 74)
For REFCLK as PCI r f r nc
DDR4 r f r nc clocks
MGT r f r nc clocks
MGT r f r nc clocks
Figure 9 : Clock Topology
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ADM-VPX3-9V2 User Manual
3.4.1 PCIe Reference Clock
Quad 224 can serve as an input for the PCIe reference clock. his quad has direct access to VPX REFCLK at
MG REFCLK0. Any other suitable quad can provide a PCIE reference clock with PROGCLK0* or PROGCLK1*
as well.
3.4.2 Fa ric Clock
he design offers a fabric clock (net name FABRIC_CLK_*) which defaults to 300 MHz. his clock is intended to
be used for IDELAY elements in FPGA designs. he fabric clock is connected to a Global Clock (GC) pin.
DIFF_ ERM_ADV = ERM_100 is required for LVDS termination
3.4.3 Programming Clock (EMCCLK)
A 100MHz clock (net name EMCCLK_B) is fed into the EMCCLK pin to drive the SPI flash device during
configuration of the FPGA. Note that this is not a global clock capable IO pin.
3.4.4 PROGCLK0 Clock
he PROGCLK_0 clocks have a default 100MHz reference clock. Note that this clock frequency can be changed
to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator.
See details on avr2util in the section: USB Interface.
he PROGCLK_0 connects at each usable MG quad at the MG REFCLK0 location. Quad 224 is the only
exception, which is connected to VPX REFCLK instead. PROGCLK0_9* is connected to global clock pins at
Bank 68 as well.
See net names PROGCLK_0* for pin locations.
3.4.5 PROGCLK1 Clock
he PROGCLK_1 clocks have a default 156.25MHz reference clock. Note that this clock frequency can be
changed to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock
oscillator. See details on avr2util in the section: USB Interface.
he PROGCLK_1 connects at each usable MG quad at the MG REFCLK1 location.
See net names PROGCLK_1* for pin locations.
3.4.6 DDR4 SDRAM Reference Clocks
he four banks of DDR4 SDRAM memory each receive a separate reference clock, as per Xilinx UltraScale MIG
design guidelines. he reference clocks for these interfaces are nets beginning with REFCLK300M*.
he default frequency is 300MHz. Note that this clock frequency can be changed to any arbitrary clock frequency
up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator. See details on avr2util in the
section: USB Interface.
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ADM-VPX3-9V2 User Manual
3.5 PCI Express
he ADM-VPX3-9V2 is capable of PCIe Gen 3 between 1 and 16 lanes. he FPGA drives these lanes dirctly
using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is
generally automatic and does not require user intervention.
PCI Express reset (PERS #) dedicated reset pin on the FPGA (IO_ 3U_N12_PERS N0_65) is driven by either/
or VPX system reset or the slot maskable reset. Complete Pinout able signal PERS N0.
he other pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout
able
he PCI Express specification requires that all add-in cards be ready for enumeration within 120ms after power
is valid (100ms after power is valid + 20ms after PERS is released). he ADM-VPX3-9V2 does not meet this
requirement, but will configure in about 200ms when configured from a tandem bitstream with the proper SPI
constraints detailed in the llink:section:Configuration From Flash Memory. For more details on tandem
configuration, see Xilinx XAPP 1179.
Note:
Different SBCs/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"G Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See Xilinx PG195, PG213, and PG239 for more details).
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ADM-VPX3-9V2 User Manual
3.6 FireFly
A Samtec FireFly site located near the front of the board allows for additional high speed optical or copper cabled
links running at up to 224G total (2 ports with 4 channels at up to 28G).
More details on FireFly can be found at https://www.samtec.com/optics/optical-cable/mid-board/firefly
It is possible for Alpha Data to pre-fit industrial or commercial optical FireFly modules. Please contact
[email protected] for full details and options.
FireFly optical modules are robust to mechanical shock up to 11 ms / 20 g peak saw tooth shock and random
vibration to a level of W0 = 0.061 g2/Hz, per MIL-S D-810G.
All connectivity is detailed in the Complete Pinout able at the end of this document. he notation used in the net
names is FIREFLY_0*, FIREFLY_1*.
Figure 10 : FireFly Location
Figure 11 : MPO with Conduction Cooled
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