Alpha Data ADM-PA120 User manual

ADM-PA120
User Manual
Document Revision: 1.2
18th July 2023

ADM-PA120 User Manual
2023 Copyright Alpha Data Parallel Systems Ltd.
All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of this
publication may be reproduced, in any shape or form, without prior written consent from Alpha
Data Parallel Systems Ltd.
Head Office
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
elephone: [phone]
Fax: [phone]
email: [email protected]
website: http://www.alpha-data.com
US Office
10822 West oller Drive, Suite 250
Littleton, CO 80127
[phone]
[phone] - toll free
[email protected]
http://www.alpha-data.com
All trademarks are the property of their respective owners.

ADM-PA120 User Manual
able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Order Code .................................................................................................................................... 1
1.2 Key Features .................................................................................................................................. 2
2 Board Information ............................................................................................................................ 3
2.1 Physical Specifications .................................................................................................................. 3
2.2 PCIe Handle Installation ................................................................................................................ 4
2.3 Chassis Re uirements ................................................................................................................... 5
2.3.1 Handling Instructions ................................................................................................................. 5
2.3.2 PCI Express ............................................................................................................................... 5
2.3.3 Mechanical Re uirements ......................................................................................................... 5
2.3.4 Power Re uirements ................................................................................................................. 6
2.4 Thermal Performance .................................................................................................................... 7
2.5 Customizations .............................................................................................................................. 7
3 Functional Description .................................................................................................................... 8
3.1 Overview ........................................................................................................................................ 8
3.1.1 Switches ..................................................................................................................................... 9
3.1.2 LEDs ........................................................................................................................................ 10
3.2 Clocking ....................................................................................................................................... 11
3.2.1 LMK61E2 ................................................................................................................................. 13
3.2.2 Si5344 ...................................................................................................................................... 14
3.2.3 Si5402 ...................................................................................................................................... 14
3.2.4 PCIe Reference Clocks ............................................................................................................ 15
3.2.5 Fabric Clock ............................................................................................................................. 15
3.2.6 PS Reference Clock (PS_REF_CLK) ...................................................................................... 15
3.2.7 MGT Programable Clock ......................................................................................................... 15
3.2.8 Memory Clocks ........................................................................................................................ 15
3.3 PCI Express ................................................................................................................................. 16
3.4 LPDDR4 SDRAM ......................................................................................................................... 16
3.5 QSFP-DD ..................................................................................................................................... 17
3.6 Front I/O timing inputs .................................................................................................................. 18
3.6.1 Trigger Input/Output (I/O) ......................................................................................................... 18
3.6.2 1PPS Input ............................................................................................................................... 19
3.6.3 10MHz Input ............................................................................................................................. 19
3.6.4 G.703 Time of Day (ToD) / One Pulse per Second (1PPS) ..................................................... 20
3.7 System Monitor ............................................................................................................................ 21
3.7.1 System Monitor Status LEDs ................................................................................................... 22
3.8 Micro USB Interface ..................................................................................................................... 23
3.9 Configuration ................................................................................................................................ 24
3.9.1 Configuration From QSPI Flash Memory ................................................................................. 24
3.9.2 Configuration From uSD Flash Memory .................................................................................. 24
3.9.3 Configuration via JTAG ............................................................................................................ 25
3.9.4 Boot Modes .............................................................................................................................. 25
3.10 ULPI USB Interface ...................................................................................................................... 26
3.11 UART interfaces ........................................................................................................................... 26
3.12 GEM0 ........................................................................................................................................... 27
3.13 User EEPROM ............................................................................................................................. 27
3.14 PMOD .......................................................................................................................................... 28
3.15 Battery .......................................................................................................................................... 28
Appendix A MIO Map .......................................................................................................................................... 29
Appendix B Complete Pinout Table .................................................................................................................. 32

ADM-PA120 User Manual
List of ables
able 1 Mechanical Dimensions (PCB only) ................................................................................................... 3
able 2 Mechanical Dimensions (Fully Assembled) ....................................................................................... 3
able 3 Available Power By Rail ..................................................................................................................... 6
able 4 Switch Functions ................................................................................................................................ 9
able 5 LED Details ...................................................................................................................................... 10
able 6 Si5328 address table ....................................................................................................................... 14
able 7 Si5328 address table ....................................................................................................................... 15
able 8 Voltage, Current, and emperature Monitors ................................................................................... 21
able 9 Status LED Definitions ..................................................................................................................... 22
able 10 Boot Mode Selection ........................................................................................................................ 25
able 11 MIO Map .......................................................................................................................................... 29
able 12 Complete Pinout able ..................................................................................................................... 32
List of Figures
Figure 1 ADM-PA120 Fully Assembled ............................................................................................................ 1
Figure 2 ADM-PA120 Product Photo ............................................................................................................... 2
Figure 3 ADM-PA120 PCIe Handle Installation ................................................................................................ 4
Figure 4 Retention Points ................................................................................................................................. 5
Figure 5 hermal Performance ........................................................................................................................ 7
Figure 6 ADM-PA120 Block Diagram ............................................................................................................... 8
Figure 7 Switches ............................................................................................................................................. 9
Figure 8 Front Panel LEDs ............................................................................................................................. 10
Figure 9 Clock opology ................................................................................................................................. 12
Figure 10 LMK61xx Oscillator Programming ool GUI .................................................................................... 13
Figure 11 LPDDR4 bank locations by index .................................................................................................... 16
Figure 12 QSFP-DD Location .......................................................................................................................... 17
Figure 13 Front I/O timing inputs ...................................................................................................................... 18
Figure 14 rig Schematic ................................................................................................................................. 18
Figure 15 1PPS Input Schematic ..................................................................................................................... 19
Figure 16 10MHz Input Schematic ................................................................................................................... 19
Figure 17 G.703 oD/1PPS or RS485 Schematic ............................................................................................ 20
Figure 18 USB Location ................................................................................................................................... 23
Figure 19 uSD Location ................................................................................................................................... 24
Figure 20 ULPI USB Location .......................................................................................................................... 26
Figure 21 USB UAR Location ........................................................................................................................ 26
Figure 22 GEM0 Ethernet Location .................................................................................................................. 27
Figure 23 PMOD location ................................................................................................................................. 28
Figure 24 Battery Location ............................................................................................................................... 28

ADM-PA120 User Manual
1 Introduction
he ADM-PA120 is a high-performance reconfigurable computing card featuring the latest AMD Adaptive
Compute Acceleration Platform (ACAP) platform known as Versal. he PCIe form factor is ideal for Data Center
applications and general evaluation and deployment of this architecture. he card features three QSFP-DD
interfaces, four banks of 64-bit LPDDR4-SDRAM, front panel Ethernet, 1pps input, 10MHz input, trigger I/O,
RJ45 G.703 oD/1PPS, PMOD, and USB.
Figure 1 : ADM-PA120 Fully Assembled
1.1 Order Code
See the datasheet on web page https://www.alpha-data.com/product/adm-pa120/ for complete ordering options.
Page 1Introduction
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ADM-PA120 User Manual
1.2 Key Features
Key Features
• PCIe Gen4 x16, dual Gen5x8 capable
• 2-slot active or passive heat sink
• 3/4 length, full profile, x16 edge PCIe form factor
• Supports Versal XCVP1202 and XCVP1502 ACAP devices in the VSVA2785 package
• 3x QSFP-DD interfaces at front panel
• 2x QSFP-DD cages connected to G M capable of 56g PAM4 on each of the 16 channels.
• 1x QSFP-DD cage connected to G Y capable of 28g NRZ on each of the 8 channels.
• Industry standard low speed I/O at front panel
• SMA for 1PPS input (I U- G.703 section 19.2)
• SMA for 10MHz input (I U- G.703 section 20)
• SMA with rig input/output (I U- G.703 section 19.2)
• RJ45 with 2x bidirectional RS485 interfaces for oD and 1PPS (I U- G.703 section 19.1)
• Versatile MIO interface support:
• GEM0 Ethernet access through RJ45 at front panel
• uSD
• Dual QSPI
• ULPI USB PHY accessible at USBA receptacle
• 2x UAR broken out through micro-USB at PCIe front panel and rear
• Four separate banks of 64 bit LPDDR4 SDRAM at 3933 M /s for 3 banks 3200M /s for 1 bank
• Front panel and rear edge J AG access via USB port
• ACAP configurable over USB/J AG and SPI configuration flash
• Voltage, current, and temperature monitoring
• Digilent PMOD 3.3V, 12-pin interface accessible to PL
• 6 user LEDs
Figure 2 : ADM-PA120 Product Photo
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ADM-PA120 User Manual
2 Board Information
2.1 Physical Specifications
he ADM-PA120 complies with PCI Express CEM revision 5.0.
Description Measure
PCB Dy 111.15 mm
PCB Dx 254 mm
otal Dz 19.9 mm
Table 1 : Mechanical Dimensions (PCB only)
Description Measure
otal Dy 126.3 mm
otal Dx 267.5 mm
otal Dz 41.9 mm
otal weight 865 grams
Weight of PCIe handle 30 grams
Table 2 : Mechanical Dimensions (Fully Assembled)
otal weight does not include the PCIe Handle, which is optional and shipped uninstalled.
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ADM-PA120 User Manual
2.2 PCIe Handle Installation
he ADM-PA120 ships fully assembled. here is a PCIe compliant handle shipped in a separate bag within the
product package. his handle assembly includes a plastic handle and a metal bracket. he bracket simulates the
full length PCIe card length, and frequently lines up with server retention clips. he plastic handle can be
removed and only the metal bracket used if it fits better in the host system. Use all retention options available to
secure this add-in card.
he drawing below details installation of the rear handle bracket.
54321
A
B
C
D
A
B
C
D
543 2 1
The copyright of this document is the property o f Alpha Data Incorporated
The document is supplied by Alpha Data Incorporated on the e press understanding that
it is to be treated as confidentia l and that it may not be copied, used of disclosed to others in whole
or in part for any purpose e cept as authorized in writing by Alpha Data Incorporated
ADM-PA120 Support Bracket Assembly
A2
1 of 1
AD01492-1_FA02-1
Document Number
Alpha Data Parallel Systems Ltd
160 Dundee Street,
Edinburgh, EH11 1DQ, UK
www.alpha-data.com
SheetDate
Size
Title
Rev
REV ZONE DESCRIPTION DATE DWN BY
1 ALL INITIAL RELEASE 26-MAY-2023 K. ROTH
ITEM PART NO DESCRIPTION QTY
1 ADM-PA120 ADM-PA120 (AD01492), PCIE, ASSEMBLY 1
NOTES
1. USE LOCTITE 222 ON ALL SCREWS
2. TORQUE ALL SCREWS TO 0.23N-M [2IN-LBS].
3. SUGGESTED ASSEMBLY ORDER FOLLOWS ITEM NUMBER IN ASCENDING ORDER.
4. START ALL SCREW SETS LOOSELY BEFORE TIGHTENING GROUP.
2 AD01398-1_SP05-3 HANDLE SUPPORT BRACKET (GOMPF P/N 3200-2954LC ECO 02) 1
ALPHA DATA
MANUFACTURER/DISTRIBUTOR
GOMPF
3 91060000AFG PCIE HANDLE 1 GOMPF
1
4
2
3
4 92010A001 SCREW, M2 X 4MM, FLAT HEAD, STAINLESS STEEL 4 MCMASTER-CARR / GENERIC
5
5 6089-3512 SCREW, SELF-THREADING, PAN HEAD, STAINLESS STEEL 2 GOMPF
Figure 3 : ADM-PA120 PCIe Handle Installation
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ADM-PA120 User Manual
2.3 Chassis Requirements
2.3.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
2.3.2 PCI Express
he ADM-PA120 is capable of PCIe Gen 1/2/3/4 with 1/4/8/16 lanes, and PCIe Gen 5 with 1/4/8 lanes when
using the AMD Integrated Block for PCI Express. PCIe Gen 5x8 can be bifurcated into two slots to achieve an
aggregate bandwidth of a 16 lane connection.
2.3.3 Mechanical Requirements
A 16 lane physical PCIe slot is required for mechanical compatibility.
he card is also designed to use the extra mechanical retention mechanisms defined in the PCIe specification.
his includes both the board keep out region along the top edge, and the full-length handle support. It is
recommended to use all board retention features supported by the host systems. hese cards are heavy and can
be damaged when used in systems that do not mechanically support the hardware properly.
Figure 4 : Retention Points
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ADM-PA120 User Manual
2.3.4 Power Requirements
he ADM-PA120 draws power from the PCIe Edge and the 8-pin A X power connector. he ADM-PA120 does
not use or require the 3.3V power from the PCIe Edge (though it does use 3.3V AUX). o operate with PCIe edge
only, ensure SW2-6 is OFF (see Switches). As per PCIe specification, users should limit the board power
consumption to 66W when using only the PCIe edge power. Adding the 8-pin A X connector provides additional
150W of power, bringing the total board power dissipation maximum to 216W.
It is possible to operate this product standalone with power from the 8-pin A X power connector alone. Please be
aware this reduces the total rated power of the card to 150W. Standalone operation requires a modified A X
power cable where the sense wires have been removed. Please contact [email protected] to receive a
modified A X extension cable. When using a cable with the sense wires removed, ensure SW1-6 is set OFF
which enables the 12V auto-detect feature. If SW2-6 is ON, the board will not power up unless both PCIe edge
and the Aux cable are both used.
Power consumption estimation requires the use of the AMD XPE spreadsheet (www.xilinx.com/products/
technology/power/xpe.html ) and a power estimator tool available from Alpha Data. Please contact
[email protected] to obtain this tool.
he power available to the rails calculated using XPE are as follows:
Voltage Source Name Current Capability
0.85-0.90 VCC_IN + VCC_IO + VCC_RAM + VCC_IO 120A
0.85-0.90 VCC_PMC + VCC_PSFP + VCC_PSLP+ VCC_CPM5 6A
0.88 MG AVCC 10A
1.1 VCCO for LDDR4 8A
1.2 MG AV 14A
1.5 G Y_AVCCAUX 1.2A
1.5 VCCO + VCCAUX + VCCAUX_PMC 8A
1.5 VCCO 8A
1.8 VCCO 1.2A
3.3 VCCO + QSFP 15A
5V USB-A 0.5A
Table 3 : Available Power By Rail
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ADM-PA120 User Manual
2.4 Thermal Performance
If the ACAP core temperature exceeds 105 degrees Celsius, the ACAP design will be cleared to prevent the card
from over-heating.
he ADM-PA120 comes with a heat sink to avoid thermal overstress of ACAP, since it is typically the hottest point
on the card. he ACAP die temperature must remain under 100 degrees Celsius. o estimate the ACAP die
temperature: first take your total board power (see next paragraph), then multiply by heta JA from the graph
below, and add the resulting temperature to your system internal ambient temperature.
he power dissipation can be estimated by using the Alpha Data power estimator in conjunction with the AMD
Power Estimator (XPE) downloadable at www.xilinx.com/products/technology/power/xpe.html . Download the
Versal tool and set the device according to your part number details: Versal Premium Series, XCVP1202 or
XCVP1502, VSVA2785 package, -2MS/-2HS speed grade, extended. Set the ambient temperature to your
system ambient and select 'user override' for the effective theta JA. hen enter the figure associated with your
system LFM in the blank field. Proceed to enter all applicable design elements and utilization in the following
spreadsheet tabs. Next acquire the PA120 power estimator from Alpha Data by contacting
[email protected]. Enter in the power figures from XPE, QSFP-DD (if used), and DRAM utilization into
the Alpha Data spreadsheet to get a complete board level estimate.
Figure 5 : Thermal Performance
2.5 Customizations
Alpha Data provides extensive customization options to existing commercial off-the-shelf (CO S) products.
Some options include, but are not limited to: custom front panel interfaces, additional networking cages in
adjacent slots, enhanced heat sinks, baffles, and circuit additions.
Please contact [email protected] to get a quote and start your project today.
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ADM-PA120 User Manual
3 Functional Description
3.1 Overview
he ADM-PA120 is a high-performance reconfigurable computing card featuring the latest AMD Adaptive
Compute Acceleration Platform (ACAP) platform with the Versal XCVP1202 or XCVP1502, three QSFP-DD
interfaces, PCIe Gen4x16 or 2xGen5x8, four banks of LPDDR4 each 64 bits wide, GEM0 Ethernet, QSPI, uSD,
USB, UAR , a Digilent PMOD site, flexible front panel I/O (RS485 for oD, 1PPS, 10MHz, and general purpose I/
O), and a robust system monitor.
LPDDR4
64bit
LPDDR4
64bit
LPDDR4
64bit
VSVA2785
VP1202/VP1502/VP1552
x16 PCIe Gen5 Edge
Syste
Monitor
QSPI
(Config)
GTYP
USB
(front)
MIO
USB Hub
HDIO
USB
(back)
USB to
JTAG
I2C
MGT
x24
Fans
3x QSFP-DD 8 GPIO
MIO
RJ45
Socket Mag + PHY
UART PHY
Mux 12V
PWR
Mux
8-pin
ATX
PWR
(150W)
PMOD
XPIO
USB PHY
Power
Reg.
XPIO
x16
I2C
EEPROM\
USB-A
(rear)
x2
GPIO
Socket
LPDDR4
64bit
uSD
Ti ing I/O
RF I/ORF I/O
Figure 6 : ADM-PA120 Block Diagram
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ADM-PA120 User Manual
3.1.1 Switches
he ADM-PA120 has two octal DIP switch SW1 and SW2, located on the rear side of the board. he function of
each switch is detailed below:
Figure 7 : Switches
Switch Factory
Default Function OFF State ON State
SW1-1 OFF Reserved BD BD
SW1-2 OFF SI5402_I2C Isolate Connect Si5402 I2C to PL Isolate Si5402 I2C from PL
SW1-3 OFF HOS _I2C_EN System Monitor connected to
PCIe slot I2C System Monitor isolated from PCIe slot I2C
SW1-4 OFF Service Mode System Monitor normal
operation System Monitor Service Mode (firmware update etc.)
SW1-5 OFF PERS to POR_B PCIE RESE isolated from
POR_B PCIE RESE will drive POR_B low
SW1-6 OFF POR_B ACAP power on reset
released ACAP power on reset active
SW1-7 OFF Reserved BD BD
SW1-7 OFF Reserved BD BD
SW2-1 ON BootMode 0 See able 10
SW1-2 OFF BootMode 1 See able 10
SW2-3 OFF BootMode 2 See able 10
SW2-4 OFF BootMode 3 See able 10
SW2-5 OFF Reserved BD BD
SW2-6 OFF 12V Auto-detect 12V auto-detect enabled 8-pin A X cable and PCIe
edge both required
SW2-7 OFF Reserved BD BD
SW2-8 OFF Power Off Board will power up Immediately power down
Table 4 : Switch Functions
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ADM-PA120 User Manual
3.1.2 LEDs
here are 10 LEDs on the ADM-PA120, 6 of which are general purpose and whose meaning can be defined by
the user. he other 4 have fixed functions described below:
D19
D18 D20
DONE_L STAT_1
D21
STAT_0
Status LEDsUser LEDs
D17
USER_LED_G0
D12
USER_LED_G1
ERROR
_OUT_L
D4
USER_LED_G2
D3
USER_LED_G3
D2
USER_LED_G4
D1
USER_LED_G5
Figure 8 : Front Panel LEDs
Comp.
Ref. Function/Net Name ON State OFF State
D17 USER_LED_G0 User defined '0' User defined '1'
D12 USER_LED_G1 User defined '0' User defined '1'
D4 USER_LED_G2 User defined '0' User defined '1'
D3 USER_LED_G3 User defined '0' User defined '1'
D2 USER_LED_G4 User defined '0' User defined '1'
D1 USER_LED_G5 User defined '0' User defined '1'
D18 ERROR_OU _L Boot error No error reported
D19 DONE_L PL is configured PL is not configured
D20 Status 1 See Status LED Definitions
D21 Status 0 See Status LED Definitions
Table 5 : LED Details
See Section Complete Pinout able for full list of user controlled LED nets and pins
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ADM-PA120 User Manual
3.2 Clocking
he ADM-PA120 provides flexible reference clock solutions for the many multi-gigabit transceiver quads,
LPDDR4 banks, and PL fabric. he reprogrammable clocks from the LMK61E2 are reconfigurable from the front
panel Micro USB Interface by using Alpha Data’s avr2util utility. his allows the user to configure almost any
arbitrary clock frequency during application run time. he maximum clock frequency for the LMK61e2 is 900MHz.
Customers who purchase RD-PA120 also have the option of embedding IP into their ACAP design that permits
programmable clock reconfiguration via PCIe or from within the ACAP.
here is one Si5344 jitter attenuator. his can provide clean and synchronous clocks to the QSFP-DD quad
locations at many clock frequencies. he Si5344 can be reconfigured over I2C using with a controller embedded
in the FPGA design.
here is one Si5402 Network Synchronizer. his can provide synchronous clocks for 5G, SyncE, and IEEE 1588
applications with 10Mhz and 1PPS inputs. he Si5402 can be reconfigured over I2C using with a controller
embedded in the FPGA design. Using this chip requires support directly from Skyworks. Alpha Data does not
support application software for this device.
All clock names in the section below can be found in Complete Pinout able.
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ADM-PA120 User Manual
SI5344
(1DSPLL)
I2C +
CNTRL XA/XB
CLKIN0
CLKIN1
Versal ACAP
PCIE_LCL_REFCLK (GTY_REFCLK0_103)
PCIe
Ed e
PCIE_REFCLK_0 (GTY_REFCLK0_102)
Buffer
NB6N11S PCIE_REFCLK_1 (GTY_REFCLK0_104)
GC XPIO (10MHZ_PIN)
LMK61E2
Pro rammable
Source
50ppm
MEM_CLK_0 300MHz Default (IO Bank 700)
MEM_CLK_1 300MHz Default (IO Bank 703)
LMK61E2
Pro rammable
Source
50ppm
10MHz
(SMA)
MGTREFCLK0 (SI5344_OUT0)
MGTREFCLK1 (SI5402_OUT6)
Quad
205
GTM
Quad
204
GTM
Connects to
QSFP-DD 2
0-3 4-7
MGTREFCLK0 (MGT_PROGCLK_0)
MGTREFCLK1 (SI5402_OUT7)
MGTREFCLK0 (SI5344_OUT1)
MGTREFCLK1 (SI5402_OUT3)
Quad
202
GTM
Quad
203
GTM
Connects to
QSFP-DD 1
0-3 4-7
MGTREFCLK0 (MGT_PROGCLK_1)
MGTREFCLK1 (SI5402_OUT4)
MGTREFCLK0 (SI5344_OUT2)
MGTREFCLK1 (SI5402_OUT1)
Quad
201
GT
Quad
200
GT
Connects to
QSFP-DD 0
0-3 4-7
MGTREFCLK0 (MGT_PROGCLK_2)
MGTREFCLK1 (SI5402_OUT2)
CLKIN2
CLKIN3
OUT0
OUT1
OUT2
OUT3
Buffer
4 Diff Pairs
Buffer MEM_CLK_2 300MHz Default (IO Bank 706)
MEM_CLK_3 300MHz Default (IO Bank 711)
XPIO
Bank 712
SI5402
(2DSPLL)
I2C +
CNTRL XA/XB
CLKIN0
CLKIN1
CLKIN2
CLKIN3
OUT10
OUT9
OUT3
OUT4
OUT2
OUT1
OUT5
OUT0
33.333MHz
Fixed
Source PS_REF_CLK (CIPS REF_CLK_503)
GC XPIO (FABRIC_CLK or “refclk_100m”)
XPIO (SI5***_IN*)
GC XPIO (SI5402_OUT5_PIN)
100MHz
Fixed
Source
50ppm
SMB
(Spare front)
SMB
(Spare rear)
100MHz
Fixed
Source
2.5ppm
Balun Buffer
XPIO (1PPS_FPGA)
1PPS
(SMA) Buffer
XPIO (TRIG_IN_FPGA)
Tri
(SMA) Buffer XPIO (TRIG_OUT_FPGA)
Figure 9 : Clock Topology
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ADM-PA120 User Manual
3.2.1 LMK61E2
he ADM-PA120 uses the LMK61E2 for arbitrary clock frequency synthesis. For complete technical details,
please reference the datasheet:
https://www.ti.com/lit/ds/symlink/lmk61e2.pdf
he ADM-PA120 uses two LMK61E2 devices in the clock architecture. hese can be accessed through either the
USB or PCIe link using the AVR2U IL application. See additional details on avr2util in the section: Micro USB
Interface.
o re-program the LMK61E2 in a non-volatile manner, issue the following command:
avr2util <other options> setclknv-regmap <clock#> <reg. map file>
Note:
Each LMK61E2 is rated for only 100 non-volatile write operations.
o re-program the LMK61E2 in a volatile manner, issue the following command:
avr2util <other options> setclk-regmap <clock#> <reg. map file>
<other options> should be left blank for PCIE, and '-usbcom' for USB.
<clock#> is 0 for MG _PROGCLK and 1 for MEM_CLK.
<reg. map file> is a text file generated using the "LMK61xx Oscillator Programming ool — SNAC074.ZIP" which
can be obtained with a I login from this page: https://www.ti.com/tool/LMK61E2EVM . After you have the tool
installed, launch the application, type in the desired frequency, select "LVDS" output standard, click "Generate
Configuration", then go to "File->Export hex register values"
Figure 10 : LMK61xx Oscillator Programming Tool GUI
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ADM-PA120 User Manual
3.2.2 Si5344
If jitter attenuation is required please see the reference documentation for the Si5344.
https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/si5345-44-42-d-datasheet.pdf
here is one input clock that originates in the ACAP PL (board net name SI5344_IN0_P/N). his allows the
application design to feed this clock from anywhere within the ACAP PL.
hree output clocks are connected to quads 201, 202, and 205 to provide clocking capability each QSFP-DD
interface.
he LOL signals for the Si5344 is available for use, and can be located at net names
SI5344_LOL_XAXB_1V5_N and SI5344_LOL_1V5_N in the Complete Pinout able.
he active low reset of the Si5344 is accessible to the ACAP. See net names SI5344_RS _1V5_N in the
Complete Pinout able.
Note:
Each sideband signal has an external pull-up resistor.
he Si5344 configuration register map is volatile unless burned into NVM. You are only allowed to burn a register
map twice during the product's life time. o write the register map use nets SI5344_SDA_1V5 and
SI5344_SCL_1V5 at pins located in the Complete Pinout able. he Si5344 device is configured the I2C address
shown in the table below:
device 7bit Hex Address Binary Address
Si5344 68 110_1000
Table 6 : Si5328 address table
3.2.3 Si5402
If a Network Synchronizer Clock for 5G/SyncE/IEEE 1588 applications is required please see the reference
documentation for the Si5402.
https://www.skyworksinc.com/en/Products/ iming/NetSync-Network-Synchronizer-Clocks/Si5402A
here are three input clock that originate in the ACAP PL (board net name SI5402_IN*_P/N). his allows the
application design to feed this clock from anywhere within the ACAP PL amd forward 10MHz and 1PPs signals.
Six output clocks are connected to quads 200 through 205 to provide clocking capability each QSFP-DD
interface.
he GPIO signals for the Si5402 are available for use, and can be located at net names SI5402_GPIO* in the
Complete Pinout able.
he active low reset of the Si5402 is accessible to the ACAP. See net names SI5402_RS _1V5_N in the
Complete Pinout able.
Note:
Each sideband signal has an external pull-up resistor.
he Si5344 configuration register map is volatile. o write the register map use nets SI5402_1V5_SDA and
SI5402_1V5_SCL at pins located in the Complete Pinout able. he Si5402 device is configured the I2C address
shown in the table below:
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device 7bit Hex Address Binary Address
Si5344 58 101_1000
Table 7 : Si5328 address table
3.2.4 PCIe Reference Clocks
he 16 MG lanes connected to the PCIe card edge use MG tiles 102 through 105 and use the host system's
100 MHz PCIe reference clock (net name PCIE_REFCLK_0_P/N or PCIE_REFCLK_1_P/N in the Complete
Pinout able).
Alternatively, a more stable but asynchronous onboard 100MHz clock is available as well (net name
PCIE_LCL_REFCLK_P/N in the Complete Pinout able).
3.2.5 Fabric Clock
he design offers a fabric clock (net name FABRIC_CLK_P/N) which is a high accuracy 2.5ppm 100 MHz clock.
his clock is intended to be used for the PL designs. he fabric clock is connected to a Global Clock (GC) pin.
Use constraints IOS ANDARD LVCMOS15 for this reference clock.
See net names FABRIC_CLK_1V5 in the Complete Pinout able for pin locations.
In the Alpha Data provided board file, this is called "refclk_100m"
3.2.6 PS Reference Clock (PS_REF_CLK)
A 33.333MHz clock is fed into the dedicated REF_CLK_503 pin to drive the processor system. his clock has an
accuracy tolerance of 50ppm.
3.2.7 MGT Programable Clock
he MG reference clock connects to one quad of each QSFP-DD connector. his programable clock has a
default 161.1328125MHz reference clock. his clock frequency can be changed to any arbitrary clock frequency
up to 900MHz by re-programming the LMK61E2 reprogrammable clock oscillator. See details on avr2util in the
section: Micro USB Interface.
See net names MG _PROGCLK_*_PIN_P/N in the Complete Pinout able for pin locations.
3.2.8 Memory Clocks
Each of the four memory banks has their own buffered 300MHz reference clock. his clock frequency can be
changed to any arbitrary clock frequency up to 900MHz by re-programming the LMK61E2 reprogrammable clock
oscillator. See details on avr2util in the section: Micro USB Interface.
See net names MEM_CLK_*_PIN_P/N in the Complete Pinout able for pin locations.
See LPDDR4 SDRAM for more information on the memory banks and their physical locations.
hese clocks are not fabric accessible, but are reserved for the Versal LPDDR4 cores.
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3.3 PCI Express
he ADM-PA120 is capable of PCIe Gen 1/2/3/4 with 1/4/8/16 lanes and bifurcated Gen 5 with 1/4/8 lanes. he
ACAP drives these lanes directly using the Integrated PCI Express block from AMD. Negotiation of PCIe link
speed and number of lanes is generally automatic and does not require user intervention.
PCI Express reset (PERS #) is connected to the ACAP through a buffer. See Complete Pinout able signal
PERS _PL_L for fabric accessible location, and PCIE_RS _1V8_L for the PS locations.
he pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout able,
see net names PCIE_ X*_PIN_P/N and PCIE_RX*_P/N.
3.4 LPDDR4 SDRAM
wo banks of LPDDR4 SDRAM memory are soldered down to the board. he available density of the memory is
4GB/per bank, 16GB total. he memory interface is 64-bit wide data . Maximum signalling rate is 3933 M /s for
banks 0-2 and 3200M /s for bank 3. his speed limitation is a limitation of the ACAP device, see AMD
specifications for more details.
Memory solutions are available from the AMD (See AMD PG313 Versal ACAP Programmable
Network on Chip and Integrated Memory Controller v1.0). LPDDR4_0 through 2 use the Non-Flipped Pinout, and
LPDDR4_3 uses the Flipped Pinout. An example memory exerciser project is included in the RD-PA120. All pin
location information is included in Complete Pinout able and the board file.
he components used are Micron M 53E512M32D1ZW-046 I or equivalent.
Figure 11 : LPDDR4 bank locations by index
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