Alpha Data ADM-XRC-9R4 User manual

ADM-XRC-9R4
User Manual
Document Revision: 1.1
8th June 2 23

ADM-XRC-9R4 User Manual
V1.1 - 8th June 2 23
© 2 23 Copyright Alpha Data Parallel Systems Ltd.
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All trademarks are the property of their respective owners.

ADM-XRC-9R4 User Manual
V1.1 - 8th June 2 23
able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Feature .................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 3
1.3 Reference & Specification .......................................................................................................... 3
2 Example Design ............................................................................................................................... 4
3 Installation ........................................................................................................................................ 5
3.1 Hardware In tallation ..................................................................................................................... 5
3.1.1 Handling In truction ................................................................................................................. 5
3.1.2 Motherboard / Carrier Requirement ......................................................................................... 5
3.1.3 Cooling Requirement ............................................................................................................... 6
4 Functional Description .................................................................................................................... 7
4.1 Overview ........................................................................................................................................ 7
4.1.1 Switch Definition ....................................................................................................................... 8
4.1.2 LED Definition .......................................................................................................................... 9
4.2 XMC Platform Interface ................................................................................................................ 10
4.2.1 IPMI I2C ................................................................................................................................... 10
4.2.2 MBIST# .................................................................................................................................... 10
4.2.3 MVMRO ................................................................................................................................... 10
4.2.4 MRSTI# .................................................................................................................................... 10
4.2.5 MRSTO# .................................................................................................................................. 10
4.2.6 MPRESENT# ........................................................................................................................... 10
4.3 JTAG Interface ............................................................................................................................. 11
4.3.1 On-board Interface ................................................................................................................... 11
4.3.2 XMC Interface .......................................................................................................................... 11
4.3.3 JTAG Voltage ......................................................................................................................... 11
4.4 Clock .......................................................................................................................................... 12
4.4.1 300MHz Reference Clock (REFCLK300M and FABRIC_CLK) .............................................. 13
4.4.2 100MHz Reference Clock (REFCLK100M) ............................................................................ 13
4.4.3 PCIe Reference Clock (PCIEREFCLK) .................................................................................. 13
4.4.4 Programmable Clock (PROGCLK 0-2) .................................................................................. 13
4.4.5 MGT Reference Clock ............................................................................................................ 14
4.4.6 PS Sy tem Clock ..................................................................................................................... 14
4.4.7 RF Sampling Clock ................................................................................................................ 15
4.4.7.1 Sy ref Clock ....................................................................................................................... 16
4.4.7.2 RF Sy tem FPGA Reference Clock ..................................................................................... 16
4.4.7.3 RF Clock Programming ........................................................................................................ 16
4.5 Zynq PS Block ............................................................................................................................. 17
4.5.1 Boot Mode .............................................................................................................................. 17
4.5.2 Quad SPI Fla h Memory .......................................................................................................... 17
4.5.3 MicroSD Fla h Memory ........................................................................................................... 17
4.5.4 PS DDR4 Memory ................................................................................................................... 17
4.5.5 PS MGT Link .......................................................................................................................... 17
4.5.6 Serial COM Port ..................................................................................................................... 17
4.6 PL Interface ................................................................................................................................ 18
4.6.1 I/O Bank Voltage .................................................................................................................... 18
4.6.2 MGT Link ................................................................................................................................ 18
4.6.3 Memory Interface ................................................................................................................... 19
4.6.4 GPIO ........................................................................................................................................ 19
4.7 RF Interface ............................................................................................................................... 20
4.7.1 Front-Panel I/O ........................................................................................................................ 20
4.7.2 RF Performance ....................................................................................................................... 21
4.7.2.1 ADC RF Performance .......................................................................................................... 21
4.7.2.2 DAC RF Performance .......................................................................................................... 24

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4.8 Configuration ................................................................................................................................ 26
4.8.1 Power-Up Sequence ................................................................................................................ 26
4.9 Sy tem Monitoring ....................................................................................................................... 26
4.9.1 Automatic Temperature Monitoring .......................................................................................... 27
4.9.2 Microcontroller Statu LED .................................................................................................... 27
4.9.3 Sy tem Monitor Interface ....................................................................................................... 28
Appendix A Rear Connector Pinouts ................................................................................................................ 29
A.1 Primary XMC Connector, P5 ........................................................................................................ 29
A.2 Secondary XMC Connector, P6 ................................................................................................... 30
A.2.1 Pn6 GPIO Pin Map .................................................................................................................. 31
A.3 PMC Connector P4 ...................................................................................................................... 32
List of ables
able 1 Build Options ...................................................................................................................................... 3
able 2 References ......................................................................................................................................... 3
able 3 Switch Definitions ............................................................................................................................... 8
able 4 LED Definitions .................................................................................................................................. 9
able 5 REFCLK300M Connections ............................................................................................................. 13
able 6 REFCLK100M Connections ............................................................................................................. 13
able 7 PCIEREFCLK Connections ............................................................................................................. 13
able 8 PROGCLK Connections .................................................................................................................. 13
able 9 PS System Clock Connections ........................................................................................................ 14
able 10 RF Clock Sources ............................................................................................................................ 15
able 11 RF Clock Connections ..................................................................................................................... 15
able 12 SysRef Connections ........................................................................................................................ 16
able 13 FPGA Reference Clock Connections ............................................................................................... 16
able 14 FPGA 4-Wire Connections ............................................................................................................... 16
able 15 Boot Mode Selection ........................................................................................................................ 17
able 16 arget FPGA IO Banks ..................................................................................................................... 18
able 17 arget MG Links ............................................................................................................................. 18
able 18 Front panel I/O signals ..................................................................................................................... 20
able 19 ADC Parameters .............................................................................................................................. 21
able 20 DAC Parameters .............................................................................................................................. 24
able 21 Voltage and emperature Monitors .................................................................................................. 26
able 22 emperature Limits .......................................................................................................................... 27
able 23 Status LED Definitions ..................................................................................................................... 27
able 24 Pn5 Interface .................................................................................................................................... 29
able 25 Pn6 Interface .................................................................................................................................... 30
able 26 Pn6 GPIO Pin Map .......................................................................................................................... 31
able 27 Pn4 Interface .................................................................................................................................... 32
List of Figures
Figure 1 ADM-XRC-9R4 Board ........................................................................................................................ 1
Figure 2 ADM-XRC-9R4 Vivado Example Design ........................................................................................... 4
Figure 3 ADM-XRC-9R4 Block Diagram .......................................................................................................... 7
Figure 4 LED Locations .................................................................................................................................... 9
Figure 5 J AG Boundary Scan Chain ............................................................................................................ 11
Figure 6 Full Clock Diagram ........................................................................................................................... 12
Figure 7 MG Clocks ..................................................................................................................................... 14
Figure 8 ADM-XRC-9R4 RF sampling clocks ................................................................................................ 15

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Figure 9 Serial COM Ports ............................................................................................................................. 17
Figure 10 MG Links ........................................................................................................................................ 18
Figure 11 PL DRAM Banks .............................................................................................................................. 19
Figure 12 GPIO Block Diagram ........................................................................................................................ 19
Figure 13 Front Panel RF IO ............................................................................................................................ 20
Figure 14 ADC Signal Path .............................................................................................................................. 20
Figure 15 Front Panel Pinout ........................................................................................................................... 20
Figure 16 ADM-XRC-9R4 ADC Frequency Response ..................................................................................... 22
Figure 17 ADM-XRC-9R4 ADC SFDR vs Signal Power .................................................................................. 22
Figure 18 ADM-XRC-9R4 ADC Input Matching ............................................................................................... 23
Figure 19 ADM-XRC-9R4 ADC Crosstalk ........................................................................................................ 23
Figure 20 ADM-XRC-9R4 ADC Phase Matching ............................................................................................. 24
Figure 21 ADM-XRC-9R4 DAC Frequency Response ..................................................................................... 25

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1 Introduction
he ADM-XRC-9R4 is a high-performance XMC for applications using Zynq Ultrascale+ RFSoC DFE from Xilinx.
Figure 1 : ADM-XRC-9R4 Board
1.1 Key Features
Key Features
• Single-width XMC, compliant to VI A Standard 42.0 and 42.10d12
• Support for Zynq Ultrascale+ XCZU67DR RFSoC DFE in FFVE1156 packages
•RF Sampling block consisting of:
• 2 14-bit 5.9GSPS RF-ADCs with:
• Input low-pass filter
• Fixed amplifier/attenuator
• 0-31dB Digital Attenuator
• 450MHz - 2500MHz bandwidth (with default filters/baluns fitted)
• Full Scale Input (at 2400MHz): 7.0dBm
• 2 14-bit 10GSPS RF-DACs with:
• 450MHz - 3100MHz bandwidth (with default baluns fitted\, inverse sinc filter ON)
• Full Scale Output (800MHz/10GSPS/40.5mA VOP): 3.6dBm
•Front Panel IO Interface with:
• 2 single ended ADC signals
• 2 single ended DAC signals
• Reference clock output from RF clocking blocks
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•Processing System (PS) Block consisting of:
• Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5, Mali-400 GPU
• 1 bank of DDR4-2400 SDRAM 2GB
• Removable microSD Flash memory
• wo Quad SPI Flash memory, 512Mb each
• One serial COM port interfaces to rear P4 connector
• One system monitor USB port to micro USB connector
•Programmable Logic (PL) block consisting of:
• 8 HSSIO links to the P6 connector
• 1 banks of DDR4-2400 SDRAM, 1GB per bank
• 15 3.3V single ended GPIO pins to P6 and P4
• 20 1.8V single ended or 10 differential GPIO pins to P6
• Voltage and temperature monitoring
• Board management via USB.
• Air-cooled and conduction-cooled configurations
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1.2 Order Code
ADM-XRC-9R4/z-y(c)(a)(x)
Name Symbol Configurations
Device z ZU67
Speed Grade y 2
Cooling c Blank = Air cooled industrial
/CC1 = conduction cooled industrial
Coating a Blank = No coating /A = Acrylic
/A = Polyurethane
XMC Connector x Blank = Vita 42 /X2 = Vita 61 connectors
/V88 = Vita 88 connectors
Table 1 : Build Options
Not all combinations are available. Please check with Alpha Data sales for details.
1.3 References & Specifications
ANSI/VI A 42.0 XMC Standard, December 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 42.2 XMC Serial RapidIO Protocol Layer Standard, Feb 2006, VI A, ISBN 1-885731-41-8
ANSI/VI A 46.9 PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Module Standard,
November 2010, VI A, ISBN 1-885731-63-9
ANSI/IEEE 1386-2001 IEEE Standard for a Common Mezzanine Card (CMC) Family, October 2001, IEEE,
ISBN 0-7381-2829-5
ANSI/IEEE 1386.1-2001 IEEE Standard Phy ical and Environmental Layer for PCI Mezzanine Card (PMC),
October 2001, IEEE, ISBN 0-7381-2831-7
ANSI/VI A 20-2001
(R2005) Conduction Cooled PMC, February 2005, VI A, ISBN 1-885731-26-4
Table 2 : References
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2 Example Design
An FPGA and PS ARM/Linux example design is available, contact [email protected] for access. It
provides an interactive interface or command line interface to control the board features. It can be used to
program the RF clocks, drive signals from the DACs, receive data from the ADCs, control the RF converter
settings using the Xilinx XRFDC API and set the DSA attenuation.
Figure 2 : ADM-XRC-9R4 Vivado Example Design
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3 Installation
3.1 Hardware Installation
3.1.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
3.1.2 Motherboard / Carrier Requirements
he ADM-XRC-9R4 is a single width XMC.3 mezzanine with P6 and P4 connectors. he motherboard/ carrier
must comply with the XMC.3 specification for the Primary XMC connector, J5.
he Secondary XMC connector, P6 has a pinout compatible with various XMC to VPX signal maps as defined by
VI A 46.9. Please consult the pinouts in this user-guide as-well as those of the carrier manufacturer prior to
installation. Assistance can be provided by Alpha Data.
he ADM-XRC-9R4 is compatible with either 5V or 12V on the "VPWR" power rail.
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3.1.3 Cooling Requirements
he power dissipation of the board is highly dependent on the arget FPGA application. A power estimator
spreadsheet is available on request from Alpha Data. his should be used in conjunction with Xilinx power
estimation tools to determine the exact current requirements for each power rail.
he board is supplied with a passive air cooled or conduction cooled heat-sink according to the order number
given at time of purchase. It is the users responsibility to ensure sufficient airflow for air cooled applications and
metalwork for conduction cooled applications.
he board features system monitoring that measures the board and FPGA temperature. It also includes a
self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is
detected.
See Section 4.9 for further details.
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4 Functional Description
4.1 Overview
Figure 3 : ADM-XRC-9R4 Block Diagram
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4.1.1 Switch Definitions
here is a set of eight DIP switches placed on the rear of the board. heir functions are described in Switch
Definitions.
Note:
SW1-5 and SW1-8 are OFF by default. Factory Configuration switch must be in the OFF position for normal
operation. Other switches can be set as per user requirements.
Switch Ref. Function ON State Off State
SW1-1 BootMode 0 See able 15
SW1-2 BootMode 1 See able 15
SW1-3 BootMode 2 See able 15
SW1-4 BootMode 3 See able 15
SW1-5 Factory
Configuration - Normal Operation
SW1-6 XMC J AG
Enable XMC J AG interface is enabled XMC J AG interface is disabled
SW1-7 XMC PCIE
reset enable Zynq PS will be reset by the XMC PCIE reset signal Zynq PS will not be reset by the XMC PCIE reset signal
SW1-8 PS Reset PS is held in reset Normal Operation
Table 3 : Switch Definitions
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4.1.2 LED Definitions
he position and description of the board status LEDs are shown in LED Locations:
D1D2
D3
D6
D5
D4
D16D11 D10D12
D7
Figure 4 : LED Locations
Comp. Ref. Function ON State Off State
D7(Amber) MVMRO Inhibit writes to non-volatile memories Enable writes to non-volatile memories
D10(Red) Power Fault Power supply fault Normal operation
D11(Green) Status 0 See Status LED Definitions
D12(Red) Status 1 See Status LED Definitions
D16(Green) Done FPGA is configured FPGA is unconfigured
D2(Red) PS Error PS error occurred No PS error
D1(Green) PS Status PS is in secure lockdown state PS is operating normally
D3(Green) User LED Pin high Pin low
D4(Green) User LED Pin high Pin low
D5(Green) User LED Pin high Pin low
D6(Green) User LED Pin high Pin low
Table 4 : LED Definitions
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4.2 XMC Platform Interface
4.2.1 IPMI I2C
A 2 Kbit I2C EEPROM (type M24C02) is connected to the XMC IPMI. his memory contains board information
(type, voltage requirements etc.) as defined in the XMC based specification.
4.2.2 MBIST#
Built-In Self est. his output signal is connected to FPGA pin K10. It is not driven by default.
4.2.3 MVMRO
XMC Write Prohibit. his signal is an input from the carrier. When asserted (high), all writes to non-volatile
memories are inhibited. his is indicated by the Amber LED, D9.
he MVMRO signal has a 100KΩ pull-up resistor fitted by default.
his signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the PS at
pin K19.
4.2.4 MRSTI#
XMC Reset In. his signal is an active low input from the carrier. A this signal connected to the PS at pin G21.
his signal can also drive the PS power-on-reset pin depending on SW1-7
A buffered version of MRS I# is also connected to the FPGA at pin J12.
4.2.5 MRSTO#
XMC Reset Out. his optional output signal is driven from the FPGA pin K12.
4.2.6 MPRESENT#
Module Present. his output signal is connected directly to GND.
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4.3 JTAG Interface
4.3.1 On-board Interface
A J AG boundary scan chain is connected to header U12. his allows the connection of the Xilinx J AG cable for
FPGA debug using the Xilinx ChipScope tools.
he scan chain is shown in J AG Boundary Scan Chain:
Target FPGA
XCZU67DR
FFVE1156
VREF (3.3V)
HDR_TDI
HDR_TDO
Buffer
3.3V
En#
XMC
Con
(Pn5)
Header
U12
XMC_TDI
XMC_TDO
XMC_JTAG_EN# SW1-6
Figure 5 : JTAG Boundary Scan Chain
Note:
If the J AG chain is connected to the interface at the XMC connector (SW1-6 is ON), Header U12 should not
be used.
4.3.2 XMC Interface
he J AG interface on the XMC connector is normally unused and XMC_ DI connected directly to XMC_ DO.
he interface can be connected to the on-board interface (through level-translators) by switching SW1-6 ON. See
Switch Definitions
4.3.3 JTAG Voltages
he on-board J AG scan chain uses 3.3V. he Vcc supply provided on U12 to the J AG cable is +3.3V and is
protected by a poly fuse rated at 350mA.
he J AG signals at the XMC interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
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4.4 Clocks
he ADM-XRC-9R4 provides a wide variety of clocking options. he board has a user-programmable clock
generator. hese clocks can be combined with the FPGA's internal PLLs to suit a wide variety of communication
protocols.
Figure 6 : Full Clock Diagram
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4.4.1 3 MHz Reference Clocks (REFCLK3 M and FABRIC_CLK)
he fixed 300MHz reference clocks REFCLK300M and FABRIC_CLK are differential LVDS signals.
REFCLK300M is used as the input clock for both DDR4 SDRAM interfaces.
FABRIC_CLK is used as the reference clock for the IO delay control block (IDELAYC RL).
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
REFCLK300M 300 MHz IO_L11_ 1U_N8_GC_65 LVDS AJ16 AJ15
FABRIC_CLK 300 MHz IO_L14_ 2L_N2_GC_66 LVDS AM12 AM11
Table 5 : REFCLK3 M Connections
4.4.2 1 MHz Reference Clocks (REFCLK1 M)
he fixed 100MHz reference clock REFCLK100M are differential LVDS signals.
REFCLK100M is used as the reference clock for the PL MG banks.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
REFCLK100M 100 MHz MG REFCLK0_127 LVDS M28 M29
Table 6 : REFCLK1 M Connections
4.4.3 PCIe Reference Clocks (PCIEREFCLK)
he 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector, P5
at pins A19 and B19. his clock is buffered into two PCIe Express reference clocks that are forwarded to the PS
G R and PL G Y transceivers.
Signal Frequency FPGA Input IO Standard "P" pin "N" pin
PCIEREFCLK 100 MHz MG REFCLK1_128 LVDS F28 F29
Table 7 : PCIEREFCLK Connections
4.4.4 Programmable Clocks (PROGCLK -2)
here is one programmable clock source that is forwarded throughout the FPGA. his clock is programmable
through the USB system monitor. PROGCLK[2:1] is generated by a dedicated programmable clock generator IC
and offer extremely high frequency resolutions (1ppm increments). PROGCLK[2:1] are all buffered copies of the
same clock signal.
Contact [email protected] for details on re-programming this clock.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
PROGCLK1 10 - 1000 MHz MG REFCLK0_128 LVDS H28 H29
PROGCLK2 10 - 1000 MHz IO_L13_ 2L_N0_G
C_QBC_66 LVDS AL9 AM9
Table 8 : PROGCLK Connections
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4.4.5 MGT Reference Clocks
he PS and PL MG s can be clocked by sources from the P5, P6 or on-board clock sources
Figure 7 : MGT Clocks
4.4.6 PS System Clock
here PS is clocked by a fixed oscillator.
Signal Frequency FPGA pin
PS Ref Clock 50MHz M25
Table 9 : PS System Clock Connections
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