Alpha Data ADM-PA101 User manual

ADM-PA101
User Manual
Document Revision: 1.2
December 13th 2021

ADM-PA101 User Manual
© 2021 Co yright Al ha Data Parallel Systems Ltd.
All rights reserved.
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ublication may be re roduced, in any sha e or form, without rior written consent from Al ha
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ADM-PA101 User Manual
able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 2
2 Board Information ............................................................................................................................ 3
2.1 Physical Specifications .................................................................................................................. 3
2.2 Chassis Requirements ................................................................................................................... 4
2.2.1 PC Express ............................................................................................................................... 4
2.2.2 Mechanical Requirements ......................................................................................................... 4
2.2.3 Power Requirements ................................................................................................................. 4
2.3 Thermal Performance .................................................................................................................... 5
2.4 Customizations .............................................................................................................................. 5
3 Functional Descri tion .................................................................................................................... 6
3.1 Overview ........................................................................................................................................ 6
3.1.1 Switches .................................................................................................................................... 7
3.1.2 LEDs .......................................................................................................................................... 8
3.2 Clocking ......................................................................................................................................... 9
3.2.1 Si5328 ...................................................................................................................................... 10
3.2.2 PC e Reference Clocks ........................................................................................................... 10
3.2.3 Fabric Clock ............................................................................................................................. 10
3.2.4 PS Reference Clock (PS_REF_CLK) ...................................................................................... 10
3.2.5 MGT Programable Clock ......................................................................................................... 10
3.2.6 FMC Clocks ............................................................................................................................. 11
3.2.7 Samtec FireFly Clock ............................................................................................................... 11
3.2.8 Memory Clocks ........................................................................................................................ 11
3.3 PC Express ................................................................................................................................. 12
3.4 DDR4 SDRAM ............................................................................................................................. 12
3.5 FMC+ nterface ............................................................................................................................ 13
3.6 FireFly .......................................................................................................................................... 15
3.7 System Monitor ............................................................................................................................ 16
3.7.1 System Monitor Status LEDs ................................................................................................... 17
3.8 Micro USB nterface ..................................................................................................................... 18
3.9 Configuration ............................................................................................................................... 19
3.9.1 Configuration From QSP Flash Memory ................................................................................. 19
3.9.1.1 Building and Programming QSP Configuration mages ...................................................... 19
3.9.2 Configuration From uSD Flash Memory .................................................................................. 19
3.9.2.1 Building and Programming uSD Configuration mages ....................................................... 20
3.9.3 Configuration via JTAG ............................................................................................................ 20
3.9.4 Boot Modes .............................................................................................................................. 20
3.10 ULP USB nterface ..................................................................................................................... 22
3.11 UART interfaces .......................................................................................................................... 22
3.12 GEM0 ........................................................................................................................................... 23
3.13 User EEPROM ............................................................................................................................. 23
3.14 PMOD .......................................................................................................................................... 23
A endix A MIO Ma .......................................................................................................................................... 25
A endix B Com lete Pinout Table .................................................................................................................. 28
List of ables

ADM-PA101 User Manual
able 1 Mechanical Dimensions (Inc. Front Panel) ........................................................................................ 3
able 2 Available Power By Rail ..................................................................................................................... 4
able 3 Switch Functions ................................................................................................................................ 7
able 4 LED Details ........................................................................................................................................ 8
able 5 Si5328 address table ....................................................................................................................... 10
able 6 FMC+ Groups .................................................................................................................................. 14
able 7 Voltage, Current, and emperature Monitors ................................................................................... 16
able 8 Status LED Definitions ..................................................................................................................... 17
able 9 Boot Mode Selection ........................................................................................................................ 21
able 10 MIO Map .......................................................................................................................................... 25
able 11 Complete Pinout able ..................................................................................................................... 28
List of Figures
Figure 1 ADM-PA101 Product Photo ............................................................................................................... 1
Figure 2 hermal Performance ........................................................................................................................ 5
Figure 3 ADM-PA101 Block Diagram ............................................................................................................... 6
Figure 4 Switches ............................................................................................................................................ 7
Figure 5 Front Panel LEDs .............................................................................................................................. 8
Figure 6 Clock opology .................................................................................................................................. 9
Figure 7 DDR4 bank locations by index ......................................................................................................... 12
Figure 8 FMC+ Location ................................................................................................................................ 13
Figure 9 FireFly Locations ............................................................................................................................. 15
Figure 10 USB Location ................................................................................................................................... 18
Figure 11 uSD Location ................................................................................................................................... 20
Figure 12 ULPI USB Location .......................................................................................................................... 22
Figure 13 GEM0 Ethernet Location ................................................................................................................. 23

ADM-PA101 User Manual
1 Introduction
he ADM-PA101 is a high-performance reconfigurable computing card featuring the latest Xilinx Adaptive
Compute Acceleration Platform (ACAP) platform known as Versal. he PCIe form factor is ideal for Data Center
applications and general evaluation and deployment of this new architecture. he card features a full FMC+
interface, two banks of 72-bit DDR4-SDRAM, front panel Ethernet, PMOD, USB, and Samtec FireFly.
Figure 1 : ADM-PA101 Product Photo
1.1 Key Features
Key Features
• PCIe Gen3 x16 and dual Gen4x8 capable
• 2-slot active or passive heat sink
• 3/4 length, full profile, x16 edge PCIe form factor
• Supports Versal XCVM1802 ACAP devices in the VSVA2197 package
• FMC+ front panel interface:
• 24 high speed serial channels capable of 32Gbps each
• 160 single ended general purpose signals (80 differential pairs)
• 1.5-1.0V VADJ voltage range
• Extra clearance for optical cages
• Versatile MIO interface support:
• GEM0 Ethernet access through RJ45 at front panel
• 12 MIO GPIO accessible at rear
• uSD
• Dual QSPI
• ULPI USB PHY accessible at USBA receptacle
• 2x UAR broken out through micro-USB at PCIe front panel and rear
• wo separate banks of 64 bit + ECC (72 bit total) DDR4-3200 SDRAM
• One internal FireFly site with 4 channels each capable of 28Gbps operation
• Front panel and rear edge J AG access via USB port
• ACAP configurable over USB/J AG and SPI configuration flash
• Voltage, current, and temperature monitoring
• Digilent PMOD 3.3V, 12-pin interface accessible to PL
• 2 user LEDs and 2 user switches
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1.2 Order Code
See the PA101 datasheet for complete ordering options.
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ADM-PA101 User Manual
2 Board Information
2.1 Physical S ecifications
he ADM-PA101 complies with PCI Express CEM revision 4.0.
Description Measure
otal Dy 126.3 mm
PCB Dy 111.15 mm
otal Dx 267.2 mm
PCB Dx 254 mm
otal Dz 19.6 mm
Circuit assembly weight 210 grams
otal weight (with heat sink) 730 grams
Table 1 : Mechanical Dimensions (Inc. Front Panel)
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ADM-PA101 User Manual
2.2 Chassis Requirements
2.2.1 PCI Ex ress
he ADM-PA100 is capable of PCIe Gen 1/2/3 with 1/4/8/16 lanes, and PCIe Gen 4 with 1/4/8 lanes when using
the Xilinx Integrated Block for PCI Express. PCIe Gen 4x8 can be bifurcated into two slots to acheive an
aggregate bandwidth of a 16 lane connection.
2.2.2 Mechanical Requirements
A 16 lane physical PCIe slot is required for mechanical compatibility.
It is possible to operate this product standalone with power from the 8-pin A X power connector alone. his
requires a small build change to the board. Please contact sales@al ha-data.com for details.
2.2.3 Power Requirements
he ADM-PA101 draws power from the PCIe Edge and the 8-pin A X power connector. he ADM-PA101 does
not use or require the 3.3V power from the PCIe Edge (though it does use 3.3V AUX). o operate with PCIe edge
only, ensure SW1-8 is OFF (see Switches). As per PCIe specification, users should limit the board power
consumption to 66W when using only the PCIe edge power. Adding the 8-pin A X connector provides additional
150W of power, bringing the total board power dissipation maximum to 216W.
Power consumption estimation requires the use of the Xilinx XPE spreadsheet (www.xilinx.com/products/
technology/power/xpe.html ) and a power estimator tool available from Alpha Data. Please contact
su ort@al ha-data.com to obtain this tool.
he power available to the rails calculated using XPE are as follows:
Voltage Source Name Current Capability
0.85-0.90 VCC_IN 150A
0.85-0.90 VCC_IO + VCC_PMC + VCC_PSFP + VCC_PSLP + VCC_RAM +
VCC_SOC 10A
0.88 MG AVCC 8A
1.2 MG AV 8A
1.2 VCCO + DDR4 8A
1.5 G Y_AVCCAUX 2A
1.5 VCCO + VCCAUX + VCCAUX_PMC 8A
1.0-1.5 FMC_VADJ + VCCO 8A
3.3 VCCO + FMC+ 8A
Table 2 : Available Power By Rail
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ADM-PA101 User Manual
2.3 Thermal Performance
If the ACAP core temperature exceeds 105 degrees Celsius, the ACAP design will be cleared to prevent the card
from over-heating.
he ADM-PA101 comes with a heat sink to avoid thermal overstress of ACAP, since it is typically the hottest point
on the card. he ACAP die temperature must remain under 100 degrees Celsius. o estimate the ACAP die
temperature: first take your total board power (see next paragraph), then multiply by heta JA from the graph
below, and add the resulting temperature to your system internal ambient temperature.
he power dissipation can be estimated by using the Alpha Data power estimator in conjunction with the Xilinx
Power Estimator (XPE) downloadable at www.xilinx.com/products/technology/power/xpe.html . Download the
Versal tool and set the device according to your part number details: Versal AI Core Series, XCVC1902,
VSVA2197 package, -2MS/-3HS speed grade, extended. Set the ambient temperature to your system ambient
and select 'user override' for the effective theta JA. hen enter the figure associated with your system LFM in the
blank field. Proceed to enter all applicable design elements and utilization in the following spreadsheet tabs. Next
acquire the PA101 power estimator from Alpha Data by contacting su ort@al ha-data.com. Enter in the
power figures from XPE, FMC+ (if used), and DRAM utilization into the Alpha Data spreadsheet to get a
complete board level estimate.
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
0.00 200.00 400.00 600.00 800.00 1000.00 1200.00 1400.00 1600.00 1800.00 2000.00
Theta JA
Linear Feet per Minute (LFM)
ADM-PA101 Board Level Thermal Performance
Figure 2 : Thermal Performance
2.4 Customizations
Alpha Data provides extensive customization options to existing commercial off-the-shelf (CO S) products.
Some options include, but are not limited to: custom front panel interfaces, additional networking cages in
adjacent slots, enhanced heat sinks, baffles, and circuit additions.
Please contact sales@al ha-data.com to get a quote and start your project today.
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ADM-PA101 User Manual
3 Functional Descri tion
3.1 Overview
he ADM-PA101 is a high-performance reconfigurable computing card featuring the latest Xilinx Adaptive
Compute Acceleration Platform (ACAP) platform with the Versal XCVC1902, a full FMC+ interface, PCIe
Gen3x16 or 2xGen4x8 interface, two banks of DDR4-3200 each 72 bits wide (for 64 bits with 8 bits ECC), GEM0
Ethernet, QSPI, uSD, USB, UAR , a Digilent PMOD site, one Samtec FireFly site capable of 28G/channel in
either optical or copper cabling, and a robust system monitor.
Figure 3 : ADM-PA101 Block Diagram
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ADM-PA101 User Manual
3.1.1 Switches
he ADM-PA101 has two octal DIP switch SW1 and SW2, located on the rear side of the board. he function of
each switch is detailed below:
Figure 4 : Switches
Switch Factory
Default Function OFF State ON State
SW1-1 ON BootMode 0 See able 9
SW1-2 OFF BootMode 1 See able 9
SW1-3 OFF BootMode 2 See able 9
SW1-4 OFF BootMode 3 See able 9
SW1-5 OFF Reserved BD BD
SW1-6 ON 12V Auto-detect 12V PCIe edge auto-detect A X AUX power required
SW1-7 ON Reserved BD BD
SW1-8 OFF Power Off Board will power up Immediately power down
SW2-1 OFF Factory Configuration Normal operation -
SW2-2 ON Factory Configuration - Normal operation
SW2-3 OFF HOS _I2C_EN System Monitor connected to
PCIe slot I2C System Monitor isolated from PCIe slot I2C
SW2-4 OFF Service Mode System Monitor normal
operation System Monitor Service Mode (firmware update etc.)
SW2-5 OFF PERS to POR_B PCIE RESE isolated from
POR_B PCIE RESE will drive POR_B low
SW2-6 OFF POR_B ACAP power on reset
released ACAP power on reset active
SW2-7 OFF User Switch 0 Pin G36 = '1' Pin G36 = '0'
SW2-7 OFF User Switch 1 Pin G37 = '1' Pin G37 = '0'
Table 3 : Switch Functions
Use I/O Standard "LVCMOS15" when constraining the User Switch pins.
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ADM-PA101 User Manual
3.1.2 LEDs
here are 6 LEDs on the ADM-PA101, 2 of which are general purpose and whose meaning can be defined by
the user. he other 4 have fixed functions described below:
D13
D12 D14
DONE_L STAT_1
D15
STAT_0
Status LEDsUser LEDs
D11
USER_LED
_G0
D6
USER_LED
_G1
ERROR
_OUT_L
Figure 5 : Front Panel LEDs
Comp.
Ref. Function/Net Name ON State OFF State
D6 USER_LED_G1_1V8 User defined '0' User defined '1'
D11 USER_LED_G0_1V8 User defined '0' User defined '1'
D12 ERROR_OU _L Boot error No error reported
D13 DONE_L PL is configured PL is not configured
D14 Status 1 See Status LED Definitions
D15 Status 0 See Status LED Definitions
Table 4 : LED Details
See Section Complete Pinout able for full list of user controlled LED nets and pins
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ADM-PA101 User Manual
3.2 Clocking
he ADM-PA101 provides flexible reference clock solutions for the many multi-gigabit transceiver quads, DDR4
banks, and PL fabric. Any programmable clock, from the Si5338 Clock Synthesizer, is reconfigurable from the
front panel Micro USB Interface by using Alpha Data’s avr2util utility. his allows the user to configure almost any
arbitrary clock frequency during application run time. he maximum clock frequency is 350MHz. Customers who
purchase RD-PA101 also have the option of embedding IP into their ACAP design that permits programmable
clock reconfiguration via PCIe or from within the ACAP.
here is one available Si5328 jitter attenuator. his can provide clean and synchronous clocks to the FMC+ quad
locations at many clock frequencies. hese devices use volatile memory, so the ACAP design will need to
reconfigure the register map over I2C after any power cycle.
All clock names in the section below can be found in Complete Pinout able.
SI5328_REFCLK_IN (MGTREFCLK1_200)
Si5328_0
(2.5V VCC)
Address: 1101000
CM DE = GND
I2C +
CNTRL
CLK UT2
CLK UT1
Crystal
114.285MHz
XA/XB
CLKIN1
CLKIN2
FPGA Bank 710
SI5328_1V5_SDA
SI5328_1V5_SCL
SI5328_0_RST_1V5_L
SI5328_1V5_INT_C1B
SI5328_1V5_C2B
SI5328_1V5_L L
MGT_PR GCLK_0 (MGTREFCLK0_200)
PCIE_LCL_REFCLK 100MHz GTY_REFCLK0_104
PCIe
Edge
U36
(ASFLMPLV-
100.000MHZ-LR-T)
PCIE_REFCLK_0 100MHz std. GTY_REFCLK0_103
Buffer
NB6N11S PCIE_REFCLK_1 100MHz std. GTY_REFCLK0_105
FABRIC_CLK 300MHz Default (I Bank 710)
25MHz
30ppm
Source
Si5338
Clock
Synth
0
1
2
3
Buffer
CDCLVD1208
MEM_CLK_0 300MHz Default (I Bank 701)
MEM_CLK_1 300MHz Default (I Bank 704)
FIREFLY_CLK 350MHz Default (GTY_REFCLK0_206)
Buffer
NB6L11S
DP[0-3]DP[4-7]DP[8-11]DP[12-15]DP[16-19]DP[20-23]
FPGA quads connected to FMC+
SI5328_ UT_0 (MGTREFCLK1_201)
MGT_PR GCLK_1 (MGTREFCLK0_201)
GBTCLK2_M2C (MGTREFCLK1_202)
MGT_PR GCLK_2 (MGTREFCLK0_202)
GBTCLK3_M2C (MGTREFCLK1_203)
MGT_PR GCLK_3 (MGTREFCLK0_203)
SI5328_ UT_1 (MGTREFCLK1_204)
MGT_PR GCLK_4 (MGTREFCLK0_204)
GBTCLK6_M2C (MGTREFCLK1_205)
MGT_PR GCLK_5 (MGTREFCLK0_205)
MGT_PR GCLK_7 156.25MHz Default (GTY_REFCLK1_206)
FMC+
GBTCLK0_M2C
GBTCLK1_M2C
GBTCLK2_M2C
GBTCLK3_M2C
GBTCLK4_M2C
GBTCLK5_M2C
=> A build modification can connect this line
Figure 6 : Clock To ology
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ADM-PA101 User Manual
3.2.1 Si5328
If jitter attenuation is required please see the reference documentation for the Si5328.
www.silabs.com/Support%20Documents/ echnicalDocs/Si5328.pdf
here are two input clock options. Si5328 pin CLKIN1 (board net name SI5328_REFCLK_IN_P/N) of the Si5328
is connected to an MG clock output for the most direct clock recovery architecture. Si5328 pin CLKIN2 (board
net name MG _PROGCLK_6_P/N) of the Si5328 is connected to a programable clock from the onboard clock
synthesizer.
he two output clocks are connected to quads 201 and 204 to provide clocking capability to the entire FMC+
interface.
he IN _C1B and LOL signals for the Si5328 is available for use, and can be located at net names
SI5328_1V5_IN _C1B and SI5328_1V5_LOL in the Complete Pinout able.
he active low reset of the Si5328 is accessible to the ACAP. See net names SI5328_1V5_RS _L in the
Complete Pinout able.
Note:
Each sideband signal has an external pull-up resistor.
he Si5328 configuration register map is volatile, and must be written on each power up event over I2C. Use
nets SI5328_1V5_SDA and SI5328_1V5_SCL at pins located in the Complete Pinout able. he Si5328 device
is configured the I2C address shown in the table below:
device 7bit Hex Address Binary Address
Si5328 68 110_1000
Table 5 : Si5328 address table
3.2.2 PCIe Reference Clocks
he 16 MG lanes connected to the PCIe card edge use MG tiles 103 through 106 and use the host system's
100 MHz PCIe reference clock (net name PCIE_REFCLK_0_P/N or PCIE_REFCLK_1_P/N in the Complete
Pinout able).
Alternatively, a more stable but asynchronous onboard 100MHz clock is available as well (net name
PCIE_LCL_REFCLK_P/N in the Complete Pinout able).
3.2.3 Fabric Clock
he design offers a fabric clock (net name FABRIC_CLK_P/N) which defaults to 300 MHz. his clock is intended
to be used for IDELAY elements in PL designs. he fabric clock is connected to a Global Clock (GC) pin. his
clock frequency can be changed to any arbitrary clock frequency up to 350MHz by re-programing the Si5338
reprogrammable clock oscillator. See details on avr2util in the section: Micro USB Interface.
Use constraints DIFF_ ERM_ADV = ERM_100 and IOS ANDARD LVDS15 for this reference clock.
See net names FABRIC_CLK_P/N in the Complete Pinout able for pin locations.
3.2.4 PS Reference Clock (PS_REF_CLK)
A 50MHz clock is fed into the dedicated REF_CLK_503 pin to drive the processor system.
3.2.5 MGT Programable Clock
he MG reference clock connects to each quad connected to the FMC connector, the Si5328, and the FireFly
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ADM-PA101 User Manual
quad. his programable clock has a default 156.25MHz reference clock. his clock frequency can be changed to
any arbitrary clock frequency up to 350MHz by re-programing the Si5338 reprogrammable clock oscillator. See
details on avr2util in the section: Micro USB Interface.
See net names MG _PROGCLK_*_PIN_P/N in the Complete Pinout able for pin locations.
3.2.6 FMC Clocks
he FMC specification defines 6 gigabit transceiver clocks (GB CLK*), one for each four high speed serial lanes.
By default only GB CLK2, GB CLK3, and GB CLK6 are connected. he other three can be connected through
a build option custimzation.
he specification also defines 4 general clocks (CLK*_M2C and CLK*_BDIR). Each of these clocks have
external AC coupling, DC bias, and 100 ohm termination (suitable for LVDS).
See ANSI/VI A 46.0 and ANSI/VI A 57.4 for full details of the FMC specification.
See net names GB CLK*_PIN_P/N, CLK*_M2C_PIN_P/N, and CLK*_BIDIR_PIN_P/N in the Complete Pinout
able for pin locations.
he ACAP quads connected to the FMC site are also configured such that they can be clocked from the Si5328
jitter attenuator, or the onboard Si5338 clock synthesizer.
Pin locations of net names SI5328_*_OU _P/N and MG _PROGCLK_*_P/N can be located in the Complete
Pinout able.
3.2.7 Samtec FireFly Clock
he FireFly clock has a default 350MHz reference clock. his clock frequency can be changed to any arbitrary
clock frequency up to 350MHz by re-programing the Si5338 reprogrammable clock oscillator. See details on
avr2util in the section: Micro USB Interface.
See net names FIREFLY_CLK_PIN_P/N in the Complete Pinout able for pin locations.
3.2.8 Memory Clocks
Each of the two memory banks has their own buffered 300MHz reference clock. his clock frequency can be
changed to any arbitrary clock frequency up to 350MHz by re-programing the Si5338 reprogrammable clock
oscillator. See details on avr2util in the section: Micro USB Interface.
See net names MEM_CLK_*_PIN_P/N in the Complete Pinout able for pin locations.
See DDR4 SDRAM for mor information on the memory banks and their physical locations.
hese clocks are not fabric accessible, but are reserved for the Versal DDR4 cores.
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3.3 PCI Ex ress
he ADM-PA100 is capable of PCIe Gen 1/2/3 with 1/4/8/16 lanes and Gen 4 with 1/4/8 lanes. he ACAP drives
these lanes directly using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and
number of lanes is generally automatic and does not require user intervention.
PCI Express reset (PERS #) is connected to the ACAP through a buffer. See Complete Pinout able signal
PERS _PL_L for fabric accessible location, and PCIE_RS _1V8_L for the PS location.
he pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout able,
see net names PCIE_ X*_PIN_P/N and PCIE_RX*_P/N.
3.4 DDR4 SDRAM
wo banks of DDR4 SDRAM memory are soldered down to the board. he available density of the memory is
4GB/per bank, 8GB total. he memory interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate is
3200 M /s.
Memory solutions are available from the Xilinx (See Xilinx PG313 Versal ACAP Programmable
Network on Chip and Integrated Memory Controller v1.0). DDR4_0 uses the Non-Flipped Pinout, and DDR4_1
uses the Flipped Pinout. An example memory exerciser project is included in the RD-PA101. All pin location
information is included in Complete Pinout able.
he 4Gb components used are Micron M 40A1G16RC-062E
Figure 7 : DDR4 bank locations by index
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ADM-PA101 User Manual
3.5 FMC+ Interface
he FMC+ interface provides a high-performance and flexible front-panel interface through a range of
interchangeable industry standard IO modules.
he FMC+ interface adheres to VI A 57.4. he ADM-PA101 utilizes all possible FMC+ connectivity. his includes
all GPIO, all MG links, and all clock capable IO.
FMC I2C signal (SCL and SDA at C30 and C31) are connected to the system monitor microcontroller. hey are
used to determine operating voltage during startup and are not accessible to the user directly, but can be
accessed through the system monitor AVR2U IL application.
Alpha Data provides a wide range of compatible FMC cards: Please see www.alpha-data.com/products/
io-adaptors/ , or contact sales@al ha-data.com for more details.
It is possible for Alpha Data to pre-fit the ADM-PA101 with FMC+ modules. Please contact
sales@al ha-data.com for full details and options.
he FMC Present signal (PRSN _M2C_L at connector pin H2) is connected to the system monitor
microcontroller.
Note:
he ADM-PA101 supports only 1.5V and lower VADJ Voltages.
he ADM-PA101 provides additional keep out space in the FMC area to enable oversized FMC cards. his is
ideal for pluggable optical modules like QSFP-DD. See Alpha Data FMC-PLUS-QSFP-DD for one example.
Figure 8 : FMC+ Location
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ADM-PA101 User Manual
he FMC+ Connector has GPIO connections arranged as follows:
Group ACAP
Bank Name Function
LA_0 66 LA(12:2) 11 diff. Pairs / 22 single-ended
LA_CC (1:0) 2x Regional Clocks / GPIO pairs / 4 single-ended
LA_1 65 LA(33:19) 15 diff. Pairs / 30 single-ended
LA_CC (18:17) 2x Regional Clocks / GPIO pairs / 4 single-ended
HA_0 66,67
HA(16:2) 15 diff. Pairs / 30 single-ended
HA_CC (1:0) 2x Regional Clocks / GPIO pairs / 4 single-ended
HA(23:18) 6 diff. Pairs / 12 single-ended
HA_CC (17) Regional Clock / GPIO pair / 2 single-ended
HB_0 64
HB(5:1) 5 diff. Pairs / 10 single-ended
HB(16:7) 10 diff. Pairs / 20 single-ended
HB(21:18) 4 diff. Pairs / 8 single-ended
HB_CC (0) Regional Clock / GPIO pair / 2 single-ended
HB_CC (6) Regional Clock / GPIO pair / 2 single-ended
HB_CC (17) Regional Clock / GPIO pair / 2 single-ended
Table 6 : FMC+ Grou s
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3.6 FireFly
here is one FireFly site available on the circuit board. he site is capable of hosting either active optical or
passive copper FireFly connectors. he communication interface can run at up to 28Gbps per channel in either
cable type. here are 4 channels on the FireFly site (total maximum bandwidth of 114Gbps). his site is ideally
suited for 4x 10G/25G, 1x 100G Ethernet, or any other protocol supported by the Xilinx G Y ransceivers.
Please see Xilinx User Guide UG578 for more details on the capabilities of the transceivers.
All FireFly sites have control signals connected to the ACAP. heir connectivity is detailed in the Complete Pinout
able at the end of this document. he notation used in the pin assignments is FIREFLY* with locations clarified
in the diagram below.
Figure 9 : FireFly Locations
he management interface of each FireFly module is connected directly to the ACAP. Each low speed sideband
signals (MODPRS, IN _L, RS _L, SDA, SCL) has an external pull-up resistor.
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ADM-PA101 User Manual
3.7 System Monitor
he ADM-PA101 has the ability to monitor select temperatures, voltages, and currents in order to provide an
indication of board health. he monitoring is implemented using an AVR microcontroller. his information can be
read out via USB using the avr2util utility. Alternatively, the sensor information can be read directly by the ACAP
or via PCIe if RD-PA101 is purchased (reference design package).
If the core ACAP temperature exceeds 105 degrees Celsius, the ACAP image will be cleared to prevent damage
to the card.
Monitors Identifier Purpose/Description
E C E C Elapsed time counter (seconds)
EC EC Event counter (power cycles)
12V_AUX ADC00 12V board input supply from 8-pin A X Cable
12V_EDGE ADC01 12V board input supply from PCIe Edge
12V_EDGE_I ADC02 12V board input current from PCIe Edge in amps
3V3_AUX ADC03 3.3V auxiliary board input supply from PCIE edge
3V3_DIG ADC04 3.3V generated onboard for FMC and other circuits
3V3_VCCO ADC05 3.3V generated onboard for ACAP IO voltage (VCCO)
1V8_DIG ADC06 1.8V generated onboard for ACAP IO voltage (VCCO)
1V5_DIG ADC07 1.5V generated onboard for ACAP IO voltage (VCCO)
1V5_AVCCAUX ADC08 1.5V generated onboard for ACAP Aux voltage
1V2_AV ADC09 1.2V generated onboard for transceiver Power (AV )
1V2_DIG ADC10 1.2V generated onboard for SDRAM and ACAP (VCCO)
0V88_AVCC ADC11 0.88V generated onboard for transceiver Power (AVCC)
VCC_IN ADC12 0.8V generated onboard for ACAP core and AI power
FMC_VADJ ADC13 1.0-1.5V generated onboard for FMC VADJ and ACAP (VCCO)
uC_ emp MP00 uC on-die temperature
Board0_ emp MP01 Board temperature near FMC connector (U24)
Board1_ emp MP02 Board temperature near back edge (U57)
ACAP_ emp MP03 ACAP on-die temperature
Table 7 : Voltage, Current, and Tem erature Monitors
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