Alpha Data ADM-XRC-7Z1 User manual

ADM-XRC-7Z1
User Manual
Document Revision: 2.6
14th ebruary 2022

ADM-XRC-7Z1 User Manual
V2.6 - 14th ebruary 2022
© 2022 Copyright Alpha Data Parallel Systems Ltd.
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Data Parallel Systems Ltd.
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All trademarks are the property of their respective owners.

ADM-XRC-7Z1 User Manual
V2.6 - 14th ebruary 2022
able Of Contents
1 Overview ........................................................................................................................................... 1
1.1 Introd ction .................................................................................................................................... 1
1.2 Key Feat res ................................................................................................................................. 1
1.3 Order Code .................................................................................................................................... 2
1.4 References & Specifications .......................................................................................................... 2
2 PCB Information .............................................................................................................................. 3
2.1 Physical Specifications .................................................................................................................. 3
2.2 Motherboard / Carrier Req irements ............................................................................................. 3
2.3 Power Req irements ..................................................................................................................... 3
3 Installation ........................................................................................................................................ 4
3.1 Software Installation ...................................................................................................................... 4
3.2 Hardware Installation ..................................................................................................................... 4
3.2.1 Handling Instr ctions ................................................................................................................. 4
3.2.2 Installation in ADC-XMC-Breako t Carrier ................................................................................. 4
4 unctional Description .................................................................................................................... 5
4.1 Overview ........................................................................................................................................ 5
4.1.1 Switch Definitions ...................................................................................................................... 6
4.1.2 LED Definitions .......................................................................................................................... 7
4.2 Primary XMC Connector P5 .......................................................................................................... 8
4.2.1 XMC Platform Interface ............................................................................................................. 8
4.2.1.1 IPMI I2C ................................................................................................................................. 8
4.2.1.2 MBIST# .................................................................................................................................. 8
4.2.1.3 MVMRO ................................................................................................................................. 8
4.2.1.4 MRSTI# .................................................................................................................................. 8
4.2.1.5 MRSTO# ................................................................................................................................ 8
4.2.1.6 MPRESENT# ......................................................................................................................... 9
4.2.1.7 JTAG ...................................................................................................................................... 9
4.2.2 P5 HSSIO Links ......................................................................................................................... 9
4.3 Secondary XMC Connector P6 ...................................................................................................... 9
4.3.1 P6 HSSIO Links ......................................................................................................................... 9
4.3.2 P6 GPIO Signals ........................................................................................................................ 9
4.4 PrPMC Connector P4 .................................................................................................................... 9
4.5 JTAG Interfaces ........................................................................................................................... 10
4.5.1 On-board Interface ................................................................................................................... 10
4.5.2 XMC Interface .......................................................................................................................... 10
4.5.3 JTAG Voltages ......................................................................................................................... 10
4.6 Clocks .......................................................................................................................................... 10
4.6.1 PCIe Reference Clock (PCIEREFCLK) ................................................................................... 10
4.6.2 P6 Reference Clock (P6REFCLK) ........................................................................................... 11
4.6.3 MGTCLK250M ......................................................................................................................... 11
4.6.4 PROGCLK ............................................................................................................................... 11
4.6.5 REFCLK200M .......................................................................................................................... 12
4.6.6 PS_CLK33M3 .......................................................................................................................... 12
4.6.7 USB_REFCLK24M .................................................................................................................. 12
4.6.8 ETH_CLK25M .......................................................................................................................... 12
4.6.9 ETH1_CLK125M ...................................................................................................................... 12
4.7 Resets .......................................................................................................................................... 12
4.8 Zynq PS Block ............................................................................................................................. 13
4.8.1 Boot Modes .............................................................................................................................. 13
4.8.2 PS Memory Interfaces ............................................................................................................. 13
4.8.2.1 Q ad SPI Flash Memory ..................................................................................................... 13
4.8.2.2 MicroSD Flash Memory ....................................................................................................... 13

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4.8.2.3 PS DDR3 Memory ............................................................................................................... 13
4.8.3 Ethernet Interfaces .................................................................................................................. 13
4.8.4 Serial COM Ports ..................................................................................................................... 15
4.8.5 USB Interfaces ......................................................................................................................... 15
4.9 Zynq PL Block .............................................................................................................................. 15
4.9.1 PL DDR3 Memory .................................................................................................................... 15
4.9.2 XRM Interface and Front-Panel I/O ......................................................................................... 15
4.9.2.1 XRM Connector, CN1 .......................................................................................................... 16
4.9.2.2 XRM Connector CN2 ........................................................................................................... 16
4.9.2.3 XRM I/F - GPIO ................................................................................................................... 16
4.9.2.4 XRM I/F - High-speed Serial Links ...................................................................................... 16
4.9.2.5 XRM IO Voltage Override .................................................................................................... 16
4.9.3 GTX Links ................................................................................................................................ 17
4.9.4 Rear GPIO Interface ................................................................................................................ 18
4.10 System Monitoring ....................................................................................................................... 19
4.10.1 A tomatic Temperat re Monitoring .......................................................................................... 19
4.10.2 System Monitor Stat s LEDs ................................................................................................... 20
Appendix A Rear Connector Pinouts ............................................................................................................... 21
A.1 Primary XMC Connector, P5 ........................................................................................................ 21
A.2 Secondary XMC Connector, P6 ................................................................................................... 22
A.3 PMC Connector P4 ...................................................................................................................... 23
Appendix B ront (XRM) Connector Pinouts ................................................................................................... 24
B.1 XRM Connector CN1, Field 1 ...................................................................................................... 25
B.2 XRM Connector CN1, Field 2 ...................................................................................................... 26
B.3 XRM Connector CN1, Field 3 ...................................................................................................... 27
B.4 XRM Connector CN2 ................................................................................................................... 28
Appendix C XMC Breakout PGA Pinout ......................................................................................................... 29
List of ables
able 1 Build Options ..................................................................................................................................... 2
able 2 References ........................................................................................................................................ 2
able 3 Physical Specifications ...................................................................................................................... 3
able 4 Switch 1 Definitions ........................................................................................................................... 6
able 5 Switch 2 Definitions ........................................................................................................................... 6
able 6 Main LED Definitions ......................................................................................................................... 7
able 7 Ethernet LED Definitions ................................................................................................................... 8
able 8 PCIEREFCLK Connections ............................................................................................................. 11
able 9 P6REFCLK Connections ................................................................................................................. 11
able 10 MG CLK250M Connections ............................................................................................................ 11
able 11 PROGCLK Connections .................................................................................................................. 11
able 12 REFCLK200M Connections ............................................................................................................. 12
able 13 PS_CLK33M3 Connections ............................................................................................................. 12
able 14 E H1_CLK125M Connections ......................................................................................................... 12
able 15 Boot Mode Selection ........................................................................................................................ 13
able 16 Ethernet Status LEDs ...................................................................................................................... 14
able 17 XRM GPIO Groups .......................................................................................................................... 16
able 18 PL RearMG Mapping ..................................................................................................................... 17
able 19 PL RearMG Mapping ..................................................................................................................... 17
able 20 PL Rear GPIO Mapping ................................................................................................................... 18
able 21 Voltage and emperature Monitors (in microcontroller) ................................................................... 19

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able 22 emperature Limits .......................................................................................................................... 20
able 23 System Monitor Status LEDs ........................................................................................................... 20
able 24 XMC Connector P5 .......................................................................................................................... 21
able 25 XMC Connector P6 .......................................................................................................................... 22
able 26 PMC Connector P4 .......................................................................................................................... 23
able 27 XRM Connector CN1, Field 1 .......................................................................................................... 25
able 28 XRM Connector CN1, Field 2 .......................................................................................................... 26
able 29 XRM Connector CN1, Field 3 .......................................................................................................... 27
able 30 XRM Connector CN2 ....................................................................................................................... 28
able 31 XMC Connector P5 .......................................................................................................................... 29
List of Figures
Figure 1 ADM-XRC-7Z1 Block Diagram .......................................................................................................... 5
Figure 2 LED Locations ................................................................................................................................... 7
Figure 3 Ethernet Interfaces .......................................................................................................................... 13
Figure 4 Serial COM Ports ............................................................................................................................. 15
Figure 5 USB Interfaces ................................................................................................................................. 15

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1 Overview
1.1 Introduction
he ADM-XRC-7Z1 ("7Z1") is a high-performance Processor XMC for applications using Zynq-7000 SoCs from
Xilinx.
1.2 Key eatures
Key eatures
• Single-width XMC, compliant to VI A Standard 42.0, 42.3 and 42.10d12
• Zynq Z-7045 EPP in FFG900 package
• Processing System (PS) Block consisting of:
. 1 bank of DDR3 SDRAM, 512MB
. Quad SPI Flash memory, two 256Mb devices in dual-stacked configuration
. Removable Secure Digital (SD) Flash memory (Commercial Spec Option)
. Ethernet interface to rear-panel P4 connector
. Serial COM port connection to rear P4 connector
. wo USB ports to rear P4 connector
. One USB port to micro USB connector (Commercial Spec Option)
• Programmable Logic (PL) Block consisting of:
. 2 banks of DDR3 SDRAM, 256MB per bank
. Ethernet interface to rear-panel P4 connector
. Serial COM port connection to rear P4 connector
• "XRM" Front Panel IO Interface with:
. 146 GPIO configurable as single-ended or differential signals
. Up to 8 multi-gigabit High-Speed Serial IO (HSSIO)
. Mux option for direct connections of Ethernet, USB and COM ports to Processor System
. Reference clocks
• XMC Rear IO Interface P5:
. VI A 42.3 Pinout
. 8 HSSIO links to FPGA for PCI Express or user defined interface
. PCI Express reference clock input
• XMC Rear IO Interface P6:
. VI A 46.9d23 X38s+X12d+X8d compatible pinout
. 8 HSSIO links (mux with XRM interface)
. 38 GPIO
. Reference clock input
• PMC Rear IO Interface P4:
. wo Gigabit Ethernet interfaces
. wo USB Ports
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. wo Serial COM ports
• Platform manager with system monitoring
1.3 Order Code
ADM-XRC-7Z1/z-y(c)
Name Symbol Configurations
Kintex-7 Device z Z045 , Z100
Kintex-7 Speed y 1 , 2 , 3
Cooling c
blank = air cooled commercial
/ACE = Extended air cooled commercial
/AC1 = air cooled industrial
/CC1 = conduction cooled industrial
Table 1 : Build Options
Not all combinations are available. Please check with Alpha Data sales for details.
1.4 References & Specifications
ANSI/VI A 42.0 XMC Standard, December 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 42.3 XMC PCI Express Protocol Layer Standard, June 2006, VI A, ISBN 1-885731-43-4
ANSI/IEEE 1386-2001 IEEE Standard for a Common Mezzanine Card (CMC) Family, October 2001, IEEE,
ISBN 0-7381-2829-5
ANSI/IEEE 1386.1-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC),
October 2001, IEEE, ISBN 0-7381-2831-7
ANSI/VI A 20-2001
(R2005) Cond ction Cooled PMC, February 2005, VI A, ISBN 1-885731-26-4
Table 2 : References
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2 PCB Information
2.1 Physical Specifications
Form Factor Single Width XMC
Length (air-cooled) 149.0 mm
Length (conduction-cooled) 143.75 mm
Width 74.0 mm
Height 10.0 mm
Weight (air-cooled) BD
Weight (conduction-cooled) BD
Table 3 : Physical Specifications
2.2 Motherboard / Carrier Requirements
he 7Z1 is a single width XMC.3 mezzanine with P5, P6 and P4 connectors.
he 7Z1 is compatible with either 5V or 12V on the "VPWR" power rail.
he Primary XMC connector, P5, is compatible with the XMC.3 (VI A 42.3) specification for PCI Express
applications.
he Secondary XMC connector, P6 also has a pinout compatible with XMC.3. Since carriers may have differing
pinouts on this connector, it is important to check compatibility prior to installation. If in doubt, please contact
Alpha Data for assistance.
IMPORTANT
Connector P6 on the card is not compatible with the VI A 42.10 (XMC GPIO) Standard. In particular, USB
VCC must not be applied on this connector.
he PMC connector, P4, has the main interfaces to the ARM Processing System (PS): Ethernet, USB and serial
ports. he pinout of this connector is compatible with other commercially available PrPMCs but is not defined by
a VI A standard. It is important to check carrier card compatibility prior to installation. If in doubt, please contact
Alpha Data for assistance.
IMPORTANT
Connector P4 has +5V (power) -/+6V (serial port) levels. It must not be connected to the Alpha Data
ADM-EMC-II or ADM-XMC-II carrier cards. Please contact Alpha Data for carrier card compatibility.
2.3 Power Requirements
he power dissipation of the board is highly dependent on the arget FPGA application. A power estimator
spreadsheet is available on request from Alpha Data. his should be used in conjunction with Xilinx's power
estimation tools to determine the exact current requirements for each power rail.
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3 Installation
3.1 Software Installation
Please refer to the Software Development Kit (SDK) installation CD. he SDK contains drivers, examples for
host control and FPGA design and comprehensive help on application interfacing.
3.2 Hardware Installation
3.2.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
3.2.2 Installation in ADC-XMC-Breakout Carrier
Note:
Note: his operation should only be performed while the ADC-XMC-Breakout carrier is not powered.
he 7Z1 should be secured to the ADC-XMC-Breakout carrier using M2.5 screws in the four holes provided.
Refer to the ADC-XMC-Breakout carrier documentation for switch configurations.
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4 unctional Description
4.1 Overview
Xilinx Zynq SoC
XC7Z045
XC7Z100
Processing System (PS)
DDR3 SDRAM
(256MB) XRM I/F
(Front IO)
GPIO
(x146)
SSIO
(x8)
microSD
Flash(Socket)
QSPI Flash
(2 x 256Mb)
Programmable Logic (PL)
Sw
microUSB
(8:11) (15:12)
Platform
Manager
COM0
IPMI
EPROM
V & T
Sensors
Ref
Clocks
Power
Supplies
(7:0)
GTX Transceivers
VPWR
(5V or 12V)
I2C
3.3V
PCIE
RefClk
PCIE/ SSIO (7:0)
P5
P6
P6 RefClk
P4
P Y
P Y
P YMAGS
MAGS
ET 1
ET 0
USB1
COM1 (RS-232)
COM2 (RS-232/485)
USB2
P Y
DDR3 SDRAM
(512MB)
DDR3 SDRAM
(256MB)
P Y
USB0
USB3
GPIO (x38)
SSIO (15:8)
igure 1 : ADM-XRC-7Z1 Block Diagram
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4.1.1 Switch Definitions
here are two sets of 8-way DIP switches for configuring the board.
Switch 1 Ref. Function OFF State ON State
SW1-1 Reserved - -
SW1-2 Flash Boot
Inhibit Allow PS to boot PL from flash Prohibit PS booting PL from flash
SW1-3 System Monitor
Upgrade Normal Operation Reserved for factory use
SW1-4 Reserved - -
SW1-5 XMC J AG Isolate J AG chain from P5 Connect J AG chain to P5
SW1-6 MG (3:0) Mux
Sel MG (3:0) routed to P6 MG (3:0) routed to XRM
SW1-7 MG (7:4) Mux
Sel MG (7:4) routed to P6 MG (7:4) routed to XRM
SW1-8 Reserved - -
Table 4 : Switch 1 Definitions
Switch 1 Ref. Function OFF State ON State
SW2-1 BootSel 0 See able 15
SW2-2 BootSel 1 See able 15
SW2-3 Independent
J AG Single (cascaded) J AG chain at J4 Independent J AG chains
SW2-4 PLL Bypass PS PLL is used PS PLL is bypassed
SW2-5 InhExtRst Do not mask MRS I# Mask MRS I# when ROO # is
asserted
SW2-6 Reserved - -
SW2-7 USB3 Mode Zynq PS is USB Host and USB3 is
downstream port USB3 is O G port
SW2-8 System Reset Normal operation PS System Reset
Table 5 : Switch 2 Definitions
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4.1.2 LED Definitions
here are seven LEDs to provide a visual indication of the board status.
heir locations are shown in Figure 2
DONE
D10
D8
D11
MVMRO
PWRFLT
FBS
D9
D12 SWRST
SYS 0
D6 D5
SYS 1
D17 D19 D20 D21 D22 D23
ETH1 ETH0
igure 2 : LED Locations
Comp. Ref. Function ON State Off State
D5 (Green) System Monitor
Status See able 23
D6 (Red) System Monitor
Status See able 23
D8 (Green) FPGA (PL)
Done PL is configured PL is not configured
D9 (Green) Flash Boot
Enable Enable PS booting PL from flash Disable PS booting PL from flash
D10 (Amber) MVMRO Enable writes to non-volatile memories Inhibit writes to non-volatile memories
D11 (Red) Power Fault Power Supply Fault Power Supplies off or within range
D12 (Green) System Reset PS is in Reset PS is not in Reset
Table 6 : Main LED Definitions
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A further two sets of three LEDs provide an indication of the status of the two Ethernet interfaces
Comp. Ref. Function ON State Off State
D23 (Green) Ethernet 0
LED0 See able 16
D22 (Green) Ethernet 0
LED1 See able 16
D21 (Amber) Ethernet 0
LED2 See able 16
D20 (Green) Ethernet 1
LED0 See able 16
D19 (Green) Ethernet 1
LED1 See able 16
D17 (Amber) Ethernet 1
LED2 See able 16
Table 7 : Ethernet LED Definitions
4.2 Primary XMC Connector P5
Full pinout information for this connector is listed in able 24
4.2.1 XMC Platform Interface
4.2.1.1 IPMI I2C
A 2 Kbit I2C EEPROM (type M24C02) is connected to the XMC IPMI. his memory contains board information
(type, voltage requirements etc.) as defined in the XMC based specification.
4.2.1.2 MBIST#
Built-In Self est. his output signal is not used and is driven inactive (high) by the CPLD when the board is
powered.
4.2.1.3 MVMRO
XMC Write Prohibit. his signal is an input from the carrier. When asserted (high), all writes to non-volatile
memories are inhibited. Amber LED D10 indicates a warning when this signal is not set and writes to
non-volatile memory are enabled. he signal has a 100k pull-up resistor to assert it by default.
his signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the Zynq
PS at MIO50 (pin A19).
4.2.1.4 MRSTI#
XMC Reset In. his signal is an active low input from the carrier and should be used to reset any PCIE endpoint.
It is translated to 1.5V levels and connected to the Zynq PL at pin K2.
MRS I# can also be used to fully reset the board by asserting the Zynq PS_POR_B input. his may not be
desirable and can be inhibited by turning switch SW2-5 ON.
4.2.1.5 MRSTO#
XMC Reset Out. his optional output signal is connected to the Zynq PL at pin J4. It should only be driven when
the board is connected to a master or Root Complex carrier slot.
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4.2.1.6 MPRESENT#
Module Present. his output signal is connected directly to 0V.
4.2.1.7 JTAG
See Section Section 4.5
4.2.2 P5 HSSIO Links
Eight pairs of HSSIO links from the Zynq PL are routed to XMC connector P6.
he pinout and coupling of these links are compatible with PCI Express.
he ransmit ( x) side of all eight lanes are AC coupled by 100nF capacitors, placed at the output from the PL.
he Receive (Rx) side of all eight lanes are directly connected from the connector to the PL.
Alternative coupling options are available as a special ordering option. Please contact Alpha Data for details.
4.3 Secondary XMC Connector P6
Full pinout information for this connector is listed in able 25
4.3.1 P6 HSSIO Links
Eight pairs of HSSIO links from the Zynq PL can be routed to XMC connector P6.
HSSIO Lanes (3:0) are routed to either P6(3:0) or XRM(3:0) using DIP switch SW1-6. (See able 4)
HSSIO Lanes (7:4) are routed to either P6(7:4) or XRM(7:4) using DIP switch SW1-7. (See able 4)
he x side of all eight lanes are directly connected from the PL to the connector.
he Rx side of all eight lanes are AC coupled by 100nF capacitors, placed at the input to the PL.
Alternative coupling options are available as a special ordering option. Please contact Alpha Data for details.
4.3.2 P6 GPIO Signals
here are 38 GPIO signals connected between P6 and the Zynq PL high-range bank 10.
he signals are routed differentially and can therefore can be used as 38 single-ended signals or as 19
differential pairs.
he signals are connected through level-clamping quick-switches to give 3.3V compatibility at the XMC interface.
Input signals are clamped at 2.5V by the quick-switches, while 2.5V outputs from the PL are passed straight
through.
he quick-switches have a very low ON resistance and are suitable for high-speed LVDS interfacing in either
direction.
4.4 PrPMC Connector P4
PrPMC connector P4 has two sets of Ethernet, Serial COM port and USB interfaces.
Details of the Ethernet interfaces are given in Section 4.8.3
Details of the Serial COM Ports are given in Section 4.8.4
Details of the USB Ports are given in Section 4.8.5
Full pinout information for this connector is listed in able 26
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4.5 JTAG Interfaces
4.5.1 On-board Interface
By default, the 7Z1 is configured to have a single (cascaded) J AG scan chain connected to header J4. his
allows the connection of the Xilinx J AG cable for debug using the Xilinx ChipScope tools.
he board can also be set to have two independent scan chains using DIP switch SW2-3. (See able 5). In
independent mode, the main chain (with the Zynq PL, CPLD and XRM interface) is connected to J4, while the
Zynq PS is connected to header J3.
If the cascaded or main scan chain is connected to the XMC connector (when SW1-5 is ON), header J4 should
not be used.
4.5.2 XMC Interface
he J AG interface on the XMC connector is normally unused and XMC_ DI connected directly to XMC_ DO.
he interface can be connected to the cascaded or main interface (through level-translators) by switching SW1-5
ON. See able 4
4.5.3 JTAG Voltages
he on-board J AG scan chains uses 1.8V. he Vcc supply provided on J3 and J4 to the J AG cable is +1.8V
and is protected by a poly fuse rated at 350mA. 3.3V signals must not be used at header J3 or J4.
he J AG signals at the XMC interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
he J AG signals at the XRM2 interface use the adjustable voltage XRM_VIO.
4.6 Clocks
he board has nine reference clocks: two from the carrier, and seven generated on-board.
he clocks MG CLK250M, PROGCLK, REFCLK200M and E H_CLK25M are generated by a single Silicon
Labs Si5338B and are all synchronous.
Note:
Clock ermination
he LVDS clocks do not have termination resistors on the circuit board. On-die terminations in the FPGA must
be enabled by setting the attribute "DIFF_ ERM = RUE". his can either be set in the source code when
instantiating the buffer, or in the design constraints file.
4.6.1 PCIe Reference Clock (PCIERE CLK)
he 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector,
P5, at pins A19 and B19. his is connected to the Zynq PL via 10nF AC coupling capacitors. On the Zynq PL, it
is connected to G X Quad 112 to allow its use as reference for the eight G X lanes on Quads 111 and 112.
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Signal arget FPGA Input IO Standard "P" pin "N" pin
PCIEREFCLK MG REFCLK0_112 HSCL N8 N7
Table 8 : PCIERE CLK Connections
4.6.2 P6 Reference Clock (P6RE CLK)
A reference clock can be provided by the carrier card through the Secondary XMC connector, P6, at pins A19
and B19. his is connected to the Zynq PL via 10nF AC coupling capacitors. On the Zynq PL, it is connected to
G X Quad 109 to allow its use as reference for the eight G X lanes on Quads 109 and 110.
Signal arget FPGA Input IO Standard "P" pin "N" pin
P6REFCLK MG REFCLK0_109 LVDS or HSCL AD10 AD9
Table 9 : P6RE CLK Connections
4.6.3 MGTCLK250M
he fixed 250.0MHz reference clock, MG CLK250M, is a differential clock signal using LVDS. wo phase
matched copies are MG REFCLK inputs on the Zynq PL at G X Quad 109 and 111. Since each input can clock
the adjacent G X Quads, this clock can be used by all G X links on the board.
Signal arget FPGA Input IO Standard "P" pin "N" pin
MG CLK250M_A MG REFCLK0_111 LVDS_25 U8 U7
MG CLK250M_B MG REFCLK1_109 LVDS_25 AF10 AF9
Table 10 : MGTCLK250M Connections
4.6.4 PROGCLK
he programmable clock, PROGCLK, is a differential clock signal using LVDS. It is connected to MG REFCLK
inputs on the Zynq PL at G X Quad 110. Since this input can clock the adjacent G X Quads, it can be used by
the G X links on quads 109 and 111.
Signal arget FPGA Input IO Standard "P" pin "N" pin
PROGCLK MG REFCLK1_110 LVDS_25 AC8 AC7
Table 11 : PROGCLK Connections
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4.6.5 RE CLK200M
he fixed 200MHz reference clock, REFCLK200M, is a differential clock signal using LVDS. hree
phase-matched copies are distributed to Global Clock inputs on the Zynq PL.
his clock can be used to generate application-specific clock frequencies using the PLLs within the Zynq PL. It
is also suitable as the reference clock for the IO delay control block (IDELAYC RL) and memory interfaces.
Signal arget FPGA Input IO Standard "P" pin "N" pin
REFCLK200M_A IO_L13_MRCCC_10 LVDS_25 AG17 AG16
REFCLK200M_B IO_L12_MRCC_33 SS L15 G5 G4
REFCLK200M_C IO_L13_MRCC_33 SS L15 F5 E5
Table 12 : RE CLK200M Connections
4.6.6 PS_CLK33M3
he Zynq PS is provided with a 33.333MHz reference clock at the PS_CLK input on pin A22. his clock is
asynchronous to the clocks generated by the Si5338B.
Signal arget FPGA Input IO Standard "P" pin "N" pin
PS_CLK33M3 PS_CLK_500 LVCMOS18 A22 -
Table 13 : PS_CLK33M3 Connections
4.6.7 USB_RE CLK24M
he USB PHY and hub are provided with an independent 24.0MHz reference clock. his clock is asynchronous
to the clocks generated by the Si5338B and is not connected to the Zynq SoC.
4.6.8 ETH_CLK25M
he Ethernet PHYs are provided with 25.0MHz reference clocks generated by the Si5338B. hese are not
connected to the Zynq SoC.
4.6.9 ETH1_CLK125M
he Ethernet PHY 1 generates a 125MHz reference clock that is connected to the Zynq PL at pin AF14.
Signal arget FPGA Input IO Standard "P" pin "N" pin
E H1_CLK125M IO_L12_MRCC_10 LVCMOS25 AF14 -
Table 14 : ETH1_CLK125M Connections
4.7 Resets
he Zynq PS can be reset using the System Reset switch, SW2-8.
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V2.6 - 14th ebruary 2022
4.8 Zynq PS Block
4.8.1 Boot Modes
BootSel1
(SW2-2) BootSel0 (SW2-1) Boot Mode
OFF OFF J AG
OFF ON Quad SPI
ON OFF SD Flash
ON ON Reserved
Table 15 : Boot Mode Selection
4.8.2 PS Memory Interfaces
4.8.2.1 Quad SPI lash Memory
512Mb of QSPI flash memory (Micron N25Q256A11E1240E/M 41K128M16J ) is attached to the PS, and is
used to store Zynq boot images, FPGA bitstreams and data.
4.8.2.2 MicroSD lash Memory
An on-board microSD card holder is available to store Zynq boot images, FPGA bitstreams and data.
4.8.2.3 PS DDR3 Memory
he PS has one bank of DDR3 memory, consisting of 2 16-bit wide memory devices in parallel to provide a
32-bit data-path capable of running up to 533MHz (DDR-1066). 2Gb devices (Micron M 41K128M16J -125) are
fitted as standard to provide 512MB per bank.
4.8.3 Ethernet Interfaces
he 7Z1 has two 1000BASE- Ethernet Interfaces at rear connector P4. Interface E H0 is connected to the
Zynq PS, while E H1 is connected to the PL
Both interfaces have a Marvell 88E1512 PHY, connected to the Zynq via RGMII.
PL
P4
PHY
MDI RGMII
PS
PHYMagnetics
MDI RGMII
ETH0
ETH1 Magnetics
igure 3 : Ethernet Interfaces
Each interface has three status LEDs. he functions of these are shown in able 16 below.
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ADM-XRC-7Z1 User Manual
V2.6 - 14th ebruary 2022
LED Colour Function
0 Green .
1 Green .
2 Amber .
Table 16 : Ethernet Status LEDs
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