Alpha Data ADM-XRC-7V1 User manual

ADM-XRC-7V1
User Manual
Document Revision: 1.9
23rd Au 2016

ADM-XRC-7V1 User Manual
V1.9 - 23rd Au 2016
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ADM-XRC-7V1 User Manual
V1.9 - 23rd Au 2016
able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 References & Specifications .......................................................................................................... 1
2 Installation ........................................................................................................................................ 2
2.1 Software Installation ...................................................................................................................... 2
2.2 Hardware Installation ..................................................................................................................... 2
2.2.1 Handling Instructions ................................................................................................................. 2
2.2.2 Motherboard / Carrier Requirements ......................................................................................... 2
2.2.2.1 Installation in ADC-EMC-II Carrier ........................................................................................ 2
2.2.3 Cooling Requirements ............................................................................................................... 2
3 Functional Description .................................................................................................................... 4
3.1 Overview ........................................................................................................................................ 4
3.1.1 Switch Definitions ...................................................................................................................... 5
3.1.2 LED Definitions ..........................................................................................................................
3.2 XMC Platform Interface ................................................................................................................. 7
3.2.1 IPMI I2C ..................................................................................................................................... 7
3.2.2 MBIST# ...................................................................................................................................... 7
3.2.3 MVMRO ..................................................................................................................................... 7
3.2.4 MRSTI# ...................................................................................................................................... 7
3.2.5 MRSTO# .................................................................................................................................... 7
3.2. MPRESENT# ............................................................................................................................. 7
3.3 JTAG Interface ............................................................................................................................... 8
3.3.1 On-board Interface ..................................................................................................................... 8
3.3.2 XMC Interface ............................................................................................................................ 8
3.3.3 JTAG Voltages ........................................................................................................................... 8
3.4 Clocks ............................................................................................................................................ 9
3.4.1 200MHz Reference Clock (REFCLK200M) ............................................................................. 10
3.4.2 PCIe Reference Clock 0 (PCIEREFCLK0) .............................................................................. 10
3.4.3 PCIe Reference Clock 1 (PCIEREFCLK1) .............................................................................. 10
3.4.4 Programmable Clocks (LCLK, PROGCLK 0-3) ........................................................................ 11
3.4.5 Module-Carrier Global Clock (GCLK_M2C) ............................................................................. 11
3.4. Module-Carrier MGT Clock (MGTCLK_M2C) .......................................................................... 11
3.4.7 XRM LVDS Clock (XRM_LVDS_CLK) ..................................................................................... 11
3.5 Flash Memory .............................................................................................................................. 13
3. Configuration ............................................................................................................................... 14
3. .1 Power-Up Sequence ................................................................................................................ 14
3. .2 Bridge-Less Mode .................................................................................................................... 14
3.7 Health Monitoring ......................................................................................................................... 15
3.7.1 Automatic Temperature Monitoring .......................................................................................... 1
3.7.2 Microcontroller Status LEDs .................................................................................................... 1
3.8 Local Bus ..................................................................................................................................... 17
3.9 Target FPGA ................................................................................................................................ 17
3.9.1 I/O Bank Voltages .................................................................................................................... 17
3.9.2 Target MGT Links .................................................................................................................... 17
3.10 Memory Interfaces ....................................................................................................................... 19
3.11 XRM Interface and Front-Panel I/O ............................................................................................. 20
3.11.1 XRM Connector, CN1 .............................................................................................................. 20
3.11.2 XRM Connector CN2 ............................................................................................................... 20
3.11.3 XRM I/F - GPIO ....................................................................................................................... 20
3.11.4 XRM I/F - High-speed Serial Links .......................................................................................... 21
3.11.5 XRM IO Voltage Override ........................................................................................................ 21

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Appendix A Rear Connector Pinouts ............................................................................................................... 23
A.1 Primary XMC Connector, P5 ........................................................................................................ 23
A.2 Secondary XMC Connector, P ................................................................................................... 24
A.2.1 Pn GPIO Pin Map .................................................................................................................. 25
A.3 PMC Connector P4 ...................................................................................................................... 27
A.4 Rear MGT Connections to the Target FPGA ............................................................................... 28
Appendix B Front (XRM) Connector Pinouts ................................................................................................... 30
B.1 XRM Connector CN1, Field 1 ...................................................................................................... 31
B.2 XRM Connector CN1, Field 2 ...................................................................................................... 32
B.3 XRM Connector CN1, Field 3 ...................................................................................................... 33
B.4 XRM Connector CN2 ................................................................................................................... 34
List of ables
able 1 References ........................................................................................................................................ 1
able 2 Switch Definitions .............................................................................................................................. 5
able 3 LED Definitions .................................................................................................................................. 6
able 4 REFCLK200M Connections ............................................................................................................. 10
able 5 PCIEREFCLK Connections ............................................................................................................. 10
able 6 PROGCLK Connections .................................................................................................................. 11
able 7 GCLK_M2C Connections ................................................................................................................. 11
able 8 MG CLK_M2C Connections ........................................................................................................... 11
able 9 XRM_LVDS_CLK Connections ........................................................................................................ 12
able 10 Voltage and emperature Monitors .................................................................................................. 15
able 11 emperature Limits .......................................................................................................................... 16
able 12 Status LED Definitions ..................................................................................................................... 16
able 13 arget FPGA IO Banks .................................................................................................................... 17
able 14 arget MG Links ............................................................................................................................ 17
able 15 Maximum Memory Speeds .............................................................................................................. 19
able 16 XRM GPIO Groups .......................................................................................................................... 20
able 17 Pn5 Interface ................................................................................................................................... 23
able 18 Pn6 Interface ................................................................................................................................... 24
able 19 Pn6 GPIO Pin Map .......................................................................................................................... 25
able 20 Pn4 Interface ................................................................................................................................... 27
able 21 arget RearMG Mapping ............................................................................................................... 28
able 22 XRM Connector CN1, Field 1 .......................................................................................................... 31
able 23 XRM Connector CN1, Field 2 .......................................................................................................... 32
able 24 XRM Connector CN1, Field 3 .......................................................................................................... 33
able 25 XRM Connector CN2 ....................................................................................................................... 34
List of Figures
Figure 1 ADM-XRC-7V1 Block Diagram .......................................................................................................... 4
Figure 2 LED Locations ................................................................................................................................... 6
Figure 3 J AG Header J1 ................................................................................................................................ 8
Figure 4 J AG Boundary Scan Chain .............................................................................................................. 8
Figure 5 Clocks ................................................................................................................................................ 9
Figure 6 Flash Memory Map .......................................................................................................................... 13
Figure 7 MG Links ....................................................................................................................................... 18
Figure 8 DRAM Banks ................................................................................................................................... 19

ADM-XRC-7V1 User Manual
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1 Introduction
he ADM-XRC-7V1 is a high-performance XMC for applications using Virtex-7 and Virtex-6 FPGAs from Xilinx.
his card supports all Virtex-7 devices available in the FF(G), FH(G), and FL(G), 1761 package.
he ADM-XRC-7V1 includes separate FPGA with a PCIe bridge developed by Alpha Data. Using a separate
device allows high performance operation without the need to integrate proprietary cores in the user (target)
FPGA.
With the release of 7series FPGA boards, Alpha Data has introduced a new build option to allow the mezzanine
card to be assembled without the bridge to reduce power and cost.
he ADM-XRC-7V1 is available in air-cooled and conduction-cooled configurations. View the ADM-XRC-7V1
Ordering Info tab at ADM-XRC-7V1 Product Page on www.alpha-data.com .
1.1 Key Features
Key Features
• Single-width XMC, compliant to VI A Standard 42.0 and 42.3
• Dedicated 4-lane PCI-Express Gen 2 interface with high-performance DMA controllers
• 4 additional PCI-Express compliant G X links between user FPGA and P5
• Support for Virtex-7 FPGA in FF(G), FH(G), and FLG(G)1761 package
• 4 independent banks of DDR3-1600 SDRAM, 256MB/bank, 1GB total (2GB and 4GB option)
• Front-panel (XRM) interface with adjustable voltage, 146 GPIO signals and 8 G X links to user FPGA
• Rear-panel (XMC) 10 G X links & 38 GPIO signals between user FPGA and P6
• Rear-panel (PMC) interface with 64 GPIO single ended or differential signals between user FPGA and P4
(optional)
• Rear-Panel I/O (Pn6 and Pn4) compatible with 3U and 6U VPX carriers featuring various VI A 46.9 PMC/
XMC to VPX signal mapping configurations
• On-board programmable clocks enabling multiple protocols to be implemented on the user FPGA's
high-speed links
• Voltage and temperature monitoring
• Air-cooled and conduction-cooled configurations
1.2 References & Specifications
ANSI/VI A 42.0 XMC Standard, December 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 42.3 XMC PCI Express Protocol Layer Standard, June 2006, VI A, ISBN 1-885731-43-4
ANSI/VI A 46.9 PMC/MXC Rear I/O Fabric Signal Mapping on 3U and U VPX Modules Standard,
November 2010, VI A, ISBN 1-885731-63-9
ANSI/IEEE 1386-2001 IEEE Standard for a Common Mezzanine Card (CMC) Family, October 2001, IEEE,
ISBN 0-7381-2829-5
ANSI/IEEE 1386.1-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC),
October 2001, IEEE, ISBN 0-7381-2831-7
ANSI/VI A 20-2001
(R2005) Conduction Cooled PMC, February 2005, VI A, ISBN 1-885731-26-4
Table 1 : References
Pa e 1Introduction
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2 Installation
2.1 Software Installation
Please refer to the Software Development Kit (SDK) installation CD. he SDK contains drivers, examples for
host control and FPGA design and comprehensive help on application interfacing.
2.2 Hardware Installation
2.2.1 Handlin Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
2.2.2 Motherboard / Carrier Requirements
he ADM-XRC-7V1 is a single width XMC.3 mezzanine with optional P6 and P4 connectors. he motherboard/
carrier must comply with the XMC.3 (VI A 42.3) specification for the Primary XMC connector, J5.
he Secondary XMC connector, P6 has a pinout compatible with various XMC to VPX signal maps as defined by
VI A 46.9. Please consult the pinouts in this user-guide as-well as those of the carrier manufacturer prior to
installation. Assistance can be provided by Alpa Data.
IMPORTANT
Connector P6 on the card is not compatible with the VI A 42.10 (XMC GPIO) Standard. In particular, USB
VCC must not be applied on this connector.
he ADM-XRC-7V1 is compatible with either 5V or 12V on the "VPWR" power rail.
2.2.2.1 Installation in ADC-EMC-II Carrier
he Alpha Data ADC-EMC-II carrier accepts both PMC and XMC mezzanine cards. By default, the carrier is
configured for PMCs and connects all the serial links from the XMC connector J15 to J25.
o configure for XMC and enable the PCIe interfaces at J15 and J25, switches 1-3 and 1-4 must be ON (closed).
2.2.3 Coolin Requirements
he power dissipation of the board is highly dependent on the arget FPGA application. A power estimator
spreadsheet is available on request from Alpha Data. his should be used in conjunction with Xilinx power
estimation tools to determine the exact current requirements for each power rail.
he board is supplied with a passive air cooled or conduction cooled heatsink according to the order number
given at time of purchase. It is the users responsibility to ensure sufficient airflow for air cooled applications and
metalwork for conduction cooled applications.
For more details on heatsinks supplied with Alpha Data boards, please view AD-AN-0018 ADM-XRC Cooling
Pa e 2 Installation
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Solutions.
he board features system monitoring that measures the board and FPGA temperature. It also includes a
self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is
detected.
See Section 3.7 for further details.
Pa e 3Installation
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3 Functional Description
3.1 Overview
Target
XC7V585T
XC7V1500T
XC7V2000T
XC7VX330T
XC7VX485T
XC7VX690T
(FFG/FLG/FHG 1761)
DDR3
Ban 1
P5
P4
XRM2
180-Way
XRM2
28-Way
System
Monitor
Bridge
XC6VLX130T
(FF484)
Mux
x4
x4
x4
Not in X330T and X485T
39
34
117 118
115119 116
114
113
12 (HR) 31 32 111 112
P6
x4
x8
SPI
FLASH
FLASH
64 GPIO
0
GPIO Level
Converter
Mux
Unused FPGA Ban s
HR ban s in X330T and 585T
DDR3
Ban 2
37
38
15
14
35
19
18 13
(HR)
16
33
DDR3
Ban 3
17
36
x4
x2
Quic Switch
DDR3
Ban 3
Power
Conversion
IPMI
EEPROM
Configuration
Switches
Programmable
Cloc ing JTAG
Fi ure 1 : ADM-XRC-7V1 Block Dia ram
Pa e 4 Functional Description
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3.1.1 Switch Definitions
here is a set of eight DIP switches placed on the rear of the board. heir functions are described in Switch
Definitions.
Note:
All switches are OFF by default. Factory Configuration switch must be in the OFF position for normal
operation.
Switch Ref. Function ON State Off State
SW1-1 User Switch to
arget FPGA 0 1
SW1-2 Reserved - Normal Operation
SW1-3 Bridge Bypass Bridge FPGA is bypassed - PCIe lanes (3:0) are connected directly to the user
FPGA.
Bridge FPGA is used. PCIe lanes (3:0)
are connected to the bridge.
SW1-4 Flash Boot
Inhibit arget FPGA is not configured from onboard flash memory. arget FPGA is configured from on- board flash memory.
SW1-5 XMC J AG Connect J AG chain to P5 Isolate J AG chain from P5
SW1-6 E-Fuse Enable E-Fuse programming voltage
(VccEFuse = 2.5V) Disable E-Fuse programming voltage (VccEFuse = 0V)
SW1-7 Factory
Configuration - Normal Operation
SW1-8 Bridge-Less
Mode Bridge-Less Mode Active - User bitstream loaded from SPI flash PCIe Bridge Mode Active - User bitstream loaded from Bridge
Table 2 : Switch Definitions
Pa e 5Functional Description
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3.1.2 LED Definitions
he position and description of the board status LEDs are shown in LED Locations:
D7 Status 1
D8 Status 2
D9 Target Done
D10 Bridge Done
D11 Bridge-Bypass
D12 Bridge-Less
D13 NVMR D14 XMC JTAG
Fi ure 2 : LED Locations
Comp. Ref. Function ON State Off State
D7(Red) Status 1 See Status LED Definitions
D8(Green) Status 2 See Status LED Definitions
D9(Green) arget Done arget FPGA is configured arget FPGA is unconfigured
D10(Green) Bridge Done Bridge FPGA is configured Bridge FPGA is unconfigured
D11(Amber) Bridge Bypass Bridge FPGA is bypassed - PCIe lanes (3:0) are connected directly to the user
FPGA
Bridge FPGA is used. PCIe lanes (3:0)
are connected to the bridge.
D12(Amber) Bridge-Less arget is configured through Auxiliary
SPI memmory arget is configured by Bridge
D13(Amber) NVMRO Inhibit writes to non-volatile memories Enable writes to non-volatile memories
D14(Amber) XMC J AG On-board J AG chain connected to P5 On-board J AG chain is isolated from
P5
Table 3 : LED Definitions
Pa e 6 Functional Description
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3.2 XMC Platform Interface
3.2.1 IPMI I2C
A 4 Kbit I2C EEPROM (type M24C04) is connected to the XMC IPMI. his memory contains board information
(type, voltage requirements etc.) as defined in the XMC based specification.
3.2.2 MBIST#
Built-In Self est. his output signal is driven active (low) until the FPGA with PCIe interface is configured. In
normal operation, this is the bridge FPGA. In Bridge Bypass mode or Bridge-Less Mode, it is the target FPGA.
3.2.3 MVMRO
XMC Write Prohibit. his signal is an input from the carrier. When asserted (high), all writes to non-volatile
memories are inhibited. his is indicated by the Amber LED, D13.
his signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the target
FPGA at pin AG32.
3.2.4 MRSTI#
XMC Reset In. his signal is an active low input from the carrier. When asserted, the bridge FPGA will be reset.
he MRS I# signal is translated to 1.8V levels and connected to the target FPGA at pin AF30.
3.2.5 MRSTO#
XMC Reset Out. his optional output signal is unused and undriven.
3.2.6 MPRESENT#
Module Present. his output signal is connected directly to 0V.
Pa e 7Functional Description
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3.3 JTAG Interface
3.3.1 On-board Interface
A J AG boundary scan chain is connected to header J1. his allows the connection of the Xilinx J AG cable for
FPGA debug using the Xilinx ChipScope tools.
he J AG Header pinout is shown in J AG Header J1:
VCC
GND
TCK
TDO
TDI
TMS
Fi ure 3 : JTAG Header J1
he scan chain is shown in J AG Boundary Scan Chain:
Bridge FPGA
XC6VLX130T
FFG484
Control CPLD
XC2C64A
CP56
Target FPGA
XC7VxxxxT
FFG1759
XRM
I/F
PRESENT#
VREF (1.8V)
Level Shift
1.8V - XRM VIO
En#
XRM TDI
XRM TDO
HDR TDI
HDR TDO
Level Shift
3.3V – 1.8V
En#
XMC
Con
(Pn5
Header
J1
XMC TDI
XMC TDO
XMC JTAG EN# SW1E
Fi ure 4 : JTAG Boundary Scan Chain
If the boundary scan chain is connected to the interface at the XMC connector (SW1-5 is ON), Header J1 should
not be used.
3.3.2 XMC Interface
he J AG interface on the XMC connector is normally unused and XMC_ DI connected directly to XMC_ DO.
he interface can be connected to the on-board interface (through level-translators) by switching SW1-5 ON.
See Switch Definitions
3.3.3 JTAG Volta es
he on-board J AG scan chain uses 1.8V. he Vcc supply provided on J1 to the J AG cable is +1.8V and is
protected by a poly fuse rated at 350mA. 3.3V signals must not be used at header J2.
he J AG signals at the XMC interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
he J AG signals at the XRM interface use the adjustable voltage XRM_VIO.
Pa e 8 Functional Description
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3.4 Clocks
he ADM-XRC-7V1 provides a wide variety of clocking options. On top of a fixed 200MHz oscillator and clocks
routed from the rear and front panel connectors, the board has 4 user-programmable clocks. hese clocks can
be combined with the FPGA's internal PLLs to suit a wide variety of communication protocols.
A complete overview of the clock routing on the ADM-XRC-7V1 is given in Clocks. A description of each clock
follows.
7 Series
MGT/ Banks
MGT111
REFCLK0
REFCLK1
MGT112
REFCLK0
REFCLK1
MGT113
REFCLK0
REFCLK1
MGT114
REFCLK0
REFCLK1
MGT115
REFCLK0
REFCLK1
MGT116
REFCLK0
REFCLK1
MGT117
REFCLK0
REFCLK1
MGT118
REFCLK0
REFCLK1
XMC
P5
XMC
P6
PC e
REFCLK
Buffer
PC e
Bridge
200MHZ
Buffer
200MHZ
Source
XRM nterface
User
Programmable
Source
MGT119
REFCLK0
REFCLK1
Note: REFCLK can be shared with
MGT tiles to the North and South
within a super logic region (SLR in
1500T and 2000T only)
REFCLK
Buffer
250MHZ
Source
DDR3
Banks
19 35
37 39
Bank 14
Fi ure 5 : Clocks
Note:
Clock ermination
he LVDS clocks do not have termination resistors on the circuit board. On-die terminations in the FPGA must
be enabled by setting the attribute "DIFF_ ERM = RUE". his can either be set in the source code when
instantiating the buffer, or in the User Constraints File (UCF). See the Xilinx Virtex-7 Libraries Guide and
Constraints Guide for further details.
Pa e 9Functional Description
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3.4.1 200MHz Reference Clock (REFCLK200M)
he fixed 200MHz reference clock REFCLK200M is a differential clock signal using LVDS. his signal is widely
distributed throughout the board.
It is connected to a MRCC inputs on the arget FPGA on Bank 14.
REFCLK200M is also converted to HS L signaling and used as the input clock for the DRAM interface.
his clock can be used to generate application-specific clock frequencies using the PLLs within the Virtex-7
FPGA. It is also suitable as the reference clock for the IO delay control block (IDELAYC RL).
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
REFCLK200M 200 MHz IO_L12_ 2_MRCC_14 LVDS AK34 AL34
REFCLK200M_HS L 200 MHz IO_L12_ 1_MRCC_19 HS L_I L39 L40
REFCLK200M_HS L 200 MHz IO_L12_ 1_MRCC_35 HS L_I E34 E35
REFCLK200M_HS L 200 MHz IO_L12_ 1_MRCC_37 HS L_I D27 D28
REFCLK200M_HS L 200 MHz IO_L12_ 1_MRCC_39 HS L_I H15 H14
REFCLK200M 200 MHz MG REFCLK0_115 LVDS Y8 Y7
REFCLK200M 200 MHz MG REFCLK0_118 LVDS G10 G9
Table 4 : REFCLK200M Connections
3.4.2 PCIe Reference Clock 0 (PCIEREFCLK0)
he 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector,
P5 at pins A19 and B19. his clock is buffered into two PLE Express reference clocks that are forwarded to the
Bridge and User FPGA respectively.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
PCIEREFCLK 100 MHz MG REFCLK0_117 LVDS K8 K7
Table 5 : PCIEREFCLK Connections
3.4.3 PCIe Reference Clock 1 (PCIEREFCLK1)
he reference clock "PCIEREFCLK1" is a differential clock provided by a carrier card through the Secondary
XMC connector P6 at pins A19 and B19. he Default build configuration for this board connects this pair to the
MG signal inputs. Most needed reference clocks can be generated through the User Programmable clocking
options. If it is a requirement that this differential pair be utilized as a clock signal to an MG bank, a resistor fit
option is available. Please contact Alpha Data for detials.
Pa e 10 Functional Description
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3.4.4 Pro rammable Clocks (LCLK, PROGCLK 0-3)
here are two programable clock sources that are forwarded throughout the FPGA. hese clocks are
programmable through the Alpha Data ADM-XRC Gen 3 SDK. LCLK is generated in the Bridge FPGA by the the
Alpha Data ADB3 driver and offers a less accurate frequency resolution, but with a wider programmable
frequency range. PROGCLK[3:0] is generated by a dedicated programmable clock generator IC and offer
extremely high frequency resolutions (1ppm increments). PROGCLK[3:0] is generated by a single source and
buffered to all MG tiles.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
LCLK 5 - 700 MHz IO_L13_MRCC_14 LVDS AJ32 AK32
PROGCLK0 5 - 312.5 MHz MG REFCLK1_113 LVDS AK8 AK7
PROGCLK1 5 - 312.5 MHz MG REFCLK1_115 LVDS AB8 AB7
PROGCLK2 5 - 312.5 MHz MG REFCLK1_117 LVDS M8 M7
PROGCLK3 5 - 312.5 MHz MG REFCLK1_119 LVDS C10 C9
Table 6 : PROGCLK Connections
3.4.5 Module-Carrier Global Clock (GCLK_M2C)
he clock "GCLK_M2C" is a differential clock signal using LVDS. It is provided by an XRM module through the
XRM connector, CN1, at pins 110 & 108. It is connected to an MRCC input on the arget FPGA.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
GCLK_M2C Variable IO_L13_ 2_MRCC_17 LVDS AF39 AF40
Table 7 : GCLK_M2C Connections
3.4.6 Module-Carrier MGT Clock (MGTCLK_M2C)
he reference clock "MG CLK_M2C" is a differential clock signal using LVDS. he clock is provided by an XRM
module through the XRM connector, CN1, at pins 109 & 111. It is first buffered and fanned out, then connected
to G X Quads 113 and 114 on the arget FPGA for application specific frequencies / line rates.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
MG CLK_M2C Variable MG REFCLK0_113 LVDS AH8 AH7
MG CLK_M2C Variable MG REFCLK0_114 LVDS AD8 AD7
Table 8 : MGTCLK_M2C Connections
3.4.7 XRM LVDS Clock (XRM_LVDS_CLK)
he clock "XRM_LVDS_CLK" is a differential clock signal using LVDS levels. he clock is provided by the target
FPGA and connected to an XRM module through the XRM connector, CN1, at pins 113 & 115.
Pa e 11Functional Description
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Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
XRM_PECL_CLK Variable IO_L13_ 2_MRCC_15 LVDS AV40 AW40
Table 9 : XRM_LVDS_CLK Connections
Pa e 12 Functional Description
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3.5 Flash Memory
A 512Mb Flash Memory (Intel / Numonyx PC28F512P30EF) is used to store board Vital Product Data (VPD),
programmable clock parameters and configuration bitstreams for the Bridge and arget FPGAs.
he flash memory cannot be accessed by the target FPGA. Host access is only possible through the FLC L,
FLPAGE and FLDA A registers in the Bridge FPGA.
he region of memory between addresses 0x11000000 and 0x11FFFFF is allocated for custom data to be stored
by the ADM-XRC-7V1 user.
Utilities for erasing, programming and verification of the flash memory are provided in the ADMXRC SDK.
Write Protect
he Flash Write Protect (WP#) pin is connected to an inverted version of the NVMRO signal at the XMC
interface. When the NVMRO signal is active (High), all writes to the flash will be inhibited. his state will be
indicated by the Amber LED as shown in LED Locations.
0x0000_0000
0x007F_FFFF
Alternate Bridge FPGA Bitstream
Default Bridge FPGA Bitstream
0x0080_0000
0x00FF_FFFF
0x0100_0000
0x010F_FFFF
B0 Length(7:0) Boot Flag 0
Bitstream 0 Length(23:8)
reser ed
Default Target FPGA Bitstream
(Target Bitstream 0)
0x0122_0000
0x028F_FFFF
0x0120_0000
0x0120_0002
B1 Length(7:0) Boot Flag 1
Bitstream 1 Length(23:8)
reser ed
Alternate Target FPGA Bitstream
(Target Bitstream 1)
0x0292_0000
0x03FF_FFFF
0x0290_0000
0x0290_0002
0x0110_0000
0x011F_FFFF
Alpha Data Vital Product Data
(Alpha Data VPD)
User Vital Product Data
(User VPD)
Fi ure 6 : Flash Memory Map
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3.6 Confi uration
3.6.1 Power-Up Sequence
If valid data is stored in the flash memory, the bridge will automatically configure the arget FPGA at power-up.
his sequence can be inhibited by turning the Flash Boot Inhibit (FBI) switch, SW1-4 to ON. (See Switch
Definitions).
Note:
If an over-temperature alert is detected from the System Monitor, the target will be cleared by pulsing its
PROG signal. See Automatic emperature Monitoring.
3.6.2 Brid e-Less Mode
When operating in bridgeless mode, the arget FPGA will be configured directly by a Quad SPI connection to a
1Gb FLASH memory device. his memory device is re-programable over a Xilinx J AG cable.
his mode is not available in Revision 2 and earlier boards.
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ADM-XRC-7V1 User Manual
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3.7 Health Monitorin
he ADM-XRC-7V1 has the ability to monitor temperature and voltage to maintain a check on the operation of
the board. he monitoring is implemented using the A MEGA64 microcontroller.
Control algorithms within the microcontroller automatically check line voltages and on board temperaturs and
shares the information with blockram in the Bridge FPGA.
he following voltage rails and temperatures are monitored:
Monitor Purpose
1.0V FPGA Core Supply (VccIN )
1.0V arget ranceiver Power (AVCC)
1.0V Bridge ranceiver Power (AVCC)
1.2V arget ranceiver Power (AV )
1.2V Bridge ranceiver Power (AV )
1.5V DDR3 SDRAM, arget FPGA memory I/O
XRM_VIO (Front-Panel) I/O voltage
1.8V arget ranceiver Power (AVCC_AUX)
1.8V Flash Memory, FPGA IO Voltage (VCCO)
2.0V arget FPGA Auxiliary Supply AUX (VccAUX)
2.5V Level ranslation, Bridge FPGA Auxiliary Supply
(VccAUX)
3.3V Board Input Supply
5.0V Internally generated 5V supply
VPWR Board Input Supply (either 5.0V or 12.0V)
emp1 arget FPGA on-die temperature
emp2 Board temperature sensor on-die temperature
emp3 Bridge FPGA on-die temperature
Table 10 : Volta e and Temperature Monitors
An example application that reads the system monitor ("sysmon") is available within the SDK.
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ADM-XRC-7V1 User Manual
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3.7.1 Automatic Temperature Monitorin
he onboard system monitor microcontroller contains pre-programmed temperature limits. he temperature limits
are shown in able emperature Limits:
.arget FPGA Bridge FPGA Board
Min Max Min Max Min Max
Commercial 0 degC +85 degC 0 degC +85 degC 0 degC +85 degC
Extended 0 degC +100 degC 0 degC +100 degC 0 degC +100 degC
Industrial -40 degC +100 degC -40 degC +100 degC -40 degC +100 degC
Table 11 : Temperature Limits
Important:
If either FPGA temperature limit is exceeded, the arget FPGA is automatically cleared. his is indicated by the
Green LED ( arget Configured or DONE) switching off and the two status LEDs showing a temperature fault
indication. his condition is cleared with a power cycle.
he purpose of this mechanism is to protect the card from damage due to over-temperature. It is possible that it
will cause the user application and, possibly, the host computer to "hang" as a result of communication errors.
An overtemperature shutdown will not occur until the system monitor reads 5 degC above the maximum limit for
multiple samples in a row (i.e. +105 degC for Industrial boards). his is to compensate for potential errors in the
temperature readings. here is no protection mechanism in place for minimum temperatures or the "Board"
temperature sensor limits.
3.7.2 Microcontroller Status LEDs
LEDs D7 (Red) and D8 (Green) indicate the microcontroller status.
LEDs Status
Green Running and no alarms
Green + Red Standby (Powered off)
Flashing Green + Flashing Red
(together) Attention - critical alarm active
Flashing Green + Flashing Red
(alternating) Service Mode
Flashing Green + Red Attention - alarm active
Red Missing application firmware or
invalid firmware
Flashing Red FPGA configuration cleared to
protect board
Table 12 : Status LED Definitions
Pa e 16 Functional Description
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