AMD SP5100 Product guide

Technical Reference Manual
Rev. 1.70
P/N: 44409_sp5100_ds_pub
© 2010 Advanced Micro Devices, Inc.
AMD SP5100
Databook

42133
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Revision History
Date
Revision
Description
Oct 2010
1.70
First release of the public version. Changes from the latest released NDA
version include:
•Updated Table 11-3, “DC Characteristics for Interface on the SP5100”:
Corrected VIL minimum value to -0.5V for CPU signals, RSMRST#, and
SBPWRGD; filled in ILI values for NB-ALLOW_LDTSTP, RSMRST#, and
SBPWRGD
; corrected condition for GPIO/IMC_GPIO and IDE pins’ VOH
to IOH=-8.0mA.
•Updated Table 14-5, “List of Pins on the SP5100 XOR Chain and the
Order of Connection”: Corrected pin names at XOR# 113 and 114 to
USB_FSD13P and USB_FSD12P.
•Updated Section 7.12, “Northbridge / Power Management Interface”:
Revised description for WAKE#/GEVENT8#.
•Updated Section 7.13, “SMBus Interface/General Purpose Open
Controller”: Removed references to ASF, as the feature is no longer
supported; SCL1/ SDA1 interface is now used as secondary SMBUS in
the S5 power domain.

AMD SP5100 Databook 44409 Rev. 1.70 October 10
4
Table of Contents
Table of Contents
1Introduction .............................................................................................................8
1.1 Features of the SP5100.............................................................................................................8
1.2 Part Number and Branding......................................................................................................11
2SP5100 Block Diagram .........................................................................................13
3SP5100 Power on Sequence and Timing.............................................................14
3.1 Power Up and Down Sequences .............................................................................................14
4SP5100 Strap Information.....................................................................................20
5Integrated Resistor and External Pull-up/Pull-down Resistor Requirements..24
6SP5100 Ballout Map ..............................................................................................31
7Signal Description.................................................................................................33
7.1 CPU Interface..........................................................................................................................33
7.2 LPC Interface ..........................................................................................................................33
7.3 A-Link Express II Interface.......................................................................................................34
7.4 PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge) .......................................................34
7.5 USB Interface..........................................................................................................................35
7.6 PATA 66/100/133....................................................................................................................35
7.7 Serial ATA Interface.................................................................................................................36
7.8 HD Audio Interface..................................................................................................................37
7.9 Real Time Clock Interface........................................................................................................37
7.10 Hardware Monitor....................................................................................................................37
7.11 SPI ROM Interface ..................................................................................................................38
7.12 Northbridge / Power Management Interface.............................................................................38
7.13 SMBus Interface / General Purpose Open Collector.................................................................40
7.14 External Event / General Event / General Power Management / General Purpose Open Collector
41
7.15 General Purpose I/O................................................................................................................43
7.16 Integrated Micro-Controller (IMC).............................................................................................46
7.17 Reset / Clocks / ATE................................................................................................................47
7.18 Intruder Alert............................................................................................................................49
7.19 Power and Ground ..................................................................................................................49
8Functional Description .........................................................................................51
8.1 EHCI USB 2.0 and OHCI USB 1.1 Controllers .........................................................................51
8.1.1 USB Power Management...............................................................................................................52
8.2 SMI#/SCI Generation...............................................................................................................53
8.3 LPC ISA Bridge .......................................................................................................................54
8.3.1 LPC Interface Overview..................................................................................................................54
8.3.2 LPC Module Block Diagram............................................................................................................56
8.4 Integrated Micro-Controller (IMC).............................................................................................56
8.5 Real Time Clock......................................................................................................................56
8.5.1 Functional Blocks of RTC...............................................................................................................57

44409 Rev. 1.70 October 10 AMD SP5100 Databook
Table of Contents
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8.6 PATA Controller.......................................................................................................................57
8.7 SATA (Serial ATA) Controller...................................................................................................57
8.8 PCI Bridge...............................................................................................................................58
8.9 High Definition Audio...............................................................................................................59
8.9.1 HD Audio Codec Connections........................................................................................................59
8.10 Power management/ACPI .......................................................................................................59
8.11 General Events and GPIOs......................................................................................................59
8.12 Hardware Monitor Interface......................................................................................................60
9System Clock Specifications................................................................................62
9.1 System Clock Descriptions and Frequency Specifications........................................................62
9.2 System Clock AC Specifications..............................................................................................62
10 States of Power Rails during ACPI S1 to S5 States ...........................................66
11 Electrical Characteristics......................................................................................67
11.1 Absolute Maximum Ratings .....................................................................................................67
11.2 Functional Operating Range for Signal Input............................................................................67
11.3 DC Characteristics...................................................................................................................68
11.4 Reset Signal Requirements .....................................................................................................73
11.5 RTC Battery Current Consumption...........................................................................................73
12 Package Information.............................................................................................74
12.1 Physical Dimensions................................................................................................................74
12.2 Pressure Specification.............................................................................................................75
13 Thermal Information..............................................................................................76
14 Testability...............................................................................................................77
14.1 Test Control Signals ................................................................................................................77
14.2 XOR Chain Test Mode.............................................................................................................78
14.2.1 Brief Description of an XOR Chain..................................................................................................78
14.2.2 Description of the SP5100 XOR Chain............................................................................................79
Appendix A: Pin Listing..............................................................................................84

AMD SP5100 Databook 44409 Rev. 1.70 October 10
6
List of Figures
List of Figures
Figure 1-1: SP5100 Rev A14 Branding Diagram ....................................................................................................11
Figure 1-2: SP5100 Rev A15 Branding Diagrams...................................................................................................12
Figure 2-1: SP5100 Block Diagram Showing the Internal PCI Devices and Major Function Blocks...........................13
Figure 3-1: SP5100 Power Up/Down Sequence.....................................................................................................15
Figure 3-2: SP5100 S3/S0 Power Up/Down Sequence...........................................................................................16
Figure 3-3: Circuit for Maintaining Proper Relationship between +V5_VREF and VDDQ..........................................17
Figure 3-4: Timing for SB PWR_GOOD De-asserted to RSMRST# De-asserted.....................................................18
Figure 3-5: Timing for LDT_STP# assertion on first power up (G3 S5)................................................................18
Figure 3-6: S5_3.3V Power Down Sequence Requirement.....................................................................................19
Figure 4-1: Straps Capture....................................................................................................................................20
Figure 4-2: Type II Straps Capture timing...............................................................................................................20
Figure 4-3: Type I Straps Capture timing ...............................................................................................................21
Figure 6-1: SP5100 Ball-out Assignment (Left).......................................................................................................31
Figure 6-2: SP5100 Ball-out Assignment (Right) ....................................................................................................32
Figure 8-1: SP5100 USB 2.0 System Block Diagram..............................................................................................51
Figure 8-2: A Typical LPC Bus System..................................................................................................................54
Figure 8-3: Block Diagram of LPC Module.............................................................................................................56
Figure 8-4: Block Diagram of Internal RTC.............................................................................................................57
Figure 8-5: Block Diagram for the SATA Module....................................................................................................58
Figure 8-6: HD Audio Codec Connections..............................................................................................................59
Figure 9-1: Timing Labels for AC Specifications of the SP5100 Clocks...................................................................63
Figure 9-2: Timing Labels for AC Specifications of the SP5100 Diff Clocks.............................................................63
Figure 9-3: SP5100 Diff Clocks Rise and Fall Time Measurement ..........................................................................63
Figure 12-1: SP5100 21 mm x 21 mm 0.8 mm Pitch 528-FCBGA Package Outline.................................................74
Figure 14-1: Test Mode Capturing Sequence Timing..............................................................................................78
Figure 14-2: A Generic XOR Chain........................................................................................................................78
Figure 14-3: On-chip XOR Chain connectivity........................................................................................................79

44409 Rev. 1.70 October 10 AMD SP5100 Databook
List of Tables
7
List of Tables
Table 1-1: SP5100 Part Numbers..........................................................................................................................12
Table 3-1: SP5100 Power Up/Down Sequence Timing...........................................................................................14
Table 4-1: Standard Straps ...................................................................................................................................21
Table 4-2: Debug Straps.......................................................................................................................................22
Table 4-3: Additional Straps..................................................................................................................................23
Table 5-1: External Resistor Requirements and Integrated Pull-Up/Down...............................................................24
Table 8-1: EHCI Support for Power Management States........................................................................................52
Table 8-2: EHCI Power State Summary.................................................................................................................52
Table 8-3: Causes of SMI# and SCI ......................................................................................................................53
Table 8-4: LPC Cycle List and Data Direction ........................................................................................................55
Table 8-5: SMI, SCI, andWake Event Support by GPIO and General Event Pins....................................................60
Table 8-6: Functionality of the General Events and GPIOs across ACPI States.......................................................60
Table 9-1: SP5100 System Clock Descriptions ......................................................................................................62
Table 9-2: SP5100 System Clock Input Frequency Specifications...........................................................................62
Table 9-3: SP5100 System Clock Output Frequency Specifications........................................................................62
Table 9-4: 48MHz USB Clock AC Specifications....................................................................................................63
Table 9-5: RTC X1 Clock AC Specifications...........................................................................................................64
Table 9-6: LPC Clock AC Specifications................................................................................................................64
Table 9-7: PCI Clock AC Specifications.................................................................................................................64
Table 9-8: PCI Express®Clock AC Specifications..................................................................................................65
Table 9-9: RTC 32-KHz Output Clock AC Specifications ........................................................................................65
Table 10-1: State of Each Power Rail during ACPI S1 to S5 States........................................................................66
Table 11-1: Absolute Maximum Rating..................................................................................................................67
Table 11-2: DC Characteristics for Power Supplies to the SP5100..........................................................................68
Table 11-3: DC Characteristics for Interfaces on the SP5100.................................................................................68
Table 11-4: GPIO/GEVENT Input DC Characteristics.............................................................................................69
Table 11-5: GPIO/GEVENT Output DC Characteristics..........................................................................................72
Table 11-6: RTC Clock Output DC Characteristics.................................................................................................72
Table 11-7: Reset Signal Requirements.................................................................................................................73
Table 11-8: RTC Battery Current Consumption......................................................................................................73
Table 12-1: SP5100 21 mm x 21 mm 0.8 mm Pitch 528-FCBGA Physical Dimensions............................................74
Table 13-1 SP5100 Thermal Limits........................................................................................................................76
Table 14-1: Signals for the Test Controller of the SP5100 ......................................................................................77
Table 14-2: Test Mode Signals..............................................................................................................................77
Table 14-3: TEST0 Bit Sequence ..........................................................................................................................77
Table 14-4: Truth Table for an XOR Chain.............................................................................................................79
Table 14-5: List of Pins on the SP5100 XOR Chain and the Order of Connection....................................................79
Table 14-6: Pins Excluded from the XOR Chain.....................................................................................................83

AMD SP5100 Databook 44409 Rev. 1.70 Oct 10
8
Introduction
1 Introduction
AMD’s SP5100 is a Southbridge that integrates key I/O, communications, and other features required in a
state-of-the-art server platform into a single device. It is specifically designed to operate with AMD’s
server Northbridges.
1.1 Features of the SP5100
CPU Interface
Supports AMD OpteronTM server class
processors, including:
Socket F processors (“Barcelona,”
Shanghai,” and “Istanbul” series
only)
Socket G34 processors
Socket C32 processors
A-Link Express II interface to AMD
Northbridges
1 / 2 / 4-lane A-Link Express II interface
Dynamic detection of lane configuration
High data transfer bandwidth (up to 2.5 Gb/s
/ Lane)
PCI Host Bus Controller
Supports PCI bus at 33 MHz
PCI Rev. 2.3 specification support
Supports up to 6 bus master devices
Supports 40-bit addressing
Interrupt steering supported for plug-n-play
devices
BIOS / Hardware support to hide PCI device
Spread spectrum support
USB Controllers
5 OHCI and 2 EHCI Host controllers to
supports 12 USB 2.0 ports and 2 dedicated
USB 1.1 ports
ACPI S1 ~ S5 supported
Legacy Keyboard/Mouse support
USB debug port
Port disable supported with individual control
SMBus Controller
SMBus Rev. 2.0 compliant
Support SMBALERT # signal / GPIO
Interrupt Controller
Supports IOAPIC/X-IO APIC mode for 24
channels of interrupts
Supports 8259 legacy mode for 15 interrupts
Supports programmable level/edge
triggering on each channels
Supports serial interrupt on quiet and
continuous modes
DMA Controller
Two cascaded 8237 DMA controllers
Supports PC/PCI DMA
Supports LPC DMA
Supports type F DMA
LPC Host Bus Controller
Supports LPC based super I/O and flash
devices
Two Master/DMA devices supported
Support for TPM version 1.1/1.2 devices
Supports SPI devices
SATA Controller
Supports six SATA ports with transfer rates
up to 3 Gb/s
Complies with SATA 2.5 specification

44409 Rev. 1.70 October 10 AMD SP5100 Databook
Introduction
9
Supports both SATA 1.5 and SATA 3.0
compliance devices
Two modes of operation are supported
Legacy Mode using I/O space
AHCI mode using the Memory space
Parallel ATA emulation supported to allow
seamless support for IDE software.
Supports e-SATA
Supports hot plug for AHCI mode
Legacy IDE Emulation Support
Legacy Mode using I/O space
Parallel ATA emulation supported to allow
seamless support for IDE software.
RAID Support
Supports integrated RAID 0, RAID 1, and
RAID 10 (requires use of 4 or more SATA
ports) functionalities across all 6 ports.
Note: AMD does not provide RAID drivers
for the SP5100.
AHCI Support
AHCI mode using the memory space
Supports AHCI hardware assist to support
advanced features such as NCQ (Native
Command Queuing), hot plug, and Device
or Host initiated power Management (DIPM
/HIPM)
IDE Controller
Single PATA channel support
Supports PIO, Multi-word DMA, and Ultra
DMA 33/66/100/133 modes.
32x32-byte buffers each channel for
buffering
Swap bay support by tri-state IDE signals
Integrated IDE series resistor
High Definition Audio
4 Independent output streams (DMA)
4 Independent input streams (DMA)
Multiple channels of audio output per stream
Support up to 4 codec’s
Up to 192 kHz Sample Rate and 32-bit
Audio
64-bit addressing capability for DMA Bus
Master
Unified Audio Architecture (UAA) compatible
HD Audio registers can be located anywhere
in the 64-bit address space
Timers
8254 compatible timer
Microsoft High Precision Event Timer
(HPET)
ACPI power management timer
Watchdog timer
RTC (Real Time Clock)
256-byte battery-backed CMOS RAM
Hardware supported century rollover
RTC battery monitoring feature
Power Management
ACPI specification 3.0 compliant power
management schemes
Supports C1e, C2, C3 and C3 pop-up
Supports S0, S1, S3, S4, and S5
Wakeup events for S1, S3, S4/S5 generated
by:
Any GEVENT pin
Any GPM pin
USB
Power Button
Internal RTC wakeup
SMI# event
Full support for On-Now
CPU SMM support, generating SMI# signal
upon power management events
GPIO supports on external wake up events
CLKRUN# supported on PCI power
management
ALPM (HIPM) on SATA

AMD SP5100 Databook 44409 Rev. 1.70 October 10
10
Introduction
DIPM on SATA
Note: Advanced Power Management (APM) is
not supported.
Hardware Monitor
Hardware monitoring support for voltage
sensors, fan control, and digital TSI to AM3
processors. Note: Temperature monitoring
is NOT supported.

44409 Rev. 1.70 October 10 AMD SP5100 Databook
Introduction
11
1.2 Part Number and Branding
SP5100 Rev A14 Branding
o
Note 1
MADE IN COO
Note 4
Note 3
WXXXXX
Note 5
Note 2
YYWW ENG
218-0660013
SB700S A14
Note 6
Note 7
Figure 1-1: SP5100 Rev A14 Branding Diagram
Note 1: Marketing logo
Note 2: AMD product type
Note 3: Date Code (YYWW). YY-assembly start year, WW-assembly start week.
Note 4: COO. Country of origin (assembly site)
Note 5: This is wafer foundry’s lot number for the product.
Note 6: AMD part number (see below)
Note 7: Pin 1 Orientation

AMD SP5100 Databook 44409 Rev. 1.70 October 10
12
Introduction
SP5100 Rev A15 Eutectic Part Production Branding
SP5100 Rev A15 Lead Free Part Production Branding
o
Note 1
COO
Note 4
Note 3
WXXXXX
Note 5
Note 2
YYWW
218-0660024
SOUTHBRIDGE
Note 6
Note 7
o
COO
WXXXXX
YYWW
218-0660026
SOUTHBRIDGE
Note 1: Marketing logo
Note 2: AMD product type
Note 3: Date Code (YYWW). YY-assembly start year, WW-assembly start week
Note 4: COO. Country of origin (assembly site)
Note 5: This is wafer foundry’s lot number for the product.
Note 6: AMD part number (see below)
Note 7: Pin 1 Orientation
Figure 1-2: SP5100 Rev A15 Branding Diagrams
Table 1-1: SP5100 Part Numbers
ASIC Revision AMD Part Number
A14
218-0660013
A15 Eutectic Part
218-0660024
A15 Lead Free Part
218-0660026

44409 Rev. 1.70 October 10 AMD SP5100 Databook
SP5100 Block Diagram
13
2 SP5100 Block Diagram
LPC
LPC /FWH/SPI Rom interface
PCI Bridge SMBUS /ACPI
AB
HD Audio
PORT 1 PORT 0
USB:OHCI(x5)
USB:EHCI(x2)
8250 TIMER
GPIO
RTC
ACPI / HW
Monitor SMBUS
BUS Controler
APIC/ PIC
INTERRUPT
controller
SMI
SIRQ
PM
SPEAKER
GEVENT[7:0],SLPBUTTON
GPM [9:0]TEMPDEAD,
TEMPCAUT,
SHUTDOWN,DC_STOP#
SCIOUT,
SOFF#
INT# H:A
LDTRST#
RESET#
PWRGOOD
A-LINK
B-LINK
PICD[0]
RTC_IRQ#,
PIDE_INTRQ,
USB_IRQ#,
SATA_IRQ#,
AZ_IRQ#
X1/X2
12 USB2.0 + 2
USB1.1 PORTS
SERIRQ#
6 PCI SLOTS LPC bus
SPI bus
Debug port
B-LINK A-LINK
Alink Express II
IMC
8051
EC_INT
25MHz X1 / X2
Flash
Controller
(Not supported as
production feature)
SATA
Controller 6 PORTS(
GEN-II )
IDE
1 CHANNEL
FC interface
IDE interface
HD Link
ASF
SMBUS
Figure 2-1: SP5100 Block Diagram Showing the Internal PCI Devices and Major Function Blocks

AMD SP5100 Databook 44409 Rev. 1.70 October 10
14
SP5100 Power on Sequence and Timing
3 SP5100 Power on Sequence and Timing
3.1 Power Up and Down Sequences
Simple diagrams of the SP5100 power up sequences are shown in Figure 3-1 and Figure 3-2 below. A
power detection circuit is integrated into the SP5100. This circuit will monitor SB PWR_GOOD and will
assert A_RST# and LDT_RST# for as long as SB PWR_GOOD is false. After SB PWR_GOOD has been
asserted, A_RST#, followed by LDT_RST#, will be de-asserted. Table 4-1 shows the timing requirements
referenced in Figure 3-1 through Figure 3-5. Besides the illustrated requirements, it is also required that
the ramp time for any rail be less than 40ms.
Table 3-1: SP5100 Power Up/Down Sequence Timing
Symbol
Min.
Max.
Description
T1
Note 1
+3.3V_S5 to +1.2V_S5
T2
10 ms
–
+3.3V_S5 to resume reset (RSMRST#).
T2A – 50 ms
Resume reset (RSMRST#) rise time (10% to 90%). SP5100 has a
Schmitt trigger input with de-bouncing logic on this pin, so the value is
relaxed relative to earlier AMD SB designs.
T3
32 ms
–
RSMRST# de-asserted to Start of RTCCLK output from SP5100.
T4
50 ns
SB PWR_GOOD de-assertion to NB_PWRGD de-assertion delay.
T7 0 ns 30 ns
SB PWR_GOOD assertion to NB_PWRGD assertion delay when using
the SP5100 NB_PWRGD output. This parameter is the internal delay of
the SB. The system board design may add additional delay due to
loading and trace length. The acceptable delay including system layout /
loading is 1 ms maximum..
T7A – 50 ms
SB PWR_GOOD rise time (10% to 90 %). See Note 3. SP5100 has a
Schmitt trigger with de-bouncing logic on this pin, so the value is relaxed
relative to earlier AMD SB designs.
T7B
–
1 ms
SB PWR_GOOD fall time.
T8A
0 ns
100 ns A_RST# (PCI host bus reset) to PCIRST#.
Note 4
T8B
–
Note 5
KBRST# to A_RST#.
T8C
1.0 ms
2.3 ms
PCIRST# to LDT_RST#.
T8D
98 ms
108 ms
NB_PWRGD to LDT_PG.
T9
101 ms
113 ms
SB PWR_GOOD to PCIRST#.
T9A
101 ms
113 ms
SB PWR_GOOD to A_RST# (T9-T8A).
T9B
31 ms
–
SB PWR_GOOD to LDT_STP#. See Note 11
T10
-31 ms
–
PCIE_CLKP/N stable time before SB PWRGOOD assertion.
T11
36 ms
41 ms
SB PWR_GOOD to stable PCICLK 33 MHz. See Note 8.
T13
–
15 ns
Wake Event (except PwrButton) to SLP_S3# / SLP_S5#.
200 ns
–
Wake Event (PwrButton) to SLP_S3# / SLP_S5# (S5/S4/S3

S0)
8 ns
--
Wake Event (PwrButton) to SLP_S3# / SLP_S5# (G3

S5

S0)
T13A 80 ns –
SB PWR_GOOD must be de-asserted before VDD (PS PWOK) drops
more than 5% off the nominal value. See
Note 9.
T14 1 ns –
SB PWR_GOOD de-assertion to Resume Reset (RSMRST#) assertion.
See
Note 10
.
T15 5 s –
[Not illustrated] VBAT to +3.3V_S5 to +1.2V_S5. Must be greater than 5
seconds to allow start time for the internal RTC.
T16A
40 µs
–
LDT_STP# assertion to LDT_RST# assertion.
T16B
4 µs
–
LDT_RST# assertion to SLP_S3# assertion.
See Notes 1 to 12 in the Power Up Sequence Timing Notes section following the timing diagrams.

44409 Rev. 1.70 October 10 AMD SP5100 Databook
SP5100 Power on Sequence and Timing
15
T1
T2A
S5 S5 G3G3 S0
S5 STRAPS
VBAT
VBAT
RTC clock In
+3.3V_S5
1.2V_S5
RSMRST#
S 0 power rails
SB PWR_ GOOD
A_RST#
S0 STRAPS
KBRST#
T8B
PCIRST#
PCIE_ RCLKP/N
T2
PCICLK[5:0]
( See Note1)
NB_ PWRGD
T7
T7A
LDT_PG
( See Note5)
T11
T8A
T9
T9A
LDT_STP#
( Note8)
Wake Event
SLP_S5#/
SLP_S3#
T13
T8D
LDT_RST#
ALLOW_ LDTSTP
WAKE#
PWR_BTN#
PS PWOK
T13A
T7B
( See Note4)
T8C
( See Note6)
RTCCLK out
T3
T10
System clocks ( See Note1 &2)
T4
T9B
Note11
Figure 3-1: SP5100 Power Up/Down Sequence

AMD SP5100 Databook 44409 Rev. 1.70 October 10
16
SP5100 Power on Sequence and Timing
S3 S3
S0
VBAT
VBAT
RTC clock
+3.3V_S5
+1.2V_S5
RSMRST#
S0 power rails
SB PWRGOOD
A_RST#
KBRST#
T8B
PCIRST#
T10
PCIE_RCLKP/N
PCICLK[5:0]
NB_PWRGD
T7
T7A
LDT_PG
(See Note 5)
T11
T8A
T9
T9A
LDT_STP#
(Note 8)
Wake Event
SLP_S3# T13
T8D
LDT_RST#
ALLOW_LDTSTP
WAKE#
PWR_BTN#
PS PWOK
T13A
T7B
(See Note 4)
SLP_S5#
GND
GND
GND
GND
GND
T8C
System clocks (See Note 1 & 2)
T9B
Figure 3-2: SP5100 S3/S0 Power Up/Down Sequence

44409 Rev. 1.70 October 10 AMD SP5100 Databook
SP5100 Power on Sequence and Timing
17
Power up Sequence Timing Notes
Note 1: There is no specific power sequencing requirement other than those indicated in Note
2 below. The SP5100 power rails are grouped in four different voltages:
I. +5 V, which includes V5_VREF
II. +3.3 V, which includes VDDQ, VDD33_18 (IDE mode)
III. +1.2 V, which includes AVDDCK_1.2V, AVDD_SATA, PLLVDD_SATA, PCIE_PVDD,
PCIE_VDDR, CKVDD_1.2V
IV. +1.8 V
Note 2: V5_VREF is used in the SP5100 for the 5-V PCI signal tolerance. VDDQ (+3.3 V) &
VDD33_18 (3.3 V) must not exceed V5_VREF by more than 0.6 V at any time during ramp up,
steady state, or ramp down. The suggested circuit below should be used to maintain
relationship between V5_VREF and VDDQ and VDD33_18.
D1
1K
1 µF
+3.3V_S0
+5V_S0
SB
V5_VREF
VDDQ
VDD33_18
SCHOTTKY DIODE
RECOMENDED
Figure 3-3: Circuit for Maintaining Proper Relationship between +V5_VREF and VDDQ
Note 3: The SP5100 will latch the straps after rising edge of SB PWR_GOOD only once. With
debouncing of SB PWR_GOOD, the latching of strap will occur at approximately ~10ms after
the rising edge of SB PWR_GOOD.
Note 4: Typical time between A_RST# and PCIRST# is 75 ns. The measurement should be
done at 10% of both signals. Loading on the motherboard may cause the measurement at
90% be more than the spec.
Note 5: The KBRST# should be de-asserted before A_RST# (LDT_RST#) is de-asserted.
Note 6: Type II Standard and Debug straps will be latched after SB PWR_GOOD is asserted.
Type I straps are latched on resume reset rising edge. Refer to Section 4: SP5100 Strap
Information for strap timing.
Note 7: The SP5100 will not monitor the ALLOW_LDTSTP signal on power up. This signal is
only used on C3 transitions.
Note 8: The PCI Clock may be stable before T11 min. under some conditions; however in all
cases, the PCI Clock is guaranteed to be stable only between T11 min and max.
Note 9: The SP5100 will monitor internally the power down events and protect the internal
circuit during the power down event. This includes power down during the S3, S4, and S5
states. During an unexpected power failure or G3 state, the relationship between the 1.2 V
(VDD) and SB Power Good should be maintained to protect the internal logic of the SP5100.

AMD SP5100 Databook 44409 Rev. 1.70 October 10
18
SP5100 Power on Sequence and Timing
Note 10: The following figure shows the timing of SB PWR_GOOD de-asserted to RSMRST#
de-asserted during a power down sequence. However, this timing only applies to S0 to G3
state transition, because G3 state is where both signals are inactivated.
SB PWR_GOOD
T14
RSMRST#
S0 to G3
Figure 3-4: Timing for SB PWR_GOOD De-asserted to RSMRST# De-asserted
Note 11: On first power up, G3 S5, or after RSMRST# assertion, the LDT_STP# will be asserted
with CPU_VDDIO power. On subsequent power up, S5 S0, the timing on T9B will apply.
CPU_VDDIO
LDT_STP#
SB PWRGOOD
Timing is system
depended
Figure 3-5: Timing for LDT_STP# assertion on first power up (G3 S5)

44409 Rev. 1.70 October 10 AMD SP5100 Databook
SP5100 Power on Sequence and Timing
19
Note 12:The S5_3.3V ramp down should be controlled to achieve a slew rate of 8mV/ µS or lower.
S5_3.3V
Min Slew Rate:
8 mV/µS
Figure 3-6: S5_3.3V Power Down Sequence Requirement

AMD SP5100 Databook 44409 Rev. 1.70 October 10
20
SP5100 Strap Information
4 SP5100 Strap Information
There are two kinds of strap-latching logic, Type I and Type II. Type I straps will be latched on G3 to S5
transition on rising edge of RSMRST#. Type II straps are latched on S5 to S0 transition after rising edge
of PWR_GOOD assertion.
S5_1.2V
STRAPs(board)
PwrGood
RsmRst#
VDD
Straps Type I
Straps I
Capture
Straps Type II
Straps I
Straps Type I
Straps Type II
Undefined
Straps II
Capture
Straps II
Don't care
Figure 4-1: Straps Capture
POWER GOOD
PCI_RST#
PCI Clock signal is tristate can be
High or Low
PCI device will
functional here
PCI device in Reset
PCI reset asserted
PCI Clock stable 33 MHz
PCI Clock
Strap signal
must be stable
and at valid
state
Undefined
Timing is system
dependent 25 ms T1
~31 ms
S5 3.3V /S5 1.2V
Figure 4-2: Type II Straps Capture timing