Analog Devices SHARC ADSP-214 Series Application guide

a
ADSP-214xx SHARC®Processor
Hardware Reference
Includes ADSP-2146x, ADSP-2147x,
ADSP-2148x Product Families
Revision 0.3, July 27, 2010
Part Number
82-000469-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
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Copyright Information
© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This
document may not be reproduced in any form without prior, express writ-
ten consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
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accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, the SHARC
logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog
Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
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ADSP-214xx SHARC Processor Hardware Reference iii
CONTENTS
CONTENTS
PREFACE
Purpose of This Manual ................................................................ lxi
Intended Audience ........................................................................ lxi
Manual Contents ......................................................................... lxii
What’s New in This Manual ........................................................ lxv
Technical or Customer Support ................................................... lxvi
Registration for MyAnalog.com ............................................. lxvi
EngineerZone ....................................................................... lxvii
Social Networking Web Sites ................................................ lxvii
Supported Processors .................................................................. lxvii
Product Information ................................................................. lxviii
Analog Devices Web Site ..................................................... lxviii
VisualDSP++ Online Documentation ................................. lxviii
Technical Library CD ............................................................ lxix
Notation Conventions .................................................................. lxx
INTRODUCTION
Design Advantages ........................................................................ 1-1
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SHARC Family Product Offerings ........................................... 1-2
Processor Architectural Overview .................................................. 1-2
Processor Core ........................................................................ 1-2
I/O Peripherals ....................................................................... 1-3
I/O Processor ..................................................................... 1-3
Digital Audio Interface (DAI) ............................................. 1-3
Interrupt Controller ........................................................... 1-4
Signal Routing Unit ............................................................ 1-4
Digital Peripheral Interface (DPI) ....................................... 1-4
Interrupt Controller ........................................................... 1-4
Signal Routing Unit 2 ......................................................... 1-5
Development Tools ....................................................................... 1-5
Differences from Previous Processors ............................................. 1-5
I/O Architecture Enhancements .............................................. 1-6
I/O PROCESSOR
Features ........................................................................................ 2-2
Register Overview ......................................................................... 2-3
DMA Channel Registers ............................................................... 2-3
DMA Channel Allocation ....................................................... 2-3
Standard DMA Parameter Registers ......................................... 2-4
Extended DMA Parameter Registers ........................................ 2-8
Data Buffers ......................................................................... 2-10
Chain Pointer Registers ......................................................... 2-11
TCB Storage ............................................................................... 2-13
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ADSP-214xx SHARC Processor Hardware Reference v
Contents
Serial Port TCB ..................................................................... 2-14
SPI TCB ............................................................................... 2-14
UART TCB .......................................................................... 2-15
Link Port TCB ...................................................................... 2-15
FIR Accelerator TCB ............................................................. 2-16
IIR Accelerator TCB .............................................................. 2-17
FFT Accelerator TCB ............................................................ 2-18
External Port TCB ................................................................. 2-19
Clocking ..................................................................................... 2-22
Functional Description ............................................................... 2-22
Automated Data Transfer ....................................................... 2-22
DMA Transfer Types ............................................................. 2-23
DMA Direction ..................................................................... 2-24
Internal to External Memory ............................................. 2-24
Peripheral to Internal Memory .......................................... 2-24
Peripheral to External Memory (SPORTs) .......................... 2-25
Internal Memory to Internal Memory ................................ 2-25
DMA Controller Addressing .................................................. 2-25
Internal Index Register Addressing ..................................... 2-27
External Index Register Addressing .................................... 2-28
DMA Channel Status ............................................................ 2-28
DMA Start and Stop Conditions ............................................ 2-29
Operating Modes ........................................................................ 2-30
DMA Chaining ..................................................................... 2-32
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TCB Memory Storage ....................................................... 2-32
Chain Assignment ............................................................ 2-33
Starting Chain Loading .................................................... 2-34
TCB Chain Loading Priority ............................................. 2-35
Chain Insert Mode (SPORTs Only) .................................. 2-36
Fixed DMA Channel Arbitration ........................................... 2-36
Peripheral DMA Bus ......................................................... 2-42
External Port DMA Bus .................................................... 2-43
SPORT/External Port DMA Bus ....................................... 2-43
Rotating DMA Channel Arbitration ...................................... 2-44
Rotating Priority by Group ............................................... 2-44
Interrupts ................................................................................... 2-45
Sources ................................................................................. 2-45
Unchained DMA Interrupts .............................................. 2-45
Chained DMA Interrupts ................................................. 2-46
Transfer Completion Types .................................................... 2-46
Internal Transfer Completion ............................................ 2-47
Access Completion ........................................................... 2-47
Core Single Word Transfer Interrupts .................................... 2-47
Interrupt Versus Channel Priorities ........................................ 2-48
Debug Features ........................................................................... 2-49
Emulation Considerations ..................................................... 2-49
Effect Latency ............................................................................ 2-49
Write Effect Latency ............................................................. 2-49
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ADSP-214xx SHARC Processor Hardware Reference vii
Contents
IOP Effect Latency ................................................................ 2-49
IOP Throughput ................................................................... 2-50
Programming Model ................................................................... 2-50
General Procedure for Configuring DMA .............................. 2-51
EXTERNAL PORT
Features ....................................................................................... 3-2
Pin Descriptions ........................................................................... 3-3
Pin Multiplexing ..................................................................... 3-3
Register Overview ......................................................................... 3-3
Clocking AMI/SDRAM ................................................................ 3-5
Clocking AMI/DDR2 ................................................................... 3-6
External Port Arbitration ............................................................... 3-7
Functional Description ................................................................. 3-7
Operating Mode .................................................................... 3-10
Arbitration Freezing .......................................................... 3-10
Asynchronous Memory Interface ................................................. 3-10
Features ................................................................................. 3-11
Functional Description .......................................................... 3-11
Asynchronous Reads ......................................................... 3-12
Asynchronous Writes ......................................................... 3-12
Parameter Timing ............................................................. 3-14
Idle Cycles ........................................................................ 3-14
Address Mapping .............................................................. 3-14
Operating Modes ................................................................... 3-15
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Data Packing .................................................................... 3-15
External Access Extension ................................................ 3-15
Predictive Reads ............................................................... 3-16
SDRAM Controller
(ADSP-2147x/ADSP-2148x) ................................................... 3-17
Features ................................................................................ 3-17
Functional Description ......................................................... 3-18
SDRAM Commands ........................................................ 3-20
Load Mode Register ...................................................... 3-20
Bank Activation ............................................................ 3-21
Single Precharge ........................................................... 3-21
Precharge All ................................................................ 3-22
Read/Write ................................................................... 3-22
Auto-Refresh ................................................................ 3-24
No Operation/Command Inhibit .................................. 3-24
Command Truth Table ................................................. 3-24
Address Mapping .............................................................. 3-25
Address Translation Options ......................................... 3-26
Address Width Settings ................................................. 3-27
16-Bit Address Mapping ................................................... 3-28
Refresh Rate Control ........................................................ 3-32
Internal SDRAM Bank Access ........................................... 3-34
Single Bank Access ........................................................ 3-34
Multibank Access .......................................................... 3-35
Multi Bank Operation with Data Packing ..................... 3-36
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ADSP-214xx SHARC Processor Hardware Reference ix
Contents
Timing Parameters ............................................................ 3-37
Fixed Timing Parameters ............................................... 3-37
Data Mask ........................................................................ 3-38
Resetting the Controller .................................................... 3-38
Operating Modes ................................................................... 3-38
Parallel Connection of SDRAMs ....................................... 3-38
Buffering Controller for Multiple SDRAMs ................... 3-39
SDRAM Read Optimization ............................................. 3-40
Core Accesses ................................................................ 3-41
DMA Access ................................................................. 3-43
Notes on Read Optimization ......................................... 3-43
Self-Refresh Mode ............................................................. 3-44
Forcing SDRAM Commands ............................................. 3-45
Force Precharge All ....................................................... 3-45
Force Load Mode Register ............................................. 3-46
Force Auto-Refresh ........................................................ 3-46
DDR2 DRAM Controller (ADSP-2146x) .................................... 3-46
Features ................................................................................. 3-46
Pin Descriptions .................................................................... 3-48
Functional Description .......................................................... 3-48
DDR2 Commands ............................................................ 3-51
Load Mode Register ...................................................... 3-51
Load Extended Mode Register ...................................... 3-52
Load Extended Mode Register 2 ................................... 3-53
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Load Extended Mode Register 3 ................................... 3-53
Bank Activation ............................................................ 3-53
Precharge ...................................................................... 3-54
Precharge All ................................................................ 3-54
Burst Read .................................................................... 3-54
Burst Write ................................................................... 3-55
Auto-Refresh ................................................................ 3-56
Self-Refresh Entry ......................................................... 3-57
Self-Refresh Exit ........................................................... 3-57
Precharge Power-Down Entry ....................................... 3-58
Precharge Power-down Exit ........................................... 3-59
No Operation/Command Inhibit .................................. 3-60
Address Mapping .............................................................. 3-60
Address Translation Options ......................................... 3-60
Page Interleaving Map .................................................. 3-60
Bank Interleaving Map .................................................. 3-61
Address Width Settings ................................................. 3-61
16-Bit Address Mapping ............................................... 3-62
Address Map Tables ...................................................... 3-63
Refresh Rate ..................................................................... 3-66
Data Mask ........................................................................ 3-68
Resetting the Controller .................................................... 3-68
Disabling the Controller ................................................... 3-69
Initialization Sequence .......................................................... 3-69
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Contents
Initialization Time ............................................................ 3-70
Internal DDR2 Bank Access .............................................. 3-71
Single Bank Access ........................................................ 3-71
Multibank Access .......................................................... 3-71
Force Activation Window .............................................. 3-72
Multi Bank Operation with Data Packing ..................... 3-73
Fixed Timing Parameters ............................................... 3-74
Operating Modes ................................................................... 3-75
Parallel Connection of DDR2s .......................................... 3-75
Buffering Controller for Multiple DDR2s ...................... 3-76
Read Optimization ............................................................ 3-76
DDR2 Read Optimization ............................................ 3-77
Self-Refresh Mode ......................................................... 3-79
Single-Ended Data Strobe .............................................. 3-81
On Die Termination (ODT) ......................................... 3-81
Additive Latency ........................................................... 3-82
Forcing DDR2 Commands ........................................... 3-82
Data Transfer .............................................................................. 3-84
Data Buffers .......................................................................... 3-84
AMI Receive Buffer ........................................................... 3-84
AMI Transmit Buffer ........................................................ 3-84
DMA Buffer ..................................................................... 3-85
Core Access ........................................................................... 3-85
External Port Dual Data Fetch ........................................... 3-85
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xii ADSP-214xx SHARC Processor Hardware Reference
Conditional Instructions ................................................... 3-86
SIMD Access ........................................................................ 3-86
SDRAM ........................................................................... 3-86
DDR2 .............................................................................. 3-87
External Instruction Fetch ................................................ 3-88
Interrupt Vector Table (IVT) ........................................ 3-88
Fetching ISA Instructions From External Memory ......... 3-89
Instruction Packing ....................................................... 3-90
16-Bit Instruction Storage and Packing ......................... 3-90
8-Bit Instruction Storage and Packing ........................... 3-92
Mixing Instructions and Data in External Bank 0 .......... 3-93
Addressing for Various Memory Sizes ............................ 3-93
Writing Instructions to External Memory ...................... 3-94
Instruction Cache ......................................................... 3-95
Fetching VISA Instructions From External Memory .......... 3-98
External Port DMA .................................................................. 3-100
External Port DMA Parameter Registers .............................. 3-100
Operating Modes ................................................................ 3-102
Internal DMA Addressing ............................................... 3-102
Standard DMA ............................................................... 3-103
Circular Buffered DMA .................................................. 3-103
Chained DMA Mode .......................................................... 3-104
Changing DMA Direction on the Fly .............................. 3-104
Scatter/Gather DMA ........................................................... 3-106
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ADSP-214xx SHARC Processor Hardware Reference xiii
Contents
External Address Calculation ........................................... 3-106
Delay Line DMA ................................................................. 3-111
External Address Calculation for Reads ............................ 3-112
Interrupts ................................................................................ 3-114
Access Completion .......................................................... 3-115
Internal Transfer Completion .......................................... 3-115
Interrupt Dependency on DMA Mode ............................ 3-115
External Port Throughput ......................................................... 3-116
AMI Data Throughput ........................................................ 3-117
SDRAM Throughput .......................................................... 3-117
Throughput Conditional Instructions .............................. 3-117
DDR2 Throughput ............................................................. 3-118
DMA Throughput .......................................................... 3-118
Core Throughput ............................................................ 3-118
External Instruction Fetch Throughput ................................ 3-119
Effect Latency ........................................................................... 3-120
Write Effect Latency ............................................................ 3-121
Programming Models ................................................................ 3-121
External Port ....................................................................... 3-121
DMA .................................................................................. 3-121
Standard DMA .............................................................. 3-121
Chained DMA ................................................................ 3-122
Delay Line DMA ............................................................ 3-123
Disabling and Re-enabling DMA ..................................... 3-124
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Additional Information ................................................... 3-124
AMI Initialization .......................................................... 3-125
SDRAM Controller ............................................................. 3-126
Power-Up Sequence ........................................................ 3-126
Output Clock Generator Programming Model ................ 3-127
Self-Refresh Mode .......................................................... 3-127
Changing the VCO Clock During Runtime ................... 3-128
DDR2 Controller ............................................................... 3-129
Power-Up Sequence ........................................................ 3-129
Frequency Change in Precharge Power-Down Mode ........ 3-130
External Instruction Fetch ................................................... 3-131
AMI Configuration ........................................................ 3-132
SDRAM Configuration .................................................. 3-132
External Memory Access Restrictions ................................... 3-132
LINK PORTS—ADSP-2146X
Features ........................................................................................ 4-2
Pin Descriptions ........................................................................... 4-3
Register Overview ......................................................................... 4-3
Clocking ...................................................................................... 4-4
Functional Description ................................................................. 4-4
Architecture ............................................................................ 4-5
Protocol .................................................................................. 4-5
Intercommunication ............................................................... 4-7
Self-Synchronization ............................................................. 4-10
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Contents
Multi-Master Conflicts .......................................................... 4-10
Example Token Passing .......................................................... 4-11
Data Transfer .............................................................................. 4-13
Link Buffers .......................................................................... 4-13
Transmit Buffer ................................................................. 4-14
Receive Buffer ................................................................... 4-14
Buffer Status ..................................................................... 4-15
Core Transfers ....................................................................... 4-15
DMA Transfers ...................................................................... 4-16
Interrupts ................................................................................... 4-16
Interrupt Sources ................................................................... 4-17
Interrupt Service ................................................................... 4-17
Access Completion ............................................................ 4-18
Internal Transfer Completion ............................................ 4-18
DMA Access .......................................................................... 4-19
Chained DMA .................................................................. 4-19
Core Access ........................................................................... 4-19
Service Request Interrupts ..................................................... 4-20
Debug Features ........................................................................... 4-21
Shadow Register .................................................................... 4-21
Buffer Hang Disable (BHD) .................................................. 4-22
Effect Latency ............................................................................. 4-22
Write Effect Latency .............................................................. 4-22
Link Port Effect Latency ........................................................ 4-22
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Programming Model ................................................................... 4-22
Changing the Link Port Clock ............................................... 4-23
Receive DMA ....................................................................... 4-24
Transmit DMA ..................................................................... 4-24
MEMORY-TO-MEMORY PORT DMA
Features ........................................................................................ 5-2
Register Overview ......................................................................... 5-2
Clocking ...................................................................................... 5-2
Functional Description ................................................................. 5-3
Data Transfer Types ...................................................................... 5-3
Data Buffer ............................................................................. 5-3
DMA Transfer ........................................................................ 5-4
Interrupts ..................................................................................... 5-4
MTM Throughput ....................................................................... 5-5
Effect Latency .............................................................................. 5-5
Write Effect Latency ............................................................... 5-5
MTM Effect Latency .............................................................. 5-5
Programming Model ..................................................................... 5-5
FFT/FIR/IIR HARDWARE MODULES
FFT Accelerator ............................................................................ 6-3
Features .................................................................................. 6-4
Register Descriptions .............................................................. 6-4
Clocking ................................................................................. 6-5
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Functional Description ............................................................ 6-5
Compute Block ................................................................... 6-5
Data Memory ..................................................................... 6-6
Coefficient Memory ............................................................ 6-6
Accelerator States ................................................................ 6-6
Reset State ...................................................................... 6-6
Idle State ........................................................................ 6-7
Read State ....................................................................... 6-7
Processing State ............................................................... 6-7
Write State ...................................................................... 6-7
Internal Memory Storage ..................................................... 6-8
Small FFT N<=256 ........................................................ 6-8
Large FFT N>=256 ........................................................ 6-9
Operating Modes ................................................................... 6-11
Small FFT Computation (<= 256 Points) .......................... 6-11
Large FFT Computation (>= 512 Points) .......................... 6-11
Example for FFT Size N=512 ............................................ 6-12
Vertical FFT ................................................................. 6-12
Special Product—Number of Iterations is N/128 = 4 ..... 6-12
Horizontal FFT ............................................................. 6-13
No Repeat Mode ............................................................... 6-14
Repeat Mode .................................................................... 6-14
Unpacked Data Mode ...................................................... 6-14
Inverse FFT ...................................................................... 6-15
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Data Transfer ........................................................................ 6-15
FFT Buffers ...................................................................... 6-15
DMA Transfers ................................................................. 6-15
DMA Channels and TCB Structure .............................. 6-16
Chained DMA .............................................................. 6-16
Interrupts ............................................................................. 6-17
Interrupt Sources ............................................................. 6-18
Servicing DMA Interrupts ................................................ 6-18
Servicing MAC Status Interrupts ....................................... 6-18
FFT Performance .................................................................. 6-19
Small FFT (N is <= 256) ................................................... 6-19
Large FFT (N >= 256) ...................................................... 6-19
Vertical FFT cycles .......................................................... 6-20
Special Prod cycles ............................................................ 6-20
Horizontal FFT cycles ...................................................... 6-20
Debug Features ..................................................................... 6-20
Local Memory Access ....................................................... 6-20
Shadow Register ............................................................... 6-20
Effect Latency ....................................................................... 6-21
Write Effect Latency ......................................................... 6-21
FFT Accelerator Effect Latency ......................................... 6-21
Programming Model ............................................................. 6-21
N <= 256, No Repeat ....................................................... 6-21
N <= 256, Repeat ............................................................. 6-22
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N >= 512, No Repeat ........................................................ 6-24
Configure the FFT Control Register .............................. 6-24
Vertical FFT Configuration ........................................... 6-25
Special Buffer Configuration ......................................... 6-25
Horizontal FFT Configuration ...................................... 6-26
N >= 512, Repeat ............................................................. 6-26
Debug Mode ..................................................................... 6-27
Write to Local Memory ................................................. 6-27
Read from Local Memory .............................................. 6-28
FIR Accelerator ........................................................................... 6-28
Features ................................................................................. 6-28
Register Overview ................................................................. 6-29
Clocking ............................................................................... 6-29
Functional Description .......................................................... 6-30
Compute Block ................................................................. 6-31
Partial Sum Register .......................................................... 6-32
Delay Line Memory .......................................................... 6-33
Coefficient Memory .......................................................... 6-33
Prefetch Data Buffer ......................................................... 6-33
Processing Output ............................................................. 6-34
Internal Memory Storage ................................................... 6-35
Coefficients and Input Buffer Storage ............................ 6-35
Operating Modes ................................................................... 6-37
Single Rate Processing ....................................................... 6-37
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Single Iteration ............................................................. 6-37
Multi-Iteration ............................................................. 6-37
Window Processing ......................................................... 6-38
Multi Rate Processing ...................................................... 6-38
Decimation ...................................................................... 6-38
Interpolation .................................................................... 6-39
Channel Processing ........................................................... 6-40
Floating-Point Data Format .............................................. 6-42
Fixed-Point Data Format .................................................. 6-42
Data Transfer ........................................................................ 6-42
DMA Access ..................................................................... 6-42
Chain Pointer DMA ..................................................... 6-43
Interrupts ............................................................................. 6-44
Interrupt Sources .............................................................. 6-45
Debug Features ..................................................................... 6-45
Local Memory Access ....................................................... 6-45
Single Step Mode .............................................................. 6-46
Emulation Considerations ................................................ 6-46
Effect Latency ....................................................................... 6-46
Write Effect Latency ......................................................... 6-46
FIR Accelerator Effect Latency .......................................... 6-46
FIR Throughput ................................................................... 6-47
Additional Information ..................................................... 6-48
Programming Model ............................................................. 6-48
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