Analog Devices SHARC ADSP-214 Series Application guide

a
ADSP-214xx SHARC®Processor
Hardware Reference
Includes ADSP-2146x, ADSP-2147x,
ADSP-2148x Product Families
Revision 0.3, July 27, 2010
Part Number
82-000469-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
www.BDTIC.com/ADI

Copyright Information
© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This
document may not be reproduced in any form without prior, express writ-
ten consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, the SHARC
logo, TigerSHARC, and VisualDSP++ are registered trademarks of Analog
Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
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ADSP-214xx SHARC Processor Hardware Reference iii
CONTENTS
CONTENTS
PREFACE
Purpose of This Manual ................................................................ lxi
Intended Audience ........................................................................ lxi
Manual Contents ......................................................................... lxii
What’s New in This Manual ........................................................ lxv
Technical or Customer Support ................................................... lxvi
Registration for MyAnalog.com ............................................. lxvi
EngineerZone ....................................................................... lxvii
Social Networking Web Sites ................................................ lxvii
Supported Processors .................................................................. lxvii
Product Information ................................................................. lxviii
Analog Devices Web Site ..................................................... lxviii
VisualDSP++ Online Documentation ................................. lxviii
Technical Library CD ............................................................ lxix
Notation Conventions .................................................................. lxx
INTRODUCTION
Design Advantages ........................................................................ 1-1
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Contents
iv ADSP-214xx SHARC Processor Hardware Reference
SHARC Family Product Offerings ........................................... 1-2
Processor Architectural Overview .................................................. 1-2
Processor Core ........................................................................ 1-2
I/O Peripherals ....................................................................... 1-3
I/O Processor ..................................................................... 1-3
Digital Audio Interface (DAI) ............................................. 1-3
Interrupt Controller ........................................................... 1-4
Signal Routing Unit ............................................................ 1-4
Digital Peripheral Interface (DPI) ....................................... 1-4
Interrupt Controller ........................................................... 1-4
Signal Routing Unit 2 ......................................................... 1-5
Development Tools ....................................................................... 1-5
Differences from Previous Processors ............................................. 1-5
I/O Architecture Enhancements .............................................. 1-6
I/O PROCESSOR
Features ........................................................................................ 2-2
Register Overview ......................................................................... 2-3
DMA Channel Registers ............................................................... 2-3
DMA Channel Allocation ....................................................... 2-3
Standard DMA Parameter Registers ......................................... 2-4
Extended DMA Parameter Registers ........................................ 2-8
Data Buffers ......................................................................... 2-10
Chain Pointer Registers ......................................................... 2-11
TCB Storage ............................................................................... 2-13
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ADSP-214xx SHARC Processor Hardware Reference v
Contents
Serial Port TCB ..................................................................... 2-14
SPI TCB ............................................................................... 2-14
UART TCB .......................................................................... 2-15
Link Port TCB ...................................................................... 2-15
FIR Accelerator TCB ............................................................. 2-16
IIR Accelerator TCB .............................................................. 2-17
FFT Accelerator TCB ............................................................ 2-18
External Port TCB ................................................................. 2-19
Clocking ..................................................................................... 2-22
Functional Description ............................................................... 2-22
Automated Data Transfer ....................................................... 2-22
DMA Transfer Types ............................................................. 2-23
DMA Direction ..................................................................... 2-24
Internal to External Memory ............................................. 2-24
Peripheral to Internal Memory .......................................... 2-24
Peripheral to External Memory (SPORTs) .......................... 2-25
Internal Memory to Internal Memory ................................ 2-25
DMA Controller Addressing .................................................. 2-25
Internal Index Register Addressing ..................................... 2-27
External Index Register Addressing .................................... 2-28
DMA Channel Status ............................................................ 2-28
DMA Start and Stop Conditions ............................................ 2-29
Operating Modes ........................................................................ 2-30
DMA Chaining ..................................................................... 2-32
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Contents
vi ADSP-214xx SHARC Processor Hardware Reference
TCB Memory Storage ....................................................... 2-32
Chain Assignment ............................................................ 2-33
Starting Chain Loading .................................................... 2-34
TCB Chain Loading Priority ............................................. 2-35
Chain Insert Mode (SPORTs Only) .................................. 2-36
Fixed DMA Channel Arbitration ........................................... 2-36
Peripheral DMA Bus ......................................................... 2-42
External Port DMA Bus .................................................... 2-43
SPORT/External Port DMA Bus ....................................... 2-43
Rotating DMA Channel Arbitration ...................................... 2-44
Rotating Priority by Group ............................................... 2-44
Interrupts ................................................................................... 2-45
Sources ................................................................................. 2-45
Unchained DMA Interrupts .............................................. 2-45
Chained DMA Interrupts ................................................. 2-46
Transfer Completion Types .................................................... 2-46
Internal Transfer Completion ............................................ 2-47
Access Completion ........................................................... 2-47
Core Single Word Transfer Interrupts .................................... 2-47
Interrupt Versus Channel Priorities ........................................ 2-48
Debug Features ........................................................................... 2-49
Emulation Considerations ..................................................... 2-49
Effect Latency ............................................................................ 2-49
Write Effect Latency ............................................................. 2-49
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ADSP-214xx SHARC Processor Hardware Reference vii
Contents
IOP Effect Latency ................................................................ 2-49
IOP Throughput ................................................................... 2-50
Programming Model ................................................................... 2-50
General Procedure for Configuring DMA .............................. 2-51
EXTERNAL PORT
Features ....................................................................................... 3-2
Pin Descriptions ........................................................................... 3-3
Pin Multiplexing ..................................................................... 3-3
Register Overview ......................................................................... 3-3
Clocking AMI/SDRAM ................................................................ 3-5
Clocking AMI/DDR2 ................................................................... 3-6
External Port Arbitration ............................................................... 3-7
Functional Description ................................................................. 3-7
Operating Mode .................................................................... 3-10
Arbitration Freezing .......................................................... 3-10
Asynchronous Memory Interface ................................................. 3-10
Features ................................................................................. 3-11
Functional Description .......................................................... 3-11
Asynchronous Reads ......................................................... 3-12
Asynchronous Writes ......................................................... 3-12
Parameter Timing ............................................................. 3-14
Idle Cycles ........................................................................ 3-14
Address Mapping .............................................................. 3-14
Operating Modes ................................................................... 3-15
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Contents
viii ADSP-214xx SHARC Processor Hardware Reference
Data Packing .................................................................... 3-15
External Access Extension ................................................ 3-15
Predictive Reads ............................................................... 3-16
SDRAM Controller
(ADSP-2147x/ADSP-2148x) ................................................... 3-17
Features ................................................................................ 3-17
Functional Description ......................................................... 3-18
SDRAM Commands ........................................................ 3-20
Load Mode Register ...................................................... 3-20
Bank Activation ............................................................ 3-21
Single Precharge ........................................................... 3-21
Precharge All ................................................................ 3-22
Read/Write ................................................................... 3-22
Auto-Refresh ................................................................ 3-24
No Operation/Command Inhibit .................................. 3-24
Command Truth Table ................................................. 3-24
Address Mapping .............................................................. 3-25
Address Translation Options ......................................... 3-26
Address Width Settings ................................................. 3-27
16-Bit Address Mapping ................................................... 3-28
Refresh Rate Control ........................................................ 3-32
Internal SDRAM Bank Access ........................................... 3-34
Single Bank Access ........................................................ 3-34
Multibank Access .......................................................... 3-35
Multi Bank Operation with Data Packing ..................... 3-36
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ADSP-214xx SHARC Processor Hardware Reference ix
Contents
Timing Parameters ............................................................ 3-37
Fixed Timing Parameters ............................................... 3-37
Data Mask ........................................................................ 3-38
Resetting the Controller .................................................... 3-38
Operating Modes ................................................................... 3-38
Parallel Connection of SDRAMs ....................................... 3-38
Buffering Controller for Multiple SDRAMs ................... 3-39
SDRAM Read Optimization ............................................. 3-40
Core Accesses ................................................................ 3-41
DMA Access ................................................................. 3-43
Notes on Read Optimization ......................................... 3-43
Self-Refresh Mode ............................................................. 3-44
Forcing SDRAM Commands ............................................. 3-45
Force Precharge All ....................................................... 3-45
Force Load Mode Register ............................................. 3-46
Force Auto-Refresh ........................................................ 3-46
DDR2 DRAM Controller (ADSP-2146x) .................................... 3-46
Features ................................................................................. 3-46
Pin Descriptions .................................................................... 3-48
Functional Description .......................................................... 3-48
DDR2 Commands ............................................................ 3-51
Load Mode Register ...................................................... 3-51
Load Extended Mode Register ...................................... 3-52
Load Extended Mode Register 2 ................................... 3-53
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Contents
x ADSP-214xx SHARC Processor Hardware Reference
Load Extended Mode Register 3 ................................... 3-53
Bank Activation ............................................................ 3-53
Precharge ...................................................................... 3-54
Precharge All ................................................................ 3-54
Burst Read .................................................................... 3-54
Burst Write ................................................................... 3-55
Auto-Refresh ................................................................ 3-56
Self-Refresh Entry ......................................................... 3-57
Self-Refresh Exit ........................................................... 3-57
Precharge Power-Down Entry ....................................... 3-58
Precharge Power-down Exit ........................................... 3-59
No Operation/Command Inhibit .................................. 3-60
Address Mapping .............................................................. 3-60
Address Translation Options ......................................... 3-60
Page Interleaving Map .................................................. 3-60
Bank Interleaving Map .................................................. 3-61
Address Width Settings ................................................. 3-61
16-Bit Address Mapping ............................................... 3-62
Address Map Tables ...................................................... 3-63
Refresh Rate ..................................................................... 3-66
Data Mask ........................................................................ 3-68
Resetting the Controller .................................................... 3-68
Disabling the Controller ................................................... 3-69
Initialization Sequence .......................................................... 3-69
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