Analog Devices EVAL-ADAU1860 User manual

User Guide | EVAL-ADAU1860
UG-2017
Evaluating the ADAU1860 Three ADCs, One DAC, Low Power Codec with Audio DSPs
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | 1 of 26
EVALUATION KIT CONTENTS
►EVAL-ADAU1860EBZ evaluation board
►USB cable with micro USB plug
►mIDAS-Link emulator
DOCUMENTS NEEDED
►ADAU1860 data sheet
►EVAL-ADAU1860EBZ user guide
GENERAL DESCRIPTION
This user guide explains the design and setup of the EVAL-
ADAU1860EBZ evaluation board.
The EVAL-ADAU1860EBZ provides access to all the analog and
digital inputs and outputs on the ADAU1860. The ADAU1860 core
is controlled by Analog Devices, Inc., Lark Studio™ software, which
interfaces to the EVAL-ADAU1860EBZ via a USB connection. In
addition, users can communicate and debug with the Tensilica HiFi
3z DSP core through the JTAG port by using the mIDAS-Link
emulator. The software development kit (SDK) is also provided by
Analog Devices for code development.
The EVAL-ADAU1860EBZ can be powered by the USB bus or by a
single 5 V supply. These supply options are regulated to the voltag-
es required on the EVAL-ADAU1860EBZ. The printed circuit board
(PCB) is a 4-layer design, with a ground plane and a power plane
on the inner layers. The EVAL-ADAU1860EBZ contains connectors
for external microphones and speakers. The master clock can be
provided externally or by the on-board 24.576 MHz oscillator.
EVAL-ADAU1860EBZ BOARD PHOTOGRAPH
Figure 1.
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User Guide EVAL-ADAU1860
TABLE OF CONTENTS
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Evaluation Kit Contents......................................... 1
Documents Needed...............................................1
General Description...............................................1
EVAL-ADAU1860EBZ Board Photograph............. 1
Evaluation Board Block Diagram...........................3
Setting Up the Evaluation Board........................... 4
Installing the Lark Studio Software.....................4
Installing the USB Drivers.................................. 4
Default Switch and Jumper Settings.................. 4
Setting Up Communication in Software.................5
Powering Up the Evaluation Board.................... 5
Connecting the Audio Cables.............................5
Creating a Basic Signal Flow............................. 5
Using the Evaluation Board................................... 9
Power Supply..................................................... 9
Control Port...................................................... 10
Codec System.................................................. 11
Audio Inputs and Outputs................................. 11
Serial Audio Interface.......................................12
Other Interfaces................................................12
Hardware Description.......................................... 13
Jumpers............................................................13
Evaluation Board Schematics and Artwork......... 15
Ordering Information............................................24
Bill of Materials.................................................24
REVISION HISTORY
10/ 2021—Revision 0 0: Initial Version

User Guide EVAL-ADAU1860
EVALUATION BOARD BLOCK DIAGRAM
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Figure 2. EVAL-ADAU1860EBZ Board Block Diagram

User Guide EVAL-ADAU1860
SETTING UP THE EVALUATION BOARD
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INSTALLING THE LARK STUDIO SOFTWARE
Download and install the latest version of Lark Studio by completing
the following steps:
1. Download the installer and run the executable file.
2. Follow the prompts, including accepting the license agreement,
to install the software.
INSTALLING THE USB DRIVERS
If the USB interface is not recognized by the Lark Studio software
and PC, go to the Future Technology Devices International (FTDI)
Chip official web page and download the relevant drivers.
DEFAULT SWITCH AND JUMPER SETTINGS
Table 1 shows the default switch and jumper settings.
Table 1. Default Switch and Jumper Settings
Jumper and Switch Connections Option Selected
Pin 1 to Pin 2 of P17 AVDD and HPVDD supplied by 1.8 V on-board low dropout (LDO) regulator
Pin 1 to Pin 2 of P48 and JP3 Removed IOVDD supplied by 1.8 V on-board LDO
Pin 1 to Pin 2 of P19 and JP2 Connected HPVDD_L supplied by 1.3 V on-board LDO
Pin 1 to Pin 2 of P18 and JP1 Connected DVDD supplied by 0.9 V on-board LDO
Pin 2 to Pin 3 of P26 Self boot disabled
Pin 2 to Pin 3 of P24 REG_EN disabled
Pin 2 to Pin 3 of P29 ROM boot disabled
S1 Down (SPI), Pin 2 to Pin 3 of P1, Pin 2 to Pin 3 of P4, Pin 2 to Pin 3 of P5, and
Pin 2 to Pin 3 of P6
SPI communication
Pin 1 of S14 to GND and Pin 2 of S14 to GND I2C Address 0x64
Pin 1 to Pin 2 of P8 and Pin 2 to Pin 3 of P27 to P27 The master clock source is the on-board, 24.576 MHz oscillator
Pin 1 to Pin 2 of P104 and Pin 1 to Pin 2 of P105 ADC0 differential mode
Pin 1 to Pin 2 of P12 and Pin 1 to Pin 2 of P14 ADC1 differential mode
Pin 1 to Pin 2 of P13 and Pin 1 to Pin 2 of P15 ADC2 differential mode

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SETTING UP COMMUNICATION IN SOFTWARE
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POWERING UP THE EVALUATION BOARD
To power up the EVAL-ADAU1860EBZ evaluation board, connect
the ribbon cable to P22 of the EVAL-ADAU1860EBZ.
CONNECTING THE AUDIO CABLES
Three channels of the microphone inputs support both differential
and single-end modes. The headphone output is differential and
is dc-coupled. The digital audio signal can be I2S or time division
multiplexing (TDM) mode through the serial audio interface.
CREATING A BASIC SIGNAL FLOW
To create a basic signal flow in LARK Studio, follow these steps:
1. Download and install Lark Studio from www.ana-
log.com/ADAU1860.
2. Start Lark Studio by double clicking the shortcut on the desktop.
3. Click New Project from the Project menu, or click Create a
New Project in the Welcome section to create a new project,
as shown in Figure 3. The New Project window shows the
Project Type options.
4. Click on the Lark option for the ADAU1860 and then OK.
5. Edit the file name, and save the file to a user specified location.
6. Click on Target Connection in the left navigation panel, and
configure the Connection settings panel that opens on the
right to set up the connection. If the USB connects, Target
Connected displays (see Figure 4).
Figure 3. Create a New Project

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SETTING UP COMMUNICATION IN SOFTWARE
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Figure 4. Connect with EVAL-ADAU1860EBZ
Configure the Register Control, FastDSP, and EQ settings on
the left navigation panel. Lark Register Control has multiple tabs
that control different sections of the ADAU1860. Figure 5 shows
the Power tab, which allows the user to power up or power down
various blocks within the ADAU1860. When a block is powered up,
that block can be configured.
The Clock tab allows the phase-locked loop (PLL) to be used or
bypassed. By register default, the PLL is disabled to save power.
To generate a 24.576 MHz master clock, enable or disable the PLL
according to the provided clock source. On the evaluation board,
a 24.576 MHz oscillator and a crystal with same frequency are
supplied. To configure an application, follow these steps:
1. Select Hibernate1, BLOCKS_ON, and CM_BST_ON in the
CHIP_PWR block in the Power tab, and then click Write (see
Figure 5 ).
2. With the default 24.576 MHz oscillator on board, select
MCLK_FREQ_24P576 of MCLK_FREQ_INDEX and set
PLL_FM_BYPASS to PLL_FM_BP in the Clock tab, then click
on Write.
3. Configure the other blocks.
When a register value is changed, click the related Write button in
a block to update a single register, or the Write this Page button
below the tabs to update multiple registers. Click Write All after all
register changes to avoid a configuration error.

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SETTING UP COMMUNICATION IN SOFTWARE
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Figure 5. Register Configurations
If FastDSP is required in the project, a schematic must be created
with the desired path for the ADAU1860 as follows:
1. Click FastDSP in the left navigation panel.
2. In the left pane of the Lark FastDSP Schematic window, click
an arrow to expand a folder.
3. Select and drag an icon into the schematic window, for exam-
ple, the ADC icon within the IO folder (see Figure 6). In
this example, AIN1 and ASRCI0 are being routed to FastDSP
Output 0 and Output 1 separately.
4. To download the correct parameter generated from the sche-
matic, set fs to be the same as the FastDSP source,
FDSP_RATE_SOURCE, which is set in the FastDSP tab in
the Lark Register Control window.
5. Click Download to Target to write the parameter and command
to FastDSP memory. After the download finishes, FastDSP is
enabled and runs automatically.
If the equalizer is required in the project, a configuration of the
filters must be set for the ADAU1860 as follows:
1. Click on EQ in the navigation panel.
2. Select the filter numbers and relative filter parameters.
3. Set fs to be same as the equalizer source, EQ_ROUTE, which
is set in the EQ tab in the Lark RegisterControl window.
4. Click Download to Target to write the parameter and command
to equalizer memory. After the download finishes, the equalizer
is enabled and runs automatically.
If Tensilica HiFi 3z DSP (TDSP) is used, a hex file for the TDSP
program code can be uploaded via Lark Studio as follows:
1. Click TDSP Programming in the navigation panel.
2. Select the hex file that will be uploaded.
3. Click TDSP Program.
4. After uploading is finished, type in the Reset Address for the
program, and then click TDSP Reset. The TDSP then runs
automatically with the uploaded program.
For full details on the operation of Lark Studio, click Getting Start
Guide from the Help menu of the Lark Studio graphical user
interface (GUI).

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SETTING UP COMMUNICATION IN SOFTWARE
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Figure 6. FastDSP Schematic Configuration

User Guide EVAL-ADAU1860
USING THE EVALUATION BOARD
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POWER SUPPLY
Power can be supplied to the EVAL-ADAU1860EBZ in one of three
following ways:
1. Connecting the USB cable to P22.
2. Connecting the 5 V dc power to P47.
3. Connecting the isolated external power supply to P42 for AVDD
and HPVDD, P43 for IOVDD, P45 for HPVDD_L, and P46 for
DVDD.
The FTDI 4232 is powered by an on-board LDO regulator with a
3.3 V output.
Table 2. Power Supply Jumper Setting
Power Source
On-Board LDO Regulator External
Jumper Settings Power Supply Voltage (V) Jumper Settings Port
AVDD and HPVDD Pin 1 to Pin 2 of P17 1.8 Pin 2 to Pin 3 of P17 P42
IOVDD Pin 1 to Pin 2 of P48, JP3 removed 1.8 Pin 2 to Pin 3 of P48, JP3 removed P43
JP3 connected, P48 removed 1.8, connected to AVDD and HPVDD
HPVDD_L Pin 1 to Pin 2 of P19, JP2 connected 1.3 Pin 2 to Pin 3 of P19 P45
Pin 1 to Pin 2 of P19, JP2 removed 1.5
DVDD Pin 1 to Pin 2 of P18, JP1 connected 0.9 Pin 2 to Pin 3 of P18 P46
Pin 1 to Pin 2 of P18, JP1 removed 1.1

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CONTROL PORT
The EVAL-ADAU1860EBZ is configured to serial peripheral inter-
face (SPI) mode by default. To operate the codec in I2C or universal
asynchronous receiver/transmitter (UART) mode, see Table 3.
Table 3. Control Port Jumper and Switch (S1) Settings
Communication Port Address Setting Jumper Settings Switch Settings
SPI Not applicable Pin 2 to Pin 3 of P1, Pin 2 to Pin 3 of P4, Pin 2 to Pin 3 of P5, and Pin 2
to Pin 3 of P6
Down
I2C S14, default 0x64 (00), 0x65 (01), 0x66 (10),
0x67 (11)
Pin 2 to Pin 3 of P1, Pin 2 to Pin 3 of P4, Pin 2 to Pin 3 of P5, and Pin 2
to Pin 3 of P6
Up
UART Not applicable Pin 1 to Pin 2 of P1, Pin 1 to Pin 2 of P4, Pin 1 to Pin 2 of P5, and Pin 1
to Pin 2 of P6