Avnet Qorvo Installation manual

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Copyright © 2019 Avnet, Inc. AVNET, “Reach Further,” and the AV logo are registered
trademarks of Avnet, Inc. All other brands are the property of their respective owners.
Qorvo 1800MHz Small Cell RF Card
Hardware User’s Guide
Version 1.3

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Qorvo 1800MHz Small Cell RF Card Hardware User’s Guide
Contents
1Document Control .................................................................................................3
2Version History......................................................................................................3
3Introduction ...........................................................................................................4
3.1 Zynq UltraScale+ RFSoC Development Kit............................................................................. 5
3.2 Glossary................................................................................................................................... 6
3.3 Reference Documents ............................................................................................................. 7
4Architecture and Features.....................................................................................8
4.1 List of Features ........................................................................................................................ 8
4.2 Block Diagram.......................................................................................................................... 9
5Functional Description.........................................................................................10
5.1 ZCU111 Interface................................................................................................................... 10
5.2 Digital Isolation....................................................................................................................... 11
5.3 Power Options........................................................................................................................ 12
5.4 Attenuators Digital Step Attenuator (DSA) DevicesControl Interfaces.................................. 13
5.4.1 Parallel DSA Control Interface....................................................................................... 13
5.4.2 Serial DSA Control Interface.......................................................................................... 13
5.5 Rebuilding the Reference Design.......................................................................................... 16
5.6 SPI Controller......................................................................................................................... 17
5.7 GPIO Assignments ................................................................................................................ 18
5.8 EEPROM and I2C Interface................................................................................................... 20
5.9 Digital Test Pins..................................................................................................................... 21
5.10 Status LEDs........................................................................................................................... 23
5.11 RFMC Connector Pin Assignments....................................................................................... 24
5.12 Pi Pad Attenuators................................................................................................................. 29
5.13 ADC Input Protection ............................................................................................................. 30
5.13.1 RX-side ADC Over-voltage Protection........................................................................... 30
Rx LNA Bypass Mechanisms ........................................................................................................ 31
5.14 Directional Coupler ................................................................................................................ 32
5.15 Circulator................................................................................................................................ 32
6Regulatory and Compliance Information.............................................................33
7Getting Help and Support....................................................................................34
8Appendix A –Alternate Reverse Build Variant....................................................35

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Hardware User’s Guide
1 Document Control
Document Version: 1.3
Document Date: 11 November 2019
2 Version History
Version
Date
Comment
1.2
24 Oct 2019
Initial Release
1.3
11 Nov 2019
Added detail to Appendix A –Alternate Reverse Build Variant

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Hardware User’s Guide
3 Introduction
The Qorvo 2x2 Small Cell RF Front-end 1.8GHz Card mates with the Xilinx Zynq UltraScale+ RFSoC
ZCU111 Evaluation Board, enabling direct RF-sampling radio prototype within the LTE 1800MHz frequency
band.
The ZCU111 has an XCZU28DR Zynq RFSoC device with eight 12-bit ADC’s that can operate up to 4GHZ
and eight 14-bit DAC’s that can operate up to 6.5GHz. The Qorvo uses 4 ADC channels and 2 DAC channels
in order to support a 2x2 configuration with observation paths for digital pre-distortion (DPD).
The Qorvo card (part # AES-LPA-QRF1800-G) may be purchased stand alone, or bundled in the Zynq®
UltraScale+™RFSoC Development Kit.
This document describes the features and use of the Qorvo RF card. For a description of the ZCU111, see
the User Guide, UG1271 [1].
Figure 1 –The Qorvo RF Card plugged into a Xilinx ZCU111 development board

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3.1 Zynq UltraScale+ RFSoC Development Kit
The Avnet Zynq UltraScale+ RFSoC Development Kit enables system architects to explore the
entire signal chain from antenna to digital using tools from MathWorks and industry-leading RF
components from Qorvo. We extend the functionality of the Xilinx Zynq UltraScale+ RFSoC
ZCU111 Evaluation Kit by adding a Qorvo 2x2 Small Cell RF front-end 1.8 GHz card for over-the-
air transmission, plus native connection to MATLAB® & Simulink® with Avnet's RFSoC Explorer®
application.
Figure 2 –Using the Avnet RFSoC Explorer tool for Matlab and Simulink

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3.2 Glossary
Term
Definition
ADC
Analog to Digital Converter
BAW
Bulk Acoustic Wave
BOM
Bill of Materials
CE
European Conformity marking
DAC
Digital to Analog Converter
dB
Decibel
DPD
Digital Pre-Distortion
DSA
Digital Step Attenuator
EEPROM
Electrically Erasable Programmable Read-only Memory
FCLK
Fabric Clock
FCC
Federal Communications Commission
FDD
Frequency Division Duplexing
GPIO
General Purpose Input / Output
I2C
Inter-Integrated Circuit interface
IC
Industry Canada (certification)
IPMI
Intelligent Platform Management Interface
LNA
Low Noise Amplifier
LTE
Long Term Evolution 4G telecommunications standard
PA
Power Amplifier
PL
Zynq UltraScale+ RFSoC Programmable Logic
PS
Zynq UltraScale+ RFSoC Processing System
RF
Radio Frequency
RFMC
RF Mezzanine Card
RFSoC
Radio Frequency System-on-Chip
RMS
Root Mean Square
Rx
Receive
SAM
Serial Addressable Mode
SPI
Serial Peripheral Interface
Tx
Transmit
TCL
Tool Command Language

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3.3 Reference Documents
[1] ZCU111 Evaluation Board User Guide
[2] AES-QRF1800-G Schematic for Qorvo 2x2 Small Cell RF Front-end 1.8GHz
[3] Xilinx Vivado Design Suite
[4] Xilinx Software Development Kit
[5] Zynq UltraScale+ RFSoC RF Data Converter 2.1 LogiCORE IP Product Guide (PG269)
[6] Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

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4 Architecture and Features
This section provides a summary of the board features.
4.1 List of Features
Two channels, each with Tx, Rx and DPD (Digital Pre Distortion) Observation path
Default tuning to LTE Band 3 / 1800 MHz FDD System
Alternate tuning options available as BOM variants
Transmit signal chain (2x):
oTQQ0303 - 1842.5 MHz RF BAW Filter
oTQL9092 - driver amplifier
oRFSA3713 - Digital Step Attenuator
oQPA9903 - 0.5 Watt High-Efficiency Linearizable Power Amplifier
oQPQ1297 - Band 3 BAW Duplexer
Receive signal chain (2x):
oQPQ1297 - Band 3 BAW Duplexer
oTQQ0302 - 1747.5 MHz RF BAW Filter - Band 3 Uplink
oTQP4M9017 - Fast Digital Step Attenuator
oRMS Power Detector
oQPL9096 - Ultra Low-Noise Bypass LNA

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4.2 Block Diagram
Figure 3 –Block Diagram

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5 Functional Description
The following sections provide brief descriptions of each feature provided on the board.
5.1 ZCU111 Interface
Two Samtec RFMC (RF Mezzanine Card) LPAM connectors on the Qorvo RF card plug into the
corresponding LPAF connectors on the ZCU111. These connectors carry the analog I/O
associated with RFSoC, as well as the digital control signals.
The diagram below illustrates how components inside the ZU28 are connected to the daughter card
via these LPAF/LPAM connectors.
Figure 4 –Controlling the Qorvo card from the RFSoC Processing System

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5.2 Digital Isolation
The ZCU111 has digital components running at high frequencies, while the Qorvo RF card may be
sensitive to minor disturbances. It is therefore desirable to isolate the ZCU111 from RF noise and
to isolate RF signals on the Qorvo card from digital noise sources.
There are a number of possible power configurations, as discussed under Power Options. When
the ZCU111 and Qorvo card are powered separately as in the diagram below, the digital ground
from the ZCU111, DGND, is not connected to the Qorvo card’s RF ground, RGND. Note that this
is not the factory default power configuration and that here external 5V to the Qorvo card
requires R140 and R141 to be removed.
The digital isolators used to achieve separation are the Texas Instruments devices:
ISO7140 (4 channels forward) and
ISO7141 (3 channels forward, 1 channel back).
The Qorvo attenuators use 5V logic. The isolators can level shift between 3V and 5V. Since the
ZCU111 Zynq banks used for digital I/O are configured for 1.8V, separate level translators are used
to convert the Zynq signals to/from 3.3V, while the isolators level shift between 3.3V and 5V.
Figure 5 –External 5V configuration and Isolators for Separate DGND and RGND Domains
Figure 6 –Example Level Translation and Digital Isolation

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5.3 Power Options
The power diagram in the previous section (Digital Isolation) is not the default configuration. It
shows the Qorvo card powered with an external 5V supply. For demonstrations and development
it is mostly convenient to not have a second power supply and to power the Qorvo card directly
from the ZCU111. This is the default configuration and in this case DGND and RGND are not
separated, but are connected through a resistor, R140, which must be removed for any the
“external power” configuration.
The diagram below shows the default configuration, where the Qorvo card is powered from the
ZCU111 and R140 and R141 are placed. Note that since DGND and RGND are connected, much
of the isolation is effectively lost. In this case 5V is generated by an on-board buck converter and
LDO.
Figure 7 –Factory Default Configuration with 12V from the ZCU111
It is also possible to power the Qorvo card stand-alone on the bench, from either 12V or 5V. The power
options all require various resistor configurations. The table on sheet 11 of the schematic [2] clearly
specifies which resistors need to be placed or removed for each option.
Figure 8 –Possible Power Configurations

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5.4 Attenuators Digital Step Attenuator (DSA) DevicesControl Interfaces
There are both parallel and serial Digital Step Attenuator (DSA) devices on this board.
5.4.1 Parallel DSA Control Interface
The two Rx attenuators are Qorvo TQP4M9071 devices.
https://www.qorvo.com/products/p/TQP4M9071
These devices can operate from DC to 4GHz. The TQP4M9071 has a 6-bit parallel interface where
one LSB presents 0.5dB of attenuation. A parallel control interface is much faster than a serial
interface. For procedures like Automatic Gain Control (AGC) it is important that there is a fast
response time and that the attenuation can be updated rapidly. This is why parallel attenuators are
being used in the receive path.
5.4.2 Serial DSA Control Interface
There are not enough GPIO available for a 6-bit interface to all 6 DSA’s. It is not as important to
change the attenuation in the Tx or DPD paths as it is for the receive path. Therefore the Tx and
DPD attenuators are the Qorvo RFSA3713 (https://www.qorvo.com/products/p/RFSA3713), which
uses a proprietary serial interface.
The RFSA3713 can operate from 5MHz to 6GHz. It is a 7-bit attenuator, where each step
represents 0.25dB of attenuation. The maximum clock rate for the serial control interface is 25MHz.
In the reference design this clock is 5MHz, and it is created by dividing down a 100MHz fabric clock
(FCLK) from the PS by 10 and then using this to run the state machine.
The serial interface used by the RFSA3713 is 3-wire “Serial Addressable Mode” (SAM). There is
a separate serial bus for each of the two channels and the address of the attenuator is specified by
the hard wiring on its address pins.
Figure 9 –Addressing and Timing for the Serial Addressable Mode Interface

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Figure 10 –Attenuator Control Interfaces

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The programmable logic and software in the Avnet reference design implements the serial protocol
for these attenuators. See 5.5.
The image below shows data being clocked out to one of the attenuators on the Channel 1 serial
bus. The serial clock here is 5MHz. The first signal, LE, is the latch enable signal, which toggles
after the serial data in (SI) has been clocked in.
Figure 11 –Scope Capture of SAM signals for Writing to an Attenuator

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5.5 Rebuilding the Reference Design
The Avnet reference design project for the Avnet RFSoC Kit is on GitHub. This reference design
is for the ZCU111 interfaced with the Qorvo card. It is a Vivado project that can be re-built from
sources in the online repository, using the instructions that are also in the repository.
The GitHub repository is at https://github.com/AvnetDev/qorvo1800
Note that the AvnetDev repository is not public. Developers may contact Avnet for access, i.e.
a user name and password.
Once access is granted by logging in, the content can be browsed or it can be cloned to a local
directory.
Under Linux the tip version of the repository can be cloned with:
git clone https://github.com/AvnetDev/qorvo1800.git
Under Windows the command to clone the tip version of the repository would be:
git clone git://github.com/AvnetDev/qorvo1800.git
For Windows it is important that a reasonably recent version of the Git executable is being used.
From a command prompt, the git version command can be used. At the time of this document,
the latest version is 2.22.0.
The latest version can be installed from https://git-scm.com/download/win.
At the time of this document, the latest code is in the “revB” directory and the build instructions are
in the file https://github.com/AvnetDev/qorvo1800/blob/master/revB/zcu111_build_instr.txt.
These instructions will direct the user to unzip the repository to a local directory and to then run the
TCL script from the TCL command window in Vivado. This will re-create and then build the project.
Figure 12 –GitHub Repository for the Avnet Reference Design

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.
5.6 SPI Controller
The programmable logic for controlling the attenuators, the power supply and the COMMS LED on
the daughter card has an SPI interface to the processor system. This allows user software in the
Zynq Processor System (PS) to access the Programmable Logic (PL) through AXI-4 to control the
DSA’s and other digital signals. This can be done through a serial port or, ultimately, from
MathWorks.
The Avnet reference design (see 5.5) software implementation uses the spidev Linux driver. The
Vivado project instantiates an axi_quad_spi component and the custom qorvo_spi component that
maps the interface to the control signals.
Figure 13 –The Qorvo Card SPI Interface in the Vivado Project
Most of the signals driven from this interface behave like typical GPIO in that the user can directly
drive them to logic ‘0’ or ‘1’ levels. There are two serial interfaces for the Tx and DPD attenuators
in the two channels though. This interface is not SPI, but a similar write-only interface called “Serial
Addressable Mode” (SAM). See 5.4.2.

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5.7 GPIO Assignments
There are 40 digital control signals available through RFMC LPAF connectors J47 and J94 on
ZCU111. They are the 1.8V ADCIO (20 signals on J47) and DACIO (20 signals on J94) lines from
the RFSoC ZU+ device.
The table below shows how the GPIO pins have been assigned. Note that the Zynq firmware pin
number assignments can be found in the Vivado project file qorvo_spi_slave.xdc.This file can
be found in the Avnet reference design (see 5.5) inside the pl\qorvo1800\revB\src folder.
Table 1 –Assignments for Digital GPIO from the ZCU111
ZCU111
Signal
Zynq
Pin #
ZCU111
LPAF Pin
Qorvo Card Signal
Qorvo Card
Test Pin
Description
DACIO_00
A9
J94 pin A37
I2C_ SCLX
J5 pin 3
I2C clock for EEPROM
DACIO_01
A10
J94 pin A39
I2C_ SDAX
J5 pin 2
I2C data for EEPROM
DACIO_02
A6
J94 pin B36
CH1_RX_LNA0_BYPX
J1 pin 13
Ch1 Rx LNA0 Bypass
DACIO_03
A7
J94 pin B38
CH1_RX_LNA1_BYPX
J1 pin 14
Ch1 Rx LNA1 Bypass
DACIO_04
A5
J94 pin B40
CH1_RX_LNA0_DISX
J1 pin 15
Ch1 Rx LNA0 Disable
DACIO_05
B5
J94 pin C37
CH1_RX_LNA0_ENX
J1 pin 16
Ch1 Rx LNA0 Enable
DACIO_06
C5
J94 pin C39
CH1_RX_OVX
Ch1 Rx Over-voltage
DACIO_07
C6
J94 pin D36
CH1_TX_PA_ENX
J1 pin 11
Ch1 Tx PA Enable
DACIO_08
B9
J94 pin D38
CH1_RX_LNA1_DISX
J1 pin 17
Ch1 Rx LNA1 Disable
DACIO_09
B10
J94 pin D40
CH1_TX_LNA_DISX
J1 pin 12
Ch1 Tx LNA Disable
DACIO_10
B7
J94 pin E37
CH1_LEX
J1 pin 2
Ch1 Tx and DPD DSA Serial Latch Enable
DACIO_11
B8
J94 pin E39
CH1_CLKX
J1 pin 3
Ch1 Tx and DPD DSA Serial Clock
DACIO_12
D8
J94 pin F36
CH1_SIX
J1 pin 4
Ch1 Tx and DPD DSA Serial Data
DACIO_13
D9
J94 pin F38
CH1_RX_DSA_D0X
J1 pin 5
Ch2 Rx DSA Data bit 0
DACIO_14
C7
J94 pin F40
CH1_RX_DSA_D1X
J1 pin 6
Ch2 Rx DSA Data bit 1
DACIO_15
C8
J94 pin G37
CH1_RX_DSA_D2X
J1 pin 7
Ch2 Rx DSA Data bit 2
DACIO_16
C10
J94 pin G39
CH1_RX_DSA_D3X
J1 pin 8
Ch2 Rx DSA Data bit 3
DACIO_17
D10
J94 pin H36
CH1_RX_DSA_D4X
J1 pin 9
Ch2 Rx DSA Data bit 4
DACIO_18
D6
J94 pin H38
CH1_RX_DSA_D5X
J1 pin 10
Ch2 Rx DSA Data bit 5
DACIO_19
E7
J94 pin H40
TP7
Spare
ADCIO_00
AP5
J47 pin A2
COMMS_LEDX
J6 pin 18
Yellow LED control
ADCIO_01
AP6
J47 pin A4
TP8
Spare
ADCIO_02
AR6
J47 pin B1
CH2_RX_LNA0_BYPX
J6 pin 13
Ch2 Rx LNA0 Bypass

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ZCU111
Signal
Zynq
Pin #
ZCU111
LPAF Pin
Qorvo Card Signal
Qorvo Card
Test Pin
Description
ADCIO_03
AR7
J47 pin B3
CH2_RX_LNA1_BYPX
J6 pin 14
Ch2 Rx LNA1 Bypass
ADCIO_04
AV7
J47 pin B5
CH2_RX_LNA0_DISX
J6 pin 15
Ch2 Rx LNA0 Disable
ADCIO_05
AU7
J47 pin C2
CH2_RX_LNA0_ENX
J6 pin 16
Ch2 Rx LNA0 Enable
ADCIO_06
AV8
J47 pin C4
CH2_RX_OVX
Ch2 Rx Over-voltage
ADCIO_07
AU8
J47 pin D1
CH2_TX_PA_ENX
J6 pin 11
Ch2 Tx PA Enable
ADCIO_08
AT6
J47 pin D3
CH2_RX_LNA1_DISX
J6 pin 17
Ch2 Rx LNA1 Disable
ADCIO_09
AT7
J47 pin D5
CH2_TX_LNA_DISX
J6 pin 12
Ch2 Tx LNA Disable
ADCIO_10
AU5
J47 pin E2
CH2_LEX
J6 pin 2
Ch2 Tx and DPD DSA Serial Latch Enable
ADCIO_11
AT5
J47 pin E4
CH2_CLKX
J6 pin 3
Ch2 Tx and DPD DSA Serial Clock
ADCIO_12
AU3
J47 pin F1
CH2_SIX
J6 pin 4
Ch2 Tx and DPD DSA Serial Data
ADCIO_13
AU4
J47 pin F3
CH2_RX_DSA_D0X
J6 pin 5
Ch2 Rx DSA Data bit 0
ADCIO_14
AV5
J47 pin F5
CH2_RX_DSA_D1X
J6 pin 6
Ch2 Rx DSA Data bit 1
ADCIO_15
AV6
J47 pin G2
CH2_RX_DSA_D2X
J6 pin 7
Ch2 Rx DSA Data bit 2
ADCIO_16
AU1
J47 pin G4
CH2_RX_DSA_D3X
J6 pin 8
Ch2 Rx DSA Data bit 3
ADCIO_17
AU2
J47 pin H1
CH2_RX_DSA_D4X
J6 pin 9
Ch2 Rx DSA Data bit 4
ADCIO_18
AV2
J47 pin H3
CH2_RX_DSA_D5X
J6 pin 10
Ch2 Rx DSA Data bit 5
ADCIO_19
AV3
J47 pin H5
TP9
Spare

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5.8 EEPROM and I2C Interface
U66 on the Qorvo card is 1Kbit EEPROM from Microchip. It uses a 2-wire I2C interface. The
purpose of this device is to store a board ID so that software can distinguish this board from other
daughter card. It would also be possible to store a device ID and/or calibration parameters that are
unique to a specific board’s serial number.
Currently this functionality has not been implemented yet.
Avnet has Intelligent Platform Management Interface (IPMI) EEPROMs for identification on some
boards. Inside the Avnet reference design (see 5.5), the RFTOOL codebase includes modules for
I2C communication.
I2C can be accessed from the ZCU111 through the LPAM/LPAF connectors. During production
the EEPROM can also be programmed from the I2C test header, J5.
Table 2 –I2C Header J5 Pin Assignments
Pin #
Signal
Description
1
VBUS_1V8
1.8V
2
I2C_ SDAX
I2C data
3
I2C_ SCLX
I2C clock
4
DGND
Digital Ground
Figure 14 –The I2C Test Header