Avnet UltraZed-EG Installation manual

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UltraZed-EG SOM
Hardware User Guide
Version 1.0

Version 1.0 Page 2
Document Control
Document Version:
Version 1.0
Document Date:
December 7, 2016
Document Author(s):
Donny Saveski
Document Classification:
Public
Document Distribution:
Public
Prior Version History:
Version:
Date:
Comment:
1.0
12/7/16
Initial Release
Comments:

Version 1.0 Page 3
Contents
1Introduction ...........................................................................................................5
2Functional Description...........................................................................................7
2.1 Zynq UltraScale+ MPSoC........................................................................................................ 7
2.2 Memory.................................................................................................................................... 7
2.2.1 DDR4................................................................................................................................... 7
2.2.2 Dual Parallel (x8) QSPI Flash.............................................................................................. 9
2.2.3 eMMC x8 Flash (Multi-Media Controller)........................................................................... 10
2.2.4 SFVA625 Device Package Delay Compensation for Memory Interfaces ......................... 11
2.3 GTR Transceivers.................................................................................................................. 11
2.3.1 SFVA625 Device Package Delay Compensation for GTR Transceiver Interface............. 12
2.4 USB 2.0 OTG......................................................................................................................... 12
2.4.1 SFVA625 Device Package Delay Compensation for USB2.0 Interface............................ 13
2.5 10/100/1000 Ethernet PHY.................................................................................................... 14
2.5.1 Ethernet PHY Strapping Resistors .................................................................................... 15
2.5.2 Ethernet PHY LEDs........................................................................................................... 16
2.5.3 SFVA625 Device Package Delay Compensation for 10/100/1000 Ethernet Interface...... 16
2.6 I2C I/O Expander................................................................................................................... 17
2.7 I2C Switch/Multiplexer........................................................................................................... 18
2.7.1 End-User Carrier Card I2C Interface................................................................................. 19
2.7.2 PMBUS Interface............................................................................................................... 20
2.8 I2C EEPROM......................................................................................................................... 21
2.9 PS General Purpose Interrupt ............................................................................................... 21
2.10 User I/O.................................................................................................................................. 21
2.10.1 PS MIO User Pins.............................................................................................................. 21
2.10.2 PL IO User Pins................................................................................................................. 22
2.11 Clock Sources........................................................................................................................ 22
2.12 Control Signal Sources.......................................................................................................... 23
2.12.1 Power-On Reset (PS_POR_N) and Carrier Card Reset (CC_RESET_OUT_N).............. 23
2.12.2 PS_PROG_B, PS_DONE, PS_INIT_B, PUDC_B, POR_OVERRIDE, and ERROR........ 23
2.12.3 Processor Subsystem Reset (PS_SRST_B) and SOM Reset (SOM_RESET_IN_N) ...... 24
2.13 Expansion Headers ............................................................................................................... 24
2.13.1 Micro Headers ................................................................................................................... 24
2.13.2 JX Connector Master Table............................................................................................... 26
2.13.3 Powering the PL Banks (SOM_PG_OUT)......................................................................... 32
2.14 Configuration Modes.............................................................................................................. 32
2.14.1 JTAG Connections............................................................................................................. 33

Version 1.0 Page 4
2.15 Power Supplies...................................................................................................................... 34
2.15.1 Voltage Rails and Sources ................................................................................................ 34
2.15.2 Voltage Regulators ............................................................................................................ 36
2.15.3 Power Supply Sequencing and Power Modes .................................................................. 37
2.15.4 PCB Bypass / Decoupling Strategy................................................................................... 40
2.15.5 Power Estimation............................................................................................................... 41
2.15.6 System Monitor (SYSMON)............................................................................................... 41
2.15.7 Battery Backup –Device Secure Boot Encryption Key..................................................... 42
2.15.8 Thermal Management: Heatsink and Fan Assembly ........................................................ 43
3Zynq UltraScale+ MPSoC I/O Bank Allocation....................................................44
3.1 PS MIO Bank Allocation ........................................................................................................ 44
3.2 Zynq UltraScale+ MPSoC Bank Voltages ............................................................................. 45
4Mechanical..........................................................................................................46

Version 1.0 Page 5
1 Introduction
The UltraZed™-EG SOM (System-On Module) is a low cost System-On-Module targeted for broad use in
many applications. The features provided by the UltraZed-EG System-On-Module consist of:
Xilinx XCZU3EG-1SFVA625 MPSoC
oPin Compatible with the 2EG, 2CG, and 3CG MPSoC devices in the same package
oPrimary configuration Options = eMMC or QSPI Flash
oAuxiliary primary configuration options via End User Carrier Card
JTAG
microSD Card
Memory
oDDR4 SDRAM (2GB, x32)
oDual QSPI Flash (64MB)
oeMMC Flash (8GB, x8)
oI2C EEPROM (2Kb)
Interfaces
oGigabit Ethernet PHY (Connector required on End User Carrier Card)
oUSB 2.0 ULPI PHY (Connector required on End User Carrier Card)
oOne 100-pin JX Micro Header
oTwo 140-pin JX Micro Headers
oI2C I/O Expander
oTwo Channel I2C Switch/MUX
PS Reference Clock Input
o33.333 MHz OSC
Power
oOn-Board 5-Output Voltage Regulators
oFull Power Sequencing Pre-Programmed
oSupport for Zynq UltraScale+® PS Low Power Mode
oBank I/O Voltage Rails and GTR Transceiver Voltage Rails are powered from End User
Carrier Card via JX Micro Headers
Pertinent URLs
oSOM: http://ultrazed.org/product/ultrazed-EG
oStarter Kit: http://ultrazed.org/product/ultrazed-eg-starter-kit
oCarrier Card: http://ultrazed.org/product/ultrazed-io-carrier-card
Figure 1 –UltraZed-EG SOM 3D Views

Version 1.0 Page 6
The following figure is a high level block diagram of the UltraZed-EG SOM and the peripherals attached to
the Zynq UltraScale+ MPSoC Processing Sub-System and Programmable Logic Sub-System.
MIO[0:12]
I2C –MIO[24:25]
MIO[26:51]
MIO[52:63]
MIO[64:77]
GTR[0:3]
GTR_Ref_CLK[0:3]
HP I/O (90)
JTAG (4)
SYSMON (4)
140-Pin Connector (JX1)
Signal(90), GND(37), VCCO(6),
VIN(3), JTAG(4)
140-Pin Connector (JX2)
Signal(90), GND(31), VCCO(6),
VIN(3), SYSMON(4), PMBus(3),
SOM_RESET_IN, CC_RESET_OUT,
SOM_PG_OUT
VoltageRegulators
Input: 5 –12V
Outputs:
0.6V, 0.85V, 1.0V, 1.2V,
1.25V,1.8V, 2.5V, 3.3V
100-Pin Connector (JX3)
Signal(65), GND(19),
GTRAVCC(3), GTRAVTT(2),
Sense(6), PS_VBATT,
CC_SDA, CC_SCL, CC_INT,
VCCO_PSIO_501
DDR4
(2GB, x32)
Dual QSPI
(64MB)
USB 2.0
ULPI PHY
Ethernet
RGMII PHY
MIO[13:22]
eMMC
(8GB, x8)
26
5
10
16
8
HP I/O (66)
HD I/O (24)
INT –MIO[23]
PMBus (3)
2-Channel
I2C Switch/Mux To PMBus
Regulators
SD1/SC1
SD0/SC0/INT0
SDA/SCL Zynq UltraScale+
ZU3EG-SFVA625
PS-Side PL-Side
I2C 8-Bit
I/O Expander
I2C EEPROM
(2Kb)
3
Figure 2 –UltraZed-EG SOM Block Diagram

Version 1.0 Page 7
2 Functional Description
2.1 Zynq UltraScale+ MPSoC
The UltraZed-EG SOM includes a Xilinx Zynq UltraScale+ MPSoC. The devices capable of being populated
on the UltraZed-EG SOM are the XCZU2EG-1SFVA625 or XCZU3EG-1SFVA625 MPSoC. The UltraZed-
EG SOM also supports the 2CG and 3CG MPSoC device as well as both extended and industrial
temperature grade options as well as all of the speed grade options offered by Xilinx.
NOTE: Please contact your local Avnet FAE in regards to currently available options or custom
device options for the UltraZed-EG SOM.
2.2 Memory
Zynq UltraScale+ contains a hardened PS memory interface unit. The memory interface unit includes a
dynamic memory controller and static memory interface modules. The UltraZed-EG SOM takes advantage
of these interfaces to provide system RAM as well as two different non-volatile memory sources.
2.2.1 DDR4
The UltraZed-EG SOM includes two Micron MT40A512M16JY-083E IT:B (96-pin BGA package) DDR4
memory components creating a 512M x 32-bit interface, totalling 2 GB of random access memory. The
DDR4 memory is connected to the hard memory controller in the PS of the Zynq UltraScale+ MPSoC via its
Bank 504 PS Memory Interface. The Bank 504 PS Memory Interface incorporates both the DDR controller
and the associated PHY, including its own set of IOs.
Speeds of up to 2,133 Mbps for DDR4 is supported. The DDR4 interface is designed to use 1.2V SSTL-
compatible inputs.
DDR4 Termination is utilized on the UltraZed-EG SOM and configured for fly-by routing topology.
Additionally the board trace lengths are matched, compensating for the internal package flight times of the
Zynq UltraScale+ MPSoC SFVA625 package, to meet the requirements listed in the Xilinx PCB Design and
Pin Planning Guide (UG583).
All single-ended signals are routed with 50 ohm trace impedance. Differential signals are set to 90 ohms
trace impedance. Several signals are terminated through 40 ohms resistors to +DDR4_VTT. Each DDR4
chip has its own 240-ohm pull-down on ZQ.
NOTE: +DDR4_VREF is not the same as +DDR4_VTT.

Version 1.0 Page 8
DDR4 SDRAM
(1GB)
MT40A512M16JY-083E IT:B
Data Group
Bank 504
Data Group DDR4 SDRAM
(1GB)
MT40A512M16JY-083E IT:B
Fly-byRouting
Address/Control Group
TPS51200 VREF
VREF
VREF
VTT
Figure 3 –DDR4 Block Diagram
Table 1 –DDR4 Connections
Signal Name
Description
Bank 504 MPSoC Pin
DDR4 Pin
PS_DDR_A0
DDR Address Input
U25
P3
PS_DDR_A1
DDR Address Input
Y25
P7
PS_DDR_A2
DDR Address Input
AB25
R3
PS_DDR_A3
DDR Address Input
AA25
N7
PS_DDR_A4
DDR Address Input
V25
N3
PS_DDR_A5
DDR Address Input
AC25
P8
PS_DDR_A6
DDR Address Input
W21
P2
PS_DDR_A7
DDR Address Input
AB22
R8
PS_DDR_A8
DDR Address Input
Y20
R2
PS_DDR_A9
DDR Address Input
AA20
R7
PS_DDR_A10
DDR Address Input
AB23
M3
PS_DDR_A11
DDR Address Input
AD24
T2
PS_DDR_A12
DDR Address Input
AC23
M7
PS_DDR_A13
DDR Address Input
AE24
T8
PS_DDR_A14
DDR Address / RAS Input
AC24
L2
PS_DDR_A15
DDR Address / CAS Input
AD23
M8
PS_DDR_A16
DDR Address / WE_N Input
Y21
L8
PS_DDR_BA0
DDR Bank Address Inputs
W22
N2
PS_DDR_BA1
DDR Bank Address Inputs
V20
N8
PS_DDR_BG0
DDR Bank Group Address Inputs
V19
M2
PS_DDR_CKE0
DDR Clock Enable Input
T24
K2
PS_DDR_CK0_P
DDR Clock Device 0 Pair
AA23
K7
PS_DDR_CK0_N
DDR Clock Device 0 Pair
AA24
K8
PS_DDR_CS0_N
DDR Chip Select Input
T25
L7
PS_DDR_ACT_N
DDR Activate Command Input
V18
L3
PS_DDR_ALERT_N
DDR Alert Output
U23
P9
PS_DDR_ODT0
DDR On-Die Termination
V24
K3
PS_DDR_PARITY
DDR Command/Address Parity
V23
T3
PS_DDR_RAM_RST_N
DDR Active Low Reset Input
U21
P1
PS_DDR_ZQ
ZQ Calibration Reference
U22
F9
PS_DDR_DQ0
DDR Data Byte 0
AB15
U24-G2
PS_DDR_DQ1
DDR Data Byte 0
AE15
U24-F7
PS_DDR_DQ2
DDR Data Byte 0
AC15
U24-H3
PS_DDR_DQ3
DDR Data Byte 0
AE14
U24-H7
PS_DDR_DQ4
DDR Data Byte 0
AD13
U24-H2
PS_DDR_DQ5
DDR Data Byte 0
AC13
U24-H8
PS_DDR_DQ6
DDR Data Byte 0
AB13
U24-J3
PS_DDR_DQ7
DDR Data Byte 0
AA13
U24-J7

Version 1.0 Page 9
NOTE: (U24 or U25 indicates DDR4 Device Reference Designator)
2.2.2 Dual Parallel (x8) QSPI Flash
The UltraZed-EG SOM features two 4-bit SPI (quad-SPI) serial NOR flash devices organized in a dual
parallel configuration. The Micron MT25QU256ABAIEW7-0SIT QSPI Flash devices are used on the
UltraZed-EG SOM. The Multi-I/O SPI Flash memory is used to provide non-volatile boot, application code,
and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem
(bitstream).
The Quad-SPI Flash connects to the Zynq UltraScale+ MPSoC PS QSPI interface. This requires connection
to specific pins in MIO Bank 500, specifically MIO[0:12] as outlined in the Zynq UltraScale+ TRM (Technical
Reference Manual, UG1085). Quad-SPI feedback mode is used, thus the CLK_FOR_LPBK signal tied to
MIO[6] is left floating. This allows a QSPI clock frequency greater than FQSPICLK2.
The Zynq UltraScale+ MPSoC peripheral used to control the QSPI flash devices is named QSPI. The
QSPI devices can be operated up to 166MHz depending on the operating mode and the possible
performance of the QSPI controller in the MPSoC. The QSPI flash devices are physically connected to the
QSPI controller in the PS of the Zynq UltraScale+ MPSoC via Bank 500.
PS_DDR_DM0
DDR Data Byte 0 Data Mask
AA14
U24-E7
PS_DDR_DQS0_P
DDR Data Byte 0 Data Strobe Pair
AC14
U24-G3
PS_DDR_DQS0_N
DDR Data Byte 0 Data Strobe Pair
AD14
U24-F3
PS_DDR_DQ8
DDR Data Byte 1
AC16
U24-A3
PS_DDR_DQ9
DDR Data Byte 1
AB16
U24-B8
PS_DDR_DQ10
DDR Data Byte 1
AD16
U24-C3
PS_DDR_DQ11
DDR Data Byte 1
AE16
U24-C7
PS_DDR_DQ12
DDR Data Byte 1
AE19
U24-C2
PS_DDR_DQ13
DDR Data Byte 1
AD18
U24-C8
PS_DDR_DQ14
DDR Data Byte 1
AB18
U24-D3
PS_DDR_DQ15
DDR Data Byte 1
AC18
U24-D7
PS_DDR_DM1
DDR Data Byte 1 Data Mask
AB17
U24-E2
PS_DDR_DQS1_P
DDR Data Byte 1 Data Strobe Pair
AD17
U24-B7
PS_DDR_DQS1_N
DDR Data Byte 1 Data Strobe Pair
AE17
U24-A7
PS_DDR_DQ16
DDR Data Byte 2
W18
U25-G2
PS_DDR_DQ17
DDR Data Byte 2
Y19
U25-F7
PS_DDR_DQ18
DDR Data Byte 2
AA19
U25-H3
PS_DDR_DQ19
DDR Data Byte 2
W16
U25-H7
PS_DDR_DQ20
DDR Data Byte 2
AA18
U25-H2
PS_DDR_DQ21
DDR Data Byte 2
AA15
U25-H8
PS_DDR_DQ22
DDR Data Byte 2
Y16
U25-J3
PS_DDR_DQ23
DDR Data Byte 2
Y15
U25-J7
PS_DDR_DM2
DDR Data Byte 2 Data Mask
W17
U25-E7
PS_DDR_DQS2_P
DDR Data Byte 2 Data Strobe Pair
Y17
U25-G3
PS_DDR_DQS2_N
DDR Data Byte 2 Data Strobe Pair
AA17
U25-F3
PS_DDR_DQ24
DDR Data Byte 3
AE20
U25-A3
PS_DDR_DQ25
DDR Data Byte 3
AD19
U25-B8
PS_DDR_DQ26
DDR Data Byte 3
AB20
U25-C3
PS_DDR_DQ27
DDR Data Byte 3
AC19
U25-C7
PS_DDR_DQ28
DDR Data Byte 3
AE21
U25-C2
PS_DDR_DQ29
DDR Data Byte 3
AB21
U25-C8
PS_DDR_DQ30
DDR Data Byte 3
AE22
U25-D3
PS_DDR_DQ31
DDR Data Byte 3
AD22
U25-D7
PS_DDR_DM3
DDR Data Byte 3 Data Mask
AD21
U25-E2
PS_DDR_DQS3_P
DDR Data Byte 3 Data Strobe Pair
AC20
U25-B7
PS_DDR_DQS3_N
DDR Data Byte 3 Data Strobe Pair
AC21
U25-A7
+DDR4_VREF
DDR Reference voltage
-
VREFCA
+DDR4_VTT
DDR Termination voltage
-
-

Version 1.0 Page 10
SPI FLASH MEMORY UPPER
(256Mb)
MT25QU256ABAIEW7-0SIT
Bank 500
SPI FLASH MEMORY LOWER
(256Mb)
MT25QU256ABAIEW7-0SIT
QSPI1_IO[:3]
QSPI0_IO[0:3]
QSPI1_SCLK
QSPI0_SCLK
QSPI0_SS_B
QSPI1_SS_B
Figure 4 –Dual QSPI Block Diagram
Table 2 –Quad-SPI Flash Pin Assignment and Definitions
NOTE: (U2 or U3 indicates QSPI Device Reference Designator)
2.2.3 eMMC x8 Flash (Multi-Media Controller)
The UltraZed-EG SOM features a Micron MTFC8GAKAJCN-4M IT eMMC Multi Media Controller and NAND
Flash IC. The eMMC is used to provide non-volatile user data storage and/or primary or secondary boot
storage.
The relevant device attributes are:
8GB (default) - Optional densities available via customization
Industrial temperature range (-40C to +85C)
8-bit data interface
The Zynq UltraScale+ MPSoC peripheral used to control the eMMC flash device is named SD0. The eMMC
flash device can be operated up to 52MHz and is physically connected to the PS of the Zynq UltraScale+
MPSoC via Bank 500. The eMMC I/O has direct connections to the Zynq UltraScale+ MIO through the
PS_MIO [13:22] pins.
The UltraZed-EG SOM end-user is capable of issuing a soft reset, P0_EMMC0_RST_N, to the eMMC
flash device via an on board two-wire serial interface. The active low reset is assigned to Port 0 of the
Texas Instruments TCA9534 I/O expander. The I/O expander is attached to an I2C peripheral on the Zynq
Signal Name
Description
MPSoC Pin
MIO
Quad-SPI Pin
MIO0_QSPI0_SCLK
Lower QSPI Serial Clock
V10
MIO 0
U2-6
MIO1_QSPI0_IO1
Lower QSPI Data [1]
W11
MIO 1
U2-2
MIO2_QSPI0_IO2
Lower QSPI Data [2]
V11
MIO 2
U2-3
MIO3_QSPI0_IO3
Lower QSPI Data [3]
W9
MIO_3
U2-7
MIO4_QSPI0_IO0
Lower QSPI Data [0]
Y9
MIO_4
U2-5
MIO5_QSPI0_SS_B
Lower QSPI Select
AA10
MIO_5
U2-1
FLOAT (NC)
Loopback Clock
Y10
MIO_6
-
MIO7_QSPI1_SS_B
Upper QSPI Select
Y11
MIO_7
U3-1
MIO8_QSPI1_IO0
Upper QSPI Data [0]
AC10
MIO_8
U3-5
MIO9_QSPI1_IO1
Upper QSPI Data [1]
AB10
MIO_9
U3-2
MIO10_QSPI1_IO2
Upper QSPI Data [2]
W12
MIO_10
U3-3
MIO11_QSPI1_IO3
Upper QSPI Data [3]
AE10
MIO_11
U3-7
MIO12_QSPI1_SCLK
Upper QSPI Serial Clock
AB11
MIO_12
U3-6

Version 1.0 Page 11
UltraScale+ device. For further information on the I/O expander and its connections, please locate the I/O
expander section within this hardware user guide.
eMMC FLASH MEMORY
(8GB)
MTFC8GAKAJCN-4M IT
Bank 500
MIOxx_EMMC0_IO[0:7]
MIO22_EMMC0_CLK
P0_EMMC0_RST_N
MIO21_EMMC0_CMD
I/O
EXPANDER
TCA9534
Figure 5 –eMMC Block Diagram
Table 3 –eMMC Pin Assignment and Definitions
Signal Name
Description
MPSoC Pin
MIO
eMMC Pin
MIO13_EMMC0_IO0
EMMC Data IO [0]
Y12
MIO_13
A3
MIO14_EMMC0_IO1
EMMC Data IO [1]
AC11
MIO_14
A4
MIO15_EMMC0_IO2
EMMC Data IO [2]
W13
MIO_15
A5
MIO16_EMMC0_IO3
EMMC Data IO [3]
V13
MIO_16
B2
MIO17_EMMC0_IO4
EMMC Data IO [4]
AD11
MIO_17
B3
MIO18_EMMC0_IO5
EMMC Data IO [5]
AB12
MIO_18
B4
MIO19_EMMC0_IO6
EMMC Data IO [6]
AE11
MIO_19
B5
MIO20_EMMC0_IO7
EMMC Data IO [7]
AA12
MIO_20
B6
MIO21_EMMC0_CMD
EMMC Command
AD12
MIO_21
M5
MIO22_EMMC0_CLK
EMMC Clock
W14
MIO_22
M6
NOTE: EMMC18 Boot Mode: MODE PINS [3:0] –0x6
2.2.4 SFVA625 Device Package Delay Compensation for Memory Interfaces
The Zynq UltraScale+ MPSoC device package delay is accommodated for in the layout of the each of the
memory interfaces signal trace lengths. The average of min and max values for package delay is utilized
to compensate for the flight time caused by the delay associated with this package.
2.3 GTR Transceivers
The UltraZed-EG SOM has four multi-gigabit transceiver lanes that reside on Bank 505 of the Zynq
UltraScale+ MPSoC device. These transceivers can be used to interface to multiple high speed interface
protocols such as PCI Express, Serial ATA, USB3.0, and Display Port. The associated high speed protocol
MAC layers are hardened macros that exist in the PS subsystem of the Zynq UltraScale+ MPSoC device
so additional Intellectual Property (IP) or targeted devices are not necessary to complete the various
interfaces.
The Zynq UltraScale+ MPSoC is enabled with four GTR transceivers which are capable of a transceiver
data rates up to 6.0 Gbps. Four differential MGT reference clock inputs are available to support the GTR
transceiver lanes. The multi-gigabit transceiver lanes and their associated reference clocks are connected
to the end-user carrier board via the JX3 Micro Header.

Version 1.0 Page 12
The UltraZed-EG SOM is capable of implementing up to a PCIe x4 interface as the physical design of the
GTRs are each length tuned from the Zynq UltraScale+ MPSoC device to the JX3 connector taking into
account the device package delays. The MPSoC device net length report provided by Xilinx and the PCB
net length report provided by Avnet can be used to determine the required delay for each implemented
interface on the end-user carrier card.
The table below shows the connections between the Zynq UltraScale+ MPSoC device and the JX3 Micro
Header.
Table 4 –Bank 505 GTR Pin Assignments
PS IO NAME
PACKAGE PIN NUMBER
NET NAME
JX3 CONNECTOR
PS_MGTRRXN0_505
M25
GTR_RX0_N
JX3.28
PS_MGTRRXN1_505
H25
GTR_RX1_N
JX3.20
PS_MGTRRXN2_505
D25
GTR_RX2_N
JX3.12
PS_MGTRRXN3_505
B25
GTR_RX3_N
JX3.6
PS_MGTRRXP0_505
M24
GTR_RX0_P
JX3.26
PS_MGTRRXP1_505
H24
GTR_RX1_P
JX3.18
PS_MGTRRXP2_505
D24
GTR_RX2_P
JX3.10
PS_MGTRRXP3_505
B24
GTR_RX3_P
JX3.4
PS_MGTRTXN0_505
K25
GTR_TX0_N
JX3.23
PS_MGTRTXN1_505
F25
GTR_TX1_N
JX3.15
PS_MGTRTXN2_505
C23
GTR_TX2_N
JX3.9
PS_MGTRTXN3_505
A23
GTR_TX3_N
JX3.3
PS_MGTRTXP0_505
K24
GTR_TX0_P
JX3.21
PS_MGTRTXP1_505
F24
GTR_TX1_P
JX3.13
PS_MGTRTXP2_505
C22
GTR_TX2_P
JX3.7
PS_MGTRTXP3_505
A22
GTR_TX3_P
JX3.1
PS_MGTREFCLK0N_505
L23
GTR_REFCLK0_N
JX3.40
PS_MGTREFCLK0P_505
L22
GTR_REFCLK0_P
JX3.38
PS_MGTREFCLK1N_505
J23
GTR_REFCLK1_N
JX3.35
PS_MGTREFCLK1P_505
J22
GTR_REFCLK1_P
JX3.33
PS_MGTREFCLK2N_505
G23
GTR_REFCLK2_N
JX3.34
PS_MGTREFCLK2P_505
G22
GTR_REFCLK2_P
JX3.32
PS_MGTREFCLK3N_505
E23
GTR_REFCLK3_N
JX3.29
PS_MGTREFCLK3P_505
E22
GTR_REFCLK3_P
JX3.27
PS_MGTRREF_505
K22
GTR_RREF
-
2.3.1 SFVA625 Device Package Delay Compensation for GTR Transceiver Interface
The Zynq UltraScale+ MPSoC device package delay is accommodated for in the layout of the each of the
GTR transceiver signal trace lengths. The average of min and max values for package delay is utilized to
compensate for the flight time caused by the delay associated with this package.
2.4 USB 2.0 OTG
The Zynq UltraScale+ MPSoC contains a hardened PS USB 2.0 controller. The UltraZed-EG SOM takes
advantage of one of the two available PS USB 2.0 controllers to provide USB 2.0 On-The-Go signalling to
the JX3 connector.
An external PHY with an 8-bit ULPI interface is implemented. A Microchip USB3320 Standalone USB
Transceiver Chip is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting
speeds of up to 480Mbs. VDDIO for this device can be 1.8V or 3.3V, and on the UltraZed-EG SOM VDDIO
is powered at 1.8V. The PHY is connected to MIO Bank 502 which is also powered at 1.8V. This is critical

Version 1.0 Page 13
since a level translator cannot be used as it would impact the ULPI timing between the PHY and the Zynq
UltraScale+ MPSoC device.
Additionally, the USB3320 must clock the ULPI interface which requires a 24 MHz crystal or oscillator
(configured as ULPI Output Clock Mode). On the UltraZed-EG SOM, the 24 MHz oscillator is an Abracon
ASDMB CMOS oscillator, ASDMB-24.000MHZ-LY-T.
The physical USB connector is not populated on the UltraZed-EG SOM. The SOM is designed to have the
physical USB connector reside on the end-user carrier card. The four USB connector signals
(USB_OTG_P, USB_OTG_N, USB_ID and USB_OTG_CPEN) and USB_OTG_VBUS are connected to
the JX3 Micro Header. The table below shows the connections of these signals at JX3.
Table 5 –USB 2.0 JX3 Pin Assignments
Signal Name
JX3 Pin
USB_OTG_N
47
USB_OTG_P
45
USB_ID
51
USB_OTG_CPEN
48
USB_OTG_VBUS
50
The USB0 peripheral is used on the PS, connected through MIO [52-63] in MIO Bank 502. The USB Reset
signal is active-low and connected to the I/O expander via Port 1, P1_USB0_RST_N. Either of the push
button resets, PS_POR_B or PS_SRST_B will also generate the active-low USB Reset signal.
The UltraZed-EG SOM, with additional circuitry on an end-user carrier card, can be configured to operate
in Host Mode (OTG) or Device Mode. With a standard connection to an end-user carrier card (no power
supply used to provide USB power to the connector) the device will operate in Device Mode. Using the
USB_OTG_CPEN signal on JX3 allows the user to control an external power source for USB_OTG_VBUS
on the end-user carrier card. Other considerations need to be made to accommodate Host Mode. Refer to
the Avnet UltraZed-EG I/O Carrier Card design for an example design for configuring the end-user carrier
card for either Host Mode or Device Mode.
Table 6 –USB 2.0 Pin Assignment and Definitions
Signal Name
Description
MPSoC Bank
MIO
USB3320 Pin
DATA[7:0]
USB Data lines
MIO Bank 502
52:63
D[7:0]
CLKOUT
USB Clock
MIO Bank 502
1
DIR
ULPI DIR output signal
MIO Bank 502
31
STP
ULPI STP input signal
MIO Bank 502
29
NXT
ULPI NXT output signal
MIO Bank 502
2
REFSEL[2:0]
USB Chip Select
N/C
N/C
8,11,14
DP
DP pin of USB Connector
18
DM
DM pin of USB Connector
19
ID
Identification pin of the USB
connector
23
RESET_B
Active-Low Reset
MIO Bank 502
N/C
27**
NOTE: ** Connected through AND-gates with PS_POR_B, PS_SRST_B, and
P1_USB0_RST_N from the I/O expander
2.4.1 SFVA625 Device Package Delay Compensation for USB2.0 Interface
The Zynq UltraScale+ MPSoC device package delay is accommodated for in the layout of the USB2.0
signal trace lengths. The average of min and max values for package delay is utilized to compensate for
the flight time caused by the delay associated with this package.

Version 1.0 Page 14
2.5 10/100/1000 Ethernet PHY
The UltraZed-EG SOM provides a single 10/100/1000 Ethernet port. The Zynq UltraScale+ MPSoC contains
hardened PS Gigabit Ethernet MAC (GEM) controllers. The UltraZed-EG SOM takes advantage of one of
the available PS GEM controllers to provide RGMII Ethernet signalling to the JX3 connector. The Texas
Instruments DP83867 device is used to implement this interface. The 10/100/1000 Ethernet PHY connect
to the Zynq UltraScale+ MPSoC device through Bank 502.
The physical RJ45 connector and magnetics is not populated on the UltraZed-EG SOM. The SOM is
designed to have the physical RJ45 connector and magnetics reside on the end-user carrier card. The
RJ45 connector signals are connected to the JX3 Micro Header. The table below shows the connections
of these signals to the JX3 Micro Header.
Table 7 –10/100/1000 Ethernet JX3 Pin Assignments
Signal Name
JX3 Pin
ETH_MD1_P
57
ETH_MD1_N
59
ETH_MD2_P
56
ETH_MD2_N
58
ETH_MD3_P
63
ETH_MD3_N
65
ETH_MD4_P
62
ETH_MD4_N
64
ETH_PHY_LED0
53
ETH_PHY_LED1
52
The next table shows the pin assignments to Bank 502 of the Zynq UltraScale+ MPSoC device for the
10/100/1000 Ethernet Port.
Table 8 –10/100/1000 Ethernet MPSoC Pin Assignments
Ethernet PHY Signals
MPSoC Pin
MIO77_GEM3_MDIO
H19
MIO76_GEM3_MDC
H20
MIO74_GEM3_RX_D3
G20
MIO73_GEM3_RX_D2
F20
MIO72_GEM3_RX_D1
E20
MIO71_GEM3_RX_D0
E19
MIO75_GEM3_RX_CTL
F19
MIO70_GEM3_RX_CLK
C20
MIO68_GEM3_TX_D3
G18
MIO67_GEM3_TX_D2
H18
MIO66_GEM3_TX_D1
D19
MIO65_GEM3_TX_D0
A20
MIO69_GEM3_TX_CTL
B20
MIO64_GEM3_TX_CLK
F18
GEM3_RST_N
N/C
The GEM3 peripheral is used on the PS, connected through MIO [64-77] in MIO Bank 502. The Ethernet
Reset signal is active-low and connected to the I/O expander via Port 2, P2_GEM3_RST_N. Either of the
push button resets, PS_POR_B or PS_SRST_B will also generate the active-low Ethernet Reset signal.
The UltraZed-EG SOM also contains an active-low Ethernet PHY interrupt/power down signal that is
connected to the I/O expander via Port 3, P3_GEM3_PWDN_N. By default, the end-user can assert this
control signal to enable the Power Down mode of operation for the Gigabit Ethernet PHY. Alternatively, if
the pin is programmed as an interrupt output, interrupts will be asserted low to the I/O Expander. The latter

Version 1.0 Page 15
requires register access to the Gigabit Ethernet PHY as well as a software polling mechanism for the I/O
Expander to identify interrupt activity.
A high-level block diagram of the 10/100/1000 Ethernet interface is shown in the following figure.
TX_CLK
TX_D[0:3]
TI DP83867 10/100/1000 PHY
10/100/1000
Magnetics
RJ45
Connector
TP_P_A
TP_M_A
TP_P_B
TP_M_B
TP_P_C
TP_M_C
TP_P_D
TP_M_D
TX_CTRL
RX_D[0:3]
XI
RX_CLK
MPSoC
RX_CTRL
Bank 502
VCCO = 1.8V
MDC
MDIO
RESETn
XO
Crystal @
25MHz
LED0,
LED1,
LED2
RBIAS
11K
VDDIO
VDDA1P8
VDDA2P5
VDD1P0
INT/PWDN
2.2K
1.8V
1.8V
1.8V
2.5V
1.0V
2.2K
1.8V JTAG TDI, TDO, TMS, TCK
RX_ER/GPIO0
COL/GPIO1
RX_CTRL
1.8V
1.8V
0
0
0
3.3V
2.2K
1.8V
Figure 6 –10/100/1000 Ethernet Interface Implementation
2.5.1 Ethernet PHY Strapping Resistors
The Texas Instruments DP83867 device that is utilized to implement the 10/100/1000 Ethernet PHY
functionality contains many setup options that can be implemented through strapping resistors physically
on the PCB rather than through register accesses in software. These strapping resistors allow the
10/100/1000 Ethernet PHYs to be active without user interaction.
The following figure shows the strapping circuit and the possible resistor combinations that set the proper
mode.

Version 1.0 Page 16
Figure 7 –PHY Strapping Circuit and Modes
The following table lists the various strapping options that are available for the 10/100/1000 Ethernet PHY
on the UltraZed-EG SOM and the default mode that they are strapped too. For a definition of what other
options are available by changing the default mode settings, please refer to the Texas Instruments
DP83867 data sheet.
Table 9 –10/100/1000 Ethernet PHY Strapping Configuration
PHY1 Strap Function
PHY1 Pin Name
Mode Set
Function Value
PHYADD[1:0]
RX_D0
2
“01”
PHYADD[3:2]
RX_D2
1
“00”
EEE Disable / Autoneg Disable
RX_CTRL
3
“10”
RGMII Clock Skew RX[0]
GPIO_0
1
“0”
RGMII Clock Skew RX[2:1]
GPIO_1
2
“01”
RGMII Clock Skew TX[1:0]
LED_2
3
“10”
SPEED_SEL / RGMII Clock Skew TX[2]
LED_1
1
“00”
Mirror Enable / SGMII Enable
LED_0
1
“00”
This set PHY1 ADDRESS to “0001”, RGMII RX Clock Skew to “001” for 1.0ns skew, RGMII TX Clock Skew
to “001” for 1.0ns skew, and SPEED SEL to “0” for Tri-Mode Ethernet.
2.5.2 Ethernet PHY LEDs
The UltraZed-EG SOM contains a single Ethernet PHY controlled LED, the LINK LED. On board the end-
user carrier card or within the RJ45 Ethernet Jack on the end-user carrier card, two additional Ethernet PHY
controlled LED signal are provided, SPEED and ACTIVITY.SPEED and ACTIVITY LEDs need to be
implemented on the end-user carrier card. Care must be taken when implementing these LEDs as the
signals being driven onto the JX3 connector by the Ethernet PHY are at 1.8V and that may not be enough
to illuminate the LEDs in an RJ45 jack or other on-board LED circuitry. A recommendation for the end-user
carrier card would be to implement a circuit similar to the LINK LED that exists on the UltraZed-EG SOM.
2.5.3 SFVA625 Device Package Delay Compensation for 10/100/1000 Ethernet Interface
The Zynq UltraScale+ MPSoC device package delay is accommodated for in the layout of the Gigabit
Ethernet signal trace lengths. The average of min and max values for package delay is utilized to
compensate for the flight time caused by the delay associated with this package.

Version 1.0 Page 17
2.6 I2C I/O Expander
The UltraZed-EG SOM uses a Texas Instruments TCA9534PWR (16-pin TSSOP) I2C and SMBUS Low-
Power I/O Expander. The Zynq UltraScale+ MPSoC controller required for I2C is named I2C1 and it exists
at MIO [25:24].
Table 10 –I2C1 TRM Pin Mapping
IO NAME
TRM SIGNAL NAME
NET NAME
PS_MIO24
SCL_OUT
MIO24_I2C1_SCL
PS_MIO25
SDA_OUT
MIO25_I2C1_SDA
Each of the ports of the I2C I/O Expander represents functions different control functions like resets and
power down. The following tables describes the connections and functionality of the ports of the I2C I/O
Expander.
Table 11 –Texas Instruments TCA9534 Pin Mapping
I/O EXPANDER NAME
I/O EXPANDER PIN
FUNCTION
NET NAME
A0
1
ADDRESS
GND
A1
2
ADDRESS
GND
A2
3
ADDRESS
GND
P0
4
P-PORT
P0_EMMC0_RST_N
P1
5
P-PORT
P1_USB0_RST_N
P2
6
P-PORT
P2_GEM3_RST_N
P3
7
P-PORT
P3_GEM3_PWDN_N
GND
8
GROUND
GND
P4
9
P-PORT
P4_I2CMUX_INT_N
P5
10
P-PORT
P5_PMBUS_ALERT_N
P6
11
P-PORT
P6_I2CMUX_RST_N
P7
12
P-PORT
P7_CC_RST_N
INT_N
13
INTERRUPT
MIO23_INT_N
SCL
14
SERIAL CLOCK
MIO24_I2C1_SCL
SDA
15
SERIAL DATA
MIO25_I2C1_SDA
VCC
16
POWER
+VCCO_PSIO0_500
Table 12 –TCA9534 P-Ports Function
I/O NAME
FUNCTION
DIRECTION
Active-State
NET NAME
P0
eMMC Soft Reset
OUTPUT
LOW
P0_EMMC0_RST_N
P1
USB 2.0 ULPI PHY
Soft Reset
OUTPUT
LOW
P1_USB0_RST_N
P2
Gigabit Ethernet PHY Soft Reset
OUTPUT
LOW
P2_GEM3_RST_N
P3
Gigabit Ethernet Power-Down
OUTPUT
LOW
P3_GEM3_PWDN_N
P4
2-Ch I2C Switch/Mux Interrupt
INPUT
LOW
P4_I2CMUX_INT_N
P5
PMBUS Alert #
INPUT
LOW
P5_PMBUS_ALERT_N
P6
2-Ch I2C Switch/Mux Soft Reset
OUTPUT
LOW
P6_I2CMUX_RST_N
P7
Carrier Card Reset
OUTPUT
LOW
P7_CC_RST_N
The following figure describes the addressing required to access the I2C I/O Expander. Please see the
appropriate device datasheet for further details regarding accessing this device.

Version 1.0 Page 18
Figure 8 –I2C I/O Expander Addressing
2.7 I2C Switch/Multiplexer
The UltraZed-EG SOM uses a Texas Instruments TCA9543APWR (14-pin TSSOP) Serial Bus
Switch/MUX with Interrupt. The Zynq UltraScale+ MPSoC controller required for I2C is named I2C1 and it
exists at MIO [25:24].
Table 13 –I2C1 TRM Pin Mapping
IO NAME
TRM SIGNAL NAME
NET NAME
PS_MIO24
SCL_OUT
MIO24_I2C1_SCL
PS_MIO25
SDA_OUT
MIO25_I2C1_SDA
The I2C Switch/MUX allows for selection of control of the end-user carrier card two-wire serial interface or
alternatively one could select the PMBUS interface that is tied to the UltraZed-EG SOM main multi-output
power supplies as well as any device that may exist on the end-user carrier card PMBUS through the JX2
connector. The two-wire serial interface on the Zynq UltraScale+ MPSoC is used as the serial source for to
the TCA9543A.The following table shows the connections to the TCA9543A device.
Table 14 –Texas Instruments TCA9543A Pin Mapping
SWITCH/MUX
NAME
SWITCH/MUX
PIN
FUNCTION
NET NAME
A0
1
ADDRESS
GND
A1
2
ADDRESS
GND
RESET_N
3
RESET
P6_I2CMUX_RST_N
INT0_N
4
INTERRUPT0
CC_INT_N
SD0
5
SERIAL DATA0
CC_SDA
SC0
6
SERIAL CLOCK0
CC_SCL
GND
7
GROUND
GND
INT1_N
8
INTERRUPT1
N/C
SD1
9
SERIAL DATA1
PMBUS_SDA
SC1
10
SERIAL CLOCK1
PMBUS_SCL
INT_N
11
INTERRUPT
P4_I2CMUX_INT_N
SCL
12
SERIAL CLOCK
MIO24_I2C1_SCL
SDA
13
SERIAL DATA
MIO25_I2C1_SDA
VCC
14
POWER
+2.5V
The following table should provide a clearer understanding of how the TCA9543A is expected to function in
the system.

Version 1.0 Page 19
Table 15 –I2C MUX/SWITCH Channel Usage
The following figure describes the addressing required to access the I2C Switch/MUX. Please see the
appropriate device datasheet for further details regarding transactions to and from this device.
Figure 9 –I2C Switch/MUX Addressing
2.7.1 End-User Carrier Card I2C Interface
The UltraZed-EG SOM provides a master two-wire serial bus (CC_SDA, CC_SCL, and CC_INT_N) to the
end-user carrier card via the JX3 connector so that software can communicate with all I2C devices on the
UltraZed-EG SOM as well as the slave I2C devices on the end-user carrier card using a single two-wire
serial interface.
The end-user carrier card two-wire serial interface is connected to channel 0 of the 2-channel switch/mux
device. End-user carrier cards can drive the INT0_N of the channel 0 via CC_INT_N, if they so desire. The
CC_INT_N (an active low signal) is not specific to the I2C interface and can be used as a general-purpose
interrupt from end-user carrier cards to the UltraZed-EG SOM. If not used, the CC_INT_N signal is to be
pulled up to 1.8V, 2.5V, or 3.3V on the Carrier Card. Since channel 0 I2C bus is dedicated to the end-user
carrier card, two-wire serial devices with any address can reside on this bus without conflicting with the I2C
devices on the UltraZed-EG SOM.
Table 16 –Carrier Card I2C Net Mapping
Switch/MUX
NAME
Switch/MUX
PIN
FUNCTION
NET NAME
JX3 CONNECTOR
INT0_N
4
INTERRUPT0
CC_INT_N
JX3.68
SD0
5
SERIAL DATA0
CC_SDA
JX3.41
SC0
6
SERIAL CLOCK0
CC_SCL
JX3.44
Switch/MUX Channel
Usage
Notes
Master Channel
(SDA/SCL/INT)
This channel is connected to the PS I2C port, MIO [24:25] and
operated at 1.8V. The master INT_N output is connected to the P4
port of the I2C 8-bit I/O expander.
Pulled-up to
1.8V on the
SOM
Slave Channel 0
(SD0/SC0/INT0)
This channel is connected to the JX3 connector (CC_SDA,
CC_SCL, and CC_INT_N signals) to allow slave I2C devices on the
Carrier Card to be virtually placed on the same PS I2C bus (MIO
[24:25]) as the I2C devices on the UltraZed-EG SOM so that
software can use a single PS I2C core to communicate with all I2C
devices in the system.
Pulled-up to
1.8V, 2.5V, or
3.3V on the
Carrier Card
Slave Channel 1
(SD1/SC1/INT1)
This channel is connected to the PMBus (PMBUS_SDA and
PMBUS_SCL signals) of the UltraZed-EG SOM PMBus voltage
regulators and used to control all PMBus voltage regulators on the
UltraZed-EG SOM as well as the Carrier Card (the PMBus is
connected to the Carrier Card via JX2 connector).
This feature will allow the PS to control/monitor the PMBus voltage
regulators on the UltraZed-EG SOM as well as the Carrier Card for
the purpose of power management and/or measurements.
Pulled-up to
3.3V on the
SOM
The unused
slave channel
1 INT1_N input
must be pulled
up to the VCC
(2.5V) rail.

Version 1.0 Page 20
2.7.2 PMBUS Interface
A PMBus is used on the UltraZed-EG SOM to program/control/monitor all on-board PMBus voltage
regulators. The UltraZed-EG SOM has access to the end-user carrier card PMBus signals via the JX2
connector (PMBUS_SDA, PMBUS_SCL, and P5_PMBUS_ALERT_N signals).
After the initial programming of all PMBus voltage regulators, the UltraZed-EG SOM can drive the PMBus
(via channel 1 of the I2C switch/mux and P5 port of the I2C 8-bit I/O expander) in order to control/monitor
the PMBus voltage regulators on the UltraZed-EG SOM for the purpose of power management and/or
measurements. If the PMBus is implemented on the end-user carrier card, the UltraZed-EG SOM PMBus
can monitor/control the end-user carrier card PMBus voltage regulators as well.
If not used, the UltraZed-EG SOM PMBus interface must be left unconnected on the end-user carrier
cards so that the UltraZed-EG SOM can still control/monitor its on-board PMBus regulators.
Table 17 –PMBUS JX2 Connector Mapping
PMBUS NAME
JX2 CONNECTOR
PMBUS_SDA
JX2.11
PMBUS_SCL
JX2.12
P5_PMBUS_ALERT_N
JX2.35
The following figure shows how the PMBus will be connected on the UltraZed-EG SOM and the UltraZed
IO Carrier Card from Avnet.
I2C 8-Bit I/O
Expander
I2C –MIO[24:25]
2-Channel
I2C Switch/Mux
P5
SD1/SC1SDA/SCL
MPSoC
PS
SDA/SCL
PMBus
Voltage
Regulator
PMBus
Header
PMBus
Voltage
Regulator
PMBus_DATA, PMBus_CLK, PMBus_ALERT#
JX2 Connector
PMBus_ALERT#
PMBus_DATA, PMBus_CLK
UltraZed IO Carrier Card
UltraZed-EG SOM
PMBus
Voltage
Regulator
Shunt Jumpers
JP2/JP3
0-ohm
Resistor
Figure 10 –PMBUS Connections