Avnet ROHM Semiconductor User manual

ROHM Semiconductor
Power Module
User Guide

Copyright © 2012 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners.
Avnet Electronics Marketing 2 of 8 Rev A 1.0 06/05/2013
Table of Contents
1 Introduction.............................................................................................................................................................................................3
1.1Description................................................................................................................................................................................3
1.2Features....................................................................................................................................................................................3
1.3Reference Design.....................................................................................................................................................................3
1.4Ordering Information.................................................................................................................................................................3
2Functional Description.......................................................................................................................................................................4
2.1Block Diagram...........................................................................................................................................................................4
2.2Power Module Interfaces ..........................................................................................................................................................4
2.3DDR Memory Voltage Select Jumper .......................................................................................................................................5
2.4Remote Sense..........................................................................................................................................................................6
2.5Sequencing and Startup ...........................................................................................................................................................6
2.6Mechanical................................................................................................................................................................................6
2.7Board Image .............................................................................................................................................................................8
2.8Revisions ..................................................................................................................................................................................8

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1Introduction
The purpose of this manual is to describe the functionality and contents of the Rohm
Semiconductor Power Module from Avnet Electronics Marketing. This document includes
instructions for operating the board, descriptions of the hardware features and explanations of
the header signals and functionality.
1.1 Description
The Power Module is designed to be used with the Avnet Mini-Module Plus development
system, or any system that meets the mechanical interconnect, pinout, voltage and current
requirements set forth in this document. The power module operates off a 12VDC input
provided from the target baseboard. The following table shows the output voltages generated
by the power module, as well as the voltage banks each rail is tied to through the baseboard
when used in the Mini-Module Plus system.
Xilinx power bank / FMC Voltage Voltage (V) Max Current (A) Tolerance
Vccint/Vccbram 1 6 3.00%
Vcco 1.5 / 1.35 4 5.00%
Vccaux/Vccaux_io/Vccadc/Vcco/MGTVccaux 1.8 65.00%
Vccaux_io 223.00%
Vcco 2.5 85.00%
Vcco 3.3 8 5.00%
MGTAVcc 1 6 3.00%
MGTAVtt/MGTAVTTrcal 1.2 4 2.50%
Table 1 – Output Voltages
1.2 Features
The Power Module provides a complete power solution through the use of 3 headers. 2
headers are used to provide power between the Avnet Power Module and the target board. The
3rd header is used to provide access to remote sensing for increased regulation accuracy.
There is one configurable supply provided on the board which is selectable to be either 1.5V
output or 1.35V output. This supply configurability allows the Power Module to work with the
Mini-Module Plus system, supporting Mini Module cards populated with either 1.5V or 1.35V
DDR3 memory.
1.3 Reference Design
Reference design files for this board are available at:
www.em.avnet.com/pom-rhm1
1.4 Ordering Information
Part Number Hardware
AES-POM-RHM1-G Rohm Semiconductor Power Module

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2 Functional Description
The power module provides 8 sequenced output voltages with controlled rise times from a
12VDC input. The supplies are designed to meet the current and regulation tolerances outlined
in table 1.
2.1 Block Diagram
Figure 1 - Block Diagram
2.2 Power Module Interfaces
The following tables show the pinouts for J1, J2 and J3. J1 and J2 provide power and ground to
and from the baseboard. J1 (Samtec part # HPM-10-05-T-S) and J2 (Samtec part # HPM-08-
05-T-S) provide power to and from the board. On the baseboard, J1 mates with Samtec part #
HPF-10-01-T-S and J2 mates with Samtec part # HPF-08-01-T-S.
Pin 1 2 3 4 5 6 7 8 9 10
Signal GND 1.5V/1.35V GND 1.8V GND 2V GND 3.3V GND 12V
Table 2 - J1 Pinout
Pin 1 2 3 4 5 6 7 8
Signal GND 1V GND 1V(MGT) GND 1.2V GND 2.5V
Table 3 - J2 Pinout

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J3 (Samtec part # FW-05-05-F-D-361-085) is in place to provide access for remote voltage
sense. The mating connector on the baseboard is Samtec part # CLP-105-02-F-D. The signals
on this header are tied directly to the load voltage pins. This header is pinned out left to right
down the header as illustrated below:
1 2
3 4
5 6
7 8
9 10
Table 4 - J3 Diagram
Pins are defined as follows:
Pin 2 4 6 8 10
Signal 2.5Vrm 1Vmgtrm 2Vrm 1.2Vrm GND
Pin 1 3 5 7 9
Signal 3.3Vrm 1.8Vrm 1Vrm 1.5Vrm GND
Table 5 - J3 Pinout
Pin 1 location on J3 is indicated on the silk screen on the PCB. Pin 1 on J1 and J2 are the right
most pins when viewing the board header side up. Refer to Figure 2 for an illustration of these
pin positions.
2.3 DDR Memory Voltage Select Jumper
JP3 sets the output of the 1.5V / 1.35V regulator. JP1 is a 2 pin header with a jumper selected
to be open or closed. Place the jumper on pins 1-2 to set the voltage to 1.5V. Leave the jumper
open to set the voltage to 1.35V. The table below shows the jumper settings and corresponding
output voltage.
JP1 setting Output voltage
Open 1.35V
Closed 1.5V
Table 6 – JP3 Jumper Settings
Setting the voltage to 1.5V or 1.35V is dependent on the type of memory utilized on the target
board. In the case of the K7 Mini-Module for example, the DDR memory used is 1.5V.
WARNING: Be sure to check that the voltage is set to the proper level before powering the
board. Using the wrong voltage can cause damage to the device or the target board.

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2.4 Remote Sense
Remote sense is used to compensate for the power supplies being located far from the load. J3
provides a low impedance path directly to the voltage pins on the load. By allowing access to
the voltage actually being seen by the load, the regulator can adjust the output to be more
accurate and compensate for impedance losses through components and the PCB.
When using remote sense, the signals tied to the header are traces that are terminated right at
the pin of the target load. In the Mini-Module Plus case, these voltage pins are terminated right
at the pins on the FPGA. The signals are then routed as traces back to the remote sense
header. It is important that the signals originate from as close to the target load as possible.
The signals on these pins are then used as the set point by the regulators to regulate the output
voltage. By using a signal directly tied to the load as the set point, the power supplies are able
to better regulate the voltage at the intended load.
2.5 Sequencing and Startup
Sequencing of the output voltages follows Xilinx specification for 7 Series devices as follows:
Vccint (1V) -> Vccaux (1.8V) -> Vccaux_io (2V) -> Vcco
The power module is designed to start all remaining supplies after the 2V rail has come up.
The diagram below illustrates the start up sequencing of the power module.
1V Vccint
1.8V Vccaux
2V Vccaux_io
1.35V / 1.5V Vcco
2.5V Vcco
3.3V Vcco
1V MGT
1.2V MGT
Timing Diagram
Each rail starts up between 0.2ms and 50ms to meet ramp requirements, as well as have
monotonic rises. The requirement for power down sequencing states that the 3.3V Vcco rail
cannot exceed the 1.8V Vccaux rail during shut down by more than 2.625V for longer than
500ms. No additional power down circuitry is needed in the power module to meet this
requirement.
2.6 Mechanical
The Power Module meets the following geometry requirements:
Max Component Height 0.4”

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Max Board Width 3.5”
Max Board Length 5.5”
Clearance Between Mated Boards
(power module and baseboard) 0.45”
Table 5
Along with meeting these geometry requirements, headers J1, J2, and J3 are placed on the
bottom of the board according to the definition below:
Figure 1 – Mechanical Header and Mounting Hole Locations
These locations are based on a topside view looking through the board. The headers are
placed on the bottom. J3 is measured to the center of the connector. The mounting holes are
plated through holes with a 125mil diameter. The mounting holes are not electrically connected
on the module.
Pin 1 locations for J1, J2 and J3 are illustrated below in Figure 2. The view is looking down on
the board with the connectors facing up.

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Figure 2 – Header Pin 1 Locations
2.7 Board Image
2.8 Revisions
01 Initial Release Chris Ammann
1
J2 J3
J1
1
1