Cypress Semiconductor MoBL CY62157EV30 User manual

8-Mbit (512K x 16) Static RAM
CY62157EV30 MoBL®
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05445 Rev. *E Revised May 07, 2007
Features
• TSOP I package configurable as 512K x 16 or as 1M x 8
SRAM
• High speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62157DV30
• Ultra low standby power
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA (Industrial)
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in both Pb-free and non Pb-free 48-ball VFBGA,
Pb-free 44-pin TSOP II and 48-pin TSOP I packages
Functional Description[1]
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™(MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Place the device into standby mode when deselected (CE1
HIGH or CE2 LOW or both BHE and BLE are HIGH). The input
or output pins (IO0through IO15) are placed in a high
impedance state when:
• Deselected (CE1HIGH or CE2LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE1LOW, CE2HIGH and WE
LOW)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0through IO7) is
written into the location specified on the address pins (A0
through A18). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO8through IO15) is written into the location
specified on the address pins (A0through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appear on IO0to IO7. If Byte High Enable (BHE) is LOW, then
data from memory appears on IO8to IO15. See the “Truth
Table” on page 10 for a complete description of read and write
modes.
Logic Block Diagram
512K × 16 / 1M x 8
RAM Array IO0–IO7
ROW DECODER
A 8
A 7
A 6
A 5
A 2
COLUMN DECODER
A11
A12 A13 A14 A15
SENSE AMPS
DATA IN DRIVERS
OE
A 4
A 3IO8–IO15
WE
BLE
BHE
A16
A 0
A 1
A17
A 9
A18
A10
PowerDown
Circuit BHE
BLE
CE2
CE1CE2
CE1
BYTE
Notes
1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *E Page 2 of 14
Product Portfolio
Product Range
VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(µA)
f = 1MHz f = fmax
Min Typ [2] Max Typ [2] Max Typ [2] Max Typ [2] Max
CY62157EV30LL Ind’l/Auto-A 2.2V 3.0 3.6 45 1.8 3 18 25 2 8
Pin Configuration
The following pictures show the 44-pin TSOP II and 48-pin TSOP I pinouts.[3, 4, 5]
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
18
17
20
19
27
28
25
26
22
21
23
24
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
IO15/A19
IO7
IO14
IO6
IO13
IO5
IO12
IO4
Vcc
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
OE
Vss
CE1
A0
A
5
44-Pin TSOP II
Top View
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
17
A
18
A
9
A
10
A
11
A
12
A
15
A
16
A
14
A
13
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
A
8
48-Pin TSOP I (512K x 16 / 1M x 8)
Top View
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.
3. NC pins are not connected on the die.
4. The 44-TSOP II package has only one chip enable (CE) pin.
5. The BYTE pin in the 48-TSOP I package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and IO8 to IO14 pins are not used (DNU).
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *E Page 3 of 14
The following picture shows the 48-ball VFBGA pinout.[3, 4, 5]
Pin Configuration (continued)
WE
V
CC
A11 A10
NC
A6
A0
A3CE1
IO10
IO8
IO9
A4
A5
IO11
IO13
IO12
IO14
IO15
V
SS
A9
A8
OE
V
SS
A7
IO0
BHE
CE2
A2
A1
BLE
V
CC
IO2
IO1
IO3
IO4
IO5IO6
IO7
A15
A14
A13
A12
NC
A18 NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
A17
48-Ball VFBGA
Top View
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Document #: 38-05445 Rev. *E Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. User guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential ................................–0.3V to 3.9V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State [6, 7]................–0.3V to 3.9V (VCCmax + 0.3V)
DC Input Voltage [6, 7] ........... –0.3V to 3.9V (VCC max + 0.3V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current .................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC [8]
CY62157EV30LL Ind’l/Auto-A –40°Cto +85°C 2.20V to
3.60V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns (Ind’l/Auto-A) Unit
Min Typ [2] Max
VOH Output HIGH Voltage IOH = –0.1 mA 2.0 V
IOH = –1.0 mA, VCC >2.70V 2.4 V
VOL Output LOW Voltage IOL = 0.1 mA 0.4 V
IOL = 2.1mA, VCC >2.70V 0.4 V
VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3 V
VCC = 2.7V to 3.6V 2.2 VCC + 0.3 V
VIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 V
VCC = 2.7V to 3.6V –0.3 0.8 V
IIX Input Leakage Current GND < VI< VCC –1 +1 µA
IOZ Output Leakage Current GND < VO <VCC, Output Disabled –1 +1 µA
ICC VCC Operating Supply Current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
18 25
mA
f = 1 MHz 1.8 3
ISB1 Automatic CE Power Down
Current — CMOS Inputs CE1> VCC − 0.2V, CE2 <0.2V
VIN >VCC – 0.2V, VIN <0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE), VCC = 3.60V
28µA
ISB2 [9] Automatic CE Power Down
Current — CMOS Inputs CE1> VCC – 0.2V or CE2< 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V
28µA
Capacitance [10]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Notes
6. VIL(min) = –2.0V for pulse durations less than 20 ns.
7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after VCC stabilization.
9. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other
inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
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Thermal Resistance [10]
Parameter Description Test Conditions BGA TSOP I TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
72 74.88 76.88 °C/W
ΘJC Thermal Resistance
(Junction to Case)
8.86 8.6 13.52 °C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
Parameters 2.5V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
TH
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [2] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR [9] Data Retention Current VCC= 1.5V, CE1> VCC – 0.2V,
CE2< 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
Ind’l/Auto-A 2 5 µA
tCDR [10] Chip Deselect to Data
Retention Time 0ns
tR [11] Operation Recovery Time tRC ns
Data Retention Waveform[12]
Figure 2. Data Retention Waveform
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC(min)
CE1or
VCC
BHE.BLE
CE
2
or
Notes
11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
12. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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Switching Characteristics
Over the Operating Range[13, 14]
Parameter Description 45 ns (Ind’l/Auto-A) Unit
Min Max
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE1LOW and CE2 HIGH to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to LOW-Z[15] 5ns
tHZOE OE HIGH to High-Z[15, 16] 18 ns
tLZCE CE1LOW and CE2 HIGH to Low-Z[15] 10 ns
tHZCE CE1HIGH and CE2 LOW to High-Z[15, 16] 18 ns
tPU CE1LOW and CE2 HIGH to Power Up 0 ns
tPD CE1HIGH and CE2 LOW to Power Down 45 ns
tDBE BLE/BHE LOW to Data Valid 45 ns
tLZBE BLE/BHE LOW to Low-Z[15, 17] 5ns
tHZBE BLE/BHE HIGH to HIGH-Z[15, 16] 18 ns
Write Cycle[18]
tWC Write Cycle Time 45 ns
tSCE CE1LOW and CE2 HIGH to Write End 35 ns
tAW Address Setup to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tBW BLE/BHE LOW to Write End 35 ns
tSD Data Setup to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z[15, 16] 18 ns
tLZWE WE HIGH to Low-Z[15] 10 ns
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
17. If both byte enables are toggled together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
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Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[19, 20]
Figure 3. Read Cycle No. 1
Read Cycle No. 2 (OE Controlled)[20, 21]
Figure 4. Read Cycle No. 2
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tPD
tHZBE
tLZBE
t
HZCE
tDBE
OE
CE1
ADDRESS
CE2
BHE/BLE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH
ICC
ISB
IMPEDANCE
Notes
19. The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2transition HIGH.
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Write Cycle No. 1 (WE Controlled)[18, 22, 23]
Figure 5. Write Cycle No. 1
Write Cycle No. 2 (CE1or CE2 Controlled)[18, 22, 23]
Figure 6. Write Cycle No. 1
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
tBW
NOTE 24
CE1
ADDRESS
CE2
WE
DATA IO
OE
BHE/BLE
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
VALID DATA
tBW
tSA
NOTE 24
CE1
ADDRESS
CE2
WE
DATA IO
OE
BHE/BLE
Notes
22. Data IO is high impedance if OE = VIH.
23. If CE1goes HIGH and CE2goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
24. During this period, the IOs are in output state. Do not apply input signals.
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *E Page 9 of 14
Write Cycle No. 3 (WE Controlled, OE LOW)[23]
Figure 7. Write Cycle No. 3
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[23]
Figure 8. Write Cycle No. 4
Switching Waveforms (continued)
VALID DATA
tHD
tSD
tLZWE
tPWE
tSA
tHA tAW
tSCE
tWC
tHZWE
tBW
NOTE 24
CE
1
ADDRESS
CE
2
WE
DATA IO
BHE
/BLE
tHD tSD
tSA
tHA tAW
tWC
VALID DATA
tBW
tSCE
tPWE
NOTE 24
CE
1
ADDRESS
CE
2
WE
DATA IO
BHE
/BLE
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Truth Table
CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X X High-Z Deselect/Power Down Standby (ISB)
X L X X X X High-Z Deselect/Power Down Standby (ISB)
X X X X H H High-Z Deselect/Power Down Standby (ISB)
L H H L L L Data Out (IO0–IO15)Read Active (ICC)
L H H L H L Data Out (IO0–IO7);
High-Z (IO8–IO15)Read Active (ICC)
L H H L L H High-Z (IO0–IO7);
Data Out (IO8–IO15)
Read Active (ICC)
L H H H L H High-Z Output Disabled Active (ICC)
L H H H H L High-Z Output Disabled Active (ICC)
L H H H L L High-Z Output Disabled Active (ICC)
L H L X L L Data In (IO0–IO15)Write Active (ICC)
L H L X H L Data In (IO0–IO7);
High-Z (IO8–IO15)
Write Active (ICC)
L H L X L H High-Z (IO0–IO7);
Data In (IO8–IO15)
Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating Range
45 CY62157EV30LL-45BVI 51-85150 48-ball Very Fine Pitch Ball Grid Array Industrial
CY62157EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62157EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
CY62157EV30LL-45ZXI 51-85183 48-pin Thin Small Outline Package Type I (Pb-free)
45 CY62157EV30LL-45BVXA 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Automotive-A
CY62157EV30LL-45ZSXA 51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *E Page 11 of 14
Package Diagrams
Figure 9. 48-Pin VFBGA (6 x 8 x 1 mm), 51-85150
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
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Figure 10. 44-Pin TSOP II, 51-85087
Package Diagrams (continued)
51-85087-*A
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CY62157EV30 MoBL®
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© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 11. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
1N
0.020[0.50]
0.007[0.17]
0.037[0.95]
0.002[0.05]
0°-5°
MAX.
0.028[0.70]
0.010[0.25]
0.004[0.10]
0.011[0.27]
0.041[1.05]
0.047[1.20]
0.472[12.00]
0.724 [18.40]
0.787[20.00]
0.006[0.15]
TYP.
0.020[0.50]
0.008[0.21] GAUGE PLANE
SEATING PLANE
0.004[0.10]
DIMENSIONS IN INCHES[MM] MIN.
MAX.
JEDEC # MO-142
51-85183-*A
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Document History Page
Document Title: CY62157EV30 MoBL®, 8-Mbit (512K x 16) Static RAM
Document Number: 38-05445
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 202940 See ECN AJU New Data Sheet
*A 291272 See ECN SYT Converted from Advance Information to Preliminary
Removed 48-TSOP I Package and the associated footnote
Added footnote stating 44 TSOP II Package has only one CE on Page # 2
Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs
Changed ICCDR from 4 to 4.5 µA
Changed tOHA from 6 to 10 ns for both 35 and 45 ns Speed Bins
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for 35
and 45 ns Speed Bins respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed
Bins respectively
Changed tSCE, tAW and tBW from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns
Speed Bins respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins
respectively
Added Lead-Free Package Information
*B 444306 See ECN NXR Converted from Preliminary to Final.
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU.
Removed 35 ns speed bin
Removed “L” bin
Added 48 pin TSOP I package
Added Automotive product information.
Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28
mA to 25 mA for test condition f = fax = 1/tRC.
Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz.
Changed the ISB1 and ISB2 Max value from 4.5 µA to 8 µA and Typ value from
0.9 µA to 2 µA respectively.
Modified ISB1test condition to include BHE, BLE
Updated Thermal Resistance table.
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for ICCDR .
Changed the ICCDR Max value from 4.5 µA to 5 µA
Corrected tR in Data Retention Characteristics from 100 µs to tRC ns.
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tLZBE from 6 to 5
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Added footnote #15
Updated the ordering Information and replaced the Package Name column
with Package Diagram.
*C 467052 See ECN NXR Modified Data sheet to include x8 configurability.
Updated the Ordering Information table
*D 925501 See ECN VKN Removed Automotive-E information
Added Preliminary Automotive-A information
Added footnote #10 related to ISB2 and ICCDR
Added footnote #15 related AC timing parameters
*E 1045801 See ECN VKN Converted Automotive-A specs from preliminary to final
Updated footnote #9
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