Cypress AutoStore STK17TA8 User manual

STK17TA8
128k X 8 AutoStore™ nvSRAM
with Real Time Clock
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-52039 Rev. ** Revised March 02, 2009
Features
■nvSRAM Combined with Integrated Real Time Clock Functions
(RTC, Watchdog Timer, Clock Alarm, Power Monitor)
■Capacitor or Battery Backup for RTC
■25, 45 ns Read Access and Read/Write Cycle Time
■Unlimited Read/Write Endurance
■Automatic nonvolatile STORE on Power Loss
■Nonvolatile STORE Under Hardware or Software Control
■Automatic RECALL to SRAM on Power Up
■Unlimited RECALL Cycles
■200K STORE Cycles
■20-Year nonvolatile Data Retention
■Single 3 V +20%, -10% Power Supply
■Commercial and Industrial Temperatures
■48-pin 300-mil SSOP Package (RoHS-Compliant)
Description
The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM
(nvSRAM) with a full featured real time clock in a reliable,
monolithic integrated circuit.
The 1 Mb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
Logic Block Diagram
ROW DECODERINPUT BUFFERS
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT A15 – A0
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0A1A2A3A4A10 A11
VCC VCAP
RTC
MUX A16 – A0
X1
X2
INT
VRTCbat
VRTCcap
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STK17TA8
Document #: 001-52039 Rev. ** Page 2 of 23
Pinouts Figure 1. Pin Diagram - 48-PIn SSOP
V
SS
A
14
A
12
A
7
A
6
DQ
0
DQ
1
V
CC
DQ
2
A
3
A
2
A
1
V
CAP
A
13
A
8
A
9
A
11
A
10
DQ
7
DQ
6
V
SS
A
0
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
X
1
X
2
23
24
A
5
INT
NC
NC
NC
NC
A
4
48
47
46
45
V
CC
HSB
NC
NC
W
NC
DQ
5
DQ
3
DQ
4
V
RTCbat
V
RTCcap
A
16
A
15
E
G
(TOP)
Pin Descriptions
Pin Name IO Type Description
A16-A0Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array or one of 16 bytes
in the clock register map
DQ7-DQ0I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC
E Input Chip Enable: The active low E input selects the device
W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location
selected on the falling edge of E
G Input Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
X1Output Crystal Connection, drives crystal on startup
X2Input Crystal Connection for 32.768 kHz crystal
VRTCcap Power Supply Capacitor supplied backup RTC supply voltage (Left unconnected if VRTCbat is used)
VRTCbat Power Supply Battery supplied backup RTC supply voltage (Left unconnected if VRTCcap is used)
VCC Power Supply Power: 3.0V, +20%, -10%
HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external
to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if
not connected. (Connection Optional).
INT Output Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the
power monitor. Programmable to either active high (push/pull) or active low (open-drain)
VCAP Power Supply Autostore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS Power Supply Ground
NC No Connect Unlabeled pins have no internal connections.
Note
1. For detailed package size specifications, See “Package Diagrams” on page 22..
Relative PCB Area Usage[1]
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STK17TA8
Document #: 001-52039 Rev. ** Page 3 of 23
Absolute Maximum Ratings
Voltage on Input Relative to Ground ................–0.1V to 4.1V
Voltage on Input Relative to VSS .........–0.5V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB.....................–0.5V to (VCC + 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Junction Temperature ................................... –55°C to 140°C
Storage Temperature .................................... –65°C to 150°C
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration)..... 15mA
RF (SSOP-48) Package Thermal Characteristics
θjc 6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliablity.
DC Electrical Characteristics
(VCC = 2.7V-3.6V)
Symbol Parameter Commercial Industrial Units Notes
Min Max Min Max
ICC1Average VCC Current 65
50
70
55
mA
mA
tAVAV = 25 ns
tAVAV = 45 ns
Dependent on output loading and
cycle rate. Values obtained
without output loads.
ICC2Average VCC Current during
STORE
3 3 mA All Inputs Don’t Care, VCC = max
Average current for duration of
STORE
cycle (tSTORE)
ICC3Average VCC Current at tAVAV =
200ns
3V, 25°C, Typical
10 10 mA W ≥(V CC – 0.2V)
All Other Inputs Cycling at CMOS
Levels
Dependent on output loading and
cycle rate. Values obtained
without output loads.
ICC4Average VCAP Current during
<Emphasis>AutoStore™ Cycle
3 3 mA All Inputs Don’t Care
Average current for duration of
STORE cycle (tSTORE)
ISB VCC Standby Current
(Standby, Stable CMOS Levels)
33mAE≥ (VCC -0.2V)
All Others VIN≤ 0.2V or ≥
(VCC-0.2V)
Standby current level after
nonvolatile cycle complete
IILK Input Leakage Current ±1 ±1 mA VCC = max
VIN = VSS to VCC
IOLK Off-State Output Leakage Current ±1 ±1 mA VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH Input Logic “1” Voltage 2.0 VCC + 0.5 2.0 VCC + 0.5 V All Inputs
VIL Input Logic “0” Voltage VSS –0.5 0.8 VSS –0.5 0.8 V All Inputs
VOH Output Logic “1” Voltage 2.4 2.4 V IOUT =– 2 mA (except HSB)
VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 4 mA
Note: The HSB pin has IOUT=-10uA for VOH of 2.4V, this parameter is characterized but not tested.
Note: The INT is open-drain and does not source or sink high current when interrupt Register bit D3 is below.
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Document #: 001-52039 Rev. ** Page 4 of 23
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times ............................................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Output Load..................................See Figure 2 and Figure 3
Capacitance
(TA= 25°C, f = 1.0MHz)[2]
Figure 2. AC Output Loading
Figure 3. AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ
TAOperating Temperature 0 70 –40 85 °C
VCC Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10%
VCAP Storage Capacitance 17 57 17 57 μF Between VCAP pin and VSS, 5V
rated.
NVCNonvolatile STORE operations 200 200 K
DATARData Retention 20 20 Years At 55 °C
DC Electrical Characteristics (continued)
(VCC = 2.7V-3.6V)
Symbol Parameter Commercial Industrial Units Notes
Min Max Min Max
Notes
2. These parameters are guaranteed but not tested.
Symbol Parameter Max Units Conditions
CIN Input Capacitance 7 pF ΔV = 0 to 3V
COUT Output Capacitance 7 pF ΔV = 0 to 3V
577 Ohms
30 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
577 Ohms
5 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
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STK17TA8
Document #: 001-52039 Rev. ** Page 5 of 23
RTC DC Characteristics
Figure 4. RTC Recommended Component Configuration
Symbol Parameter Commercial Industrial Units Notes
Min Max Min Max
IBAK RTC Backup Current — 300 — 350 nA From either VRTCcap or VRTCbat
VRTCbat RTC Battery Pin Voltage 1.8 3.3 1.8 3.3 V Typical = 3.0 Volts during normal
operation
VRTCcap RTC Capacitor Pin Voltage 1.2 2.7 1.2 2.7 V Typical = 2.4 Volts during normal
operation
tOSCS RTC Oscillator time to start — 10 — 10 sec At MIN Temperature from Power up
or Enable
—5—5 secAt25°C from Power up or Enable
C1
C2
RF
Y1
X1
X2
Recommended Values
Y1 = 32.768 KHz
= 10M Ohm
= 0 (install cap footprint,
but leave unloaded)
= 56 pF ± 10% (do not vary from this value)
RF
C1
C2
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STK17TA8
Document #: 001-52039 Rev. ** Page 6 of 23
SRAM READ Cycles #1 and #2
Figure 5. SRAM READ Cycle #1: Address Controlled[3, 4, 6]
Figure 6. SRAM READ Cycle #2: Eand G Controlled[3, 6]
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured ±200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles.
NO. Symbols Parameter STK17TA8-25 STK17TA8-45 Units
#1 #2 Alt. Min Max Min Max
1t
ELQV tACS Chip Enable Access Time 25 45 ns
2t
AVAV[3] tELEH[3] tRC Read Cycle Time 25 45 ns
3t
AVQV[4] tAVQV[4] tAA Address Access Time 25 45 ns
4t
GLQV tOE Output Enable to Data Valid 12 20 ns
5t
AXQX[4] tAXQX[4] tOH Output Hold after Address Change 3 3 ns
6t
ELQX tLZ Address Change or Chip Enable to Output Active 3 3 ns
7t
EHQZ[5] tHZ Address Change or Chip Disable to Output
Inactive
10 15 ns
8t
GLQX tOLZ Output Enable to Output Active 0 0 ns
9t
GHQZ[5] tOHZ Output Disable to Output Inactive 10 15 ns
10 tELICCL[2] tPA Chip Enable to Power Active 0 0 ns
11 tEHICCH[2] tPS Chip Disable to Power Standby 25 45 ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
229
11
7
9
10
8
4
3
6
1
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STK17TA8
Document #: 001-52039 Rev. ** Page 7 of 23
SRAM WRITE Cycles #1 and #2
Figure 7. SRAM WRITE Cycle #1: WControlled[7, 8]
Figure 8. SRAM WRITE Cycle #2: EControlled[7, 8]
Notes
7. If W is low when E goes low, the outputs remain in the high-impedance state.
8. Eor W must be ≥VIH during address transitions.
NO. Symbols Parameter STK17TA8-25 STK17TA8-45 Units
#1 #2 Alt. Min Max Min Max
11 tAVAV tAVAV tWC Write Cycle Time 25 45 ns
13 tWLWH tWLEH tWP Write Pulse Width 20 30 ns
14 tELWH tELEH tCW Chip Enable to End of Write 20 30 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 10 15 ns
16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 20 30 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 ns
19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 ns
20 tWLQZ5, 7 tWZ Write Enable to Output Disable 10 15 ns
21 tWHQX tOW Output Active after End of Write 3 3 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
11
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA IN
11
tAVAV
16
tEHDX
13
tWLEH
19
tEHAX
18
tAVEL
17
tAVEH
DATA VALID
15
tDVEH
HIGH IMPEDANCE
14
tELEH
DATA OUT
E
ADDRESS
W
DATA IN
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STK17TA8
Document #: 001-52039 Rev. ** Page 8 of 23
AutoStore/Power Up Recall
Figure 9. AutoStore/Power Up RECALL
Notes
9. tHRECALL starts from the time VCC rises above VSWITCH
10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
11. Industrial Grade Devices require 15 ms MAX.
NO. Symbols Parameter STK17TA8 Units Notes
Standard Alternate Min Max
22 tHRECALL Power-up RECALL Duration 40 ms 9
23 tSTORE tHLHZ STORE Cycle Duration 12.5 ms 10,11
24 VSWITCH Low Voltage Trigger Level 2.65 V
25 VCCRISE VCC Rise Time 150 μS
NOTE: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
25
23 23
22 22
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STK17TA8
Document #: 001-52039 Rev. ** Page 9 of 23
Software-Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed. [12, 13]
Figure 10. Software STORE/RECALL Cycle: ECONTROLLED[13]
Figure 11. Software STORE/RECALL Cycle: G Controlled[13]
NO. Symbols Parameter STK17TA8-35 STK17TA8-45 Units Notes
ECont GCont Alternate Min Max Min Max
26 tAVAV tAVAV tRC STORE / RECALL Initiation Cycle
Time
25 45 ns 13
27 tAVEL tAVGL tAS Address Set-up Time 0 0 ns
28 tELEH tGLGH tCW Clock Pulse Width 20 30 ns
29 tEHAX tGHAX Address Hold Time 1 1 ns
30 tRECALL tRECALL RECALL Duration 100 100 μs
26 26
27 28
29
23 30
26 26
27 28
29
23 30
Notes
12. The software sequence is clocked on the falling edge of E controlled READs or G controlled READs
13. The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table W must be high during all six consecutive cycles.
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STK17TA8
Document #: 001-52039 Rev. ** Page 10 of 23
Hardware STORE Cycle
Figure 12. Hardware STORE Cycle
Soft Sequence Commands
Figure 13. Soft Sequence Commands
NO. Symbols Parameter STK17TA8 Units Notes
Standard Alternate Min Max
31 tDELAY tHLQZ Hardware STORE to SRAM Disabled 1 70 μs14
32 tHLHX Hardware STORE Pulse Width 15 ns
32
23
31
Notes
14. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow READ/WRITE cycles to compete.
15. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
16. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
NO. Symbols Parameter STK17TA8 Units Notes
Standard Min Max
33 tSS Soft Sequence Processing Time 70 μs 15,16
33 33
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