Digital Equipment PDT 11/150 User manual

PDT
III
TECHNICAL MANUAL

EK·PT150·TM·001
PDT -11/150
TECHNICAL MANUAL
digital equipment corporation • marlboro, massachusetts

Copyright © 1980 by Digital Equipment Corporation
All Rights Reserved
The material in this manual is for informational pur-
poses
and is subject to change without notice.
Digital Equipment
Corporation assumes no responsi-
bility for any errors which may appear in this manual.
Printed in U.S.A.
1st Edition, April 1980
This document was set on DIGITAL's DECset-8000 computerized
typesetting system.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS
DECLAB
DECsystem-10
DECSYSTEM-20
DIBOL
EduSystem
VAX
VMS
MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS
MINC-II

PREFACE
CHAPTER 1
1.1
1.2
1.3
1.3.1
1.3.2
1.4
CHAPTER 2
2.1
2.2
2.2.1
2.2.2
2.2.2.1
2.2.2.2
2.3
CHAPTER 3
3.1
3.1.1
3.1.2
3.1.3
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
CHAPTER 4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
. 4.1.5
4.1.6
4.1.7
4.2
4.3
CONTENTS
Page
INTRODUCTION
TYPICAL SYSTEM
CONFIGURA TIONS........................................................ 1-1
EQUIPMENT AND MEDIA SPECIFICATIONS .............................................1-4
RELATED PUBLICATIONS............................................................................. 1-4
Ordering Information for DIGITAL Personnel ............................................ 1-8
Ordering Information for Customers............................................................ 1-8
TECHNICAL REFERENCE MATERIAL ........................................................ 1-9
UNPACKING/INSTALLATION
UNPACKING AND INSPECTION................................................................... 2-1
SITE PREPARATION AND CONNECTIONS ................................................. 2-3
AC Power Requirements .............................................................................. 2-3
Serial Line Cable Connectors........................................................................ 2-5
EIA Connector Pin Assignments .................. ~ ....................................... 2-5
Serial Line Cable Lengths.....................................................................2-5
SERIAL
LINE DATA CHARACTERISTICS .................................................... 2-5
OPERATING PROCEDURES
SWITCHES AND INDICATORS ...................................................................... 3-1
Front Panel Indicators.................................................................................. 3-1
Rear Panel Switches and Components .......................................................... 3-1
Function Switch ...........................................................................................3-2
DISK HANDLING AND STORAGE ................................................................3-4
TEST PROCEDURES ........................................................................................3-4
Preliminary Setup.........................................................................................3-6
Optional Loopback Connector.....................................................................3-6
Self-Test Procedures.....................................................................................
3-7
Loading a System Program........................................................................... 3-8
Changing a System Program.........................................................................3-9
TECHNICAL DESCRIPTION
GENERAL OPERATION .................................................................................. 4-1
Intelligence Module (KDT 11 )...................................................................... .4-1
RAM Module (MSTll) ................................................................................4-3
Peripheral Module (DLTll) .......................................................: .. -...............4-3
Standard and Cluster EIA Modules
(DFTll) ...............................................4-3
Disk Controller Module
(RXTl1) ................................................................4-3
Disk Drive Assemblies (RXTOl)...................................................................4-3
Power Supply Assembly (H7833) ..................................................................4-3
PDT-ll/150 BUS STRUCTURE ........................................................................4-4
SIGNAL DISTRIBUTION .................................................................................4-8
iii

404
404.1
404.2
404.3
40404
404.5
404.6
404.7
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.5.1.4
4.5.1.5
4.5.1.6
4.5.2
4.5.3
4.5.3.1
4.5.3.2
4.5.3.3
4.5.3.4
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.2
4.9
4.9.1
4.9.1.1
4.9.1.2
4.9.2
4.9.2.1
4.9.2.2
4.9.2.3
CONTENTS (Coot)
Page
SYSTEM OPERATION......................................................................................4-8
Power-Up Functions .....................................................................................4-8
I/O Microprocessor Control.......................................................................4-10
Data Transfer Operations.....................................,..................................... 4-1 0
LSI-II Resident Memory............................................................................
4-11
Peripheral Device Interface........................................................................ .4-11
EIA/TTL Level Converters.........................................................................4-12
Disk Controller ..........................................................................................4-12
INTELLIGENCE MODULE FUNCTIONS (DWG. NO. 5413271)..................4-12
8085 I/O Microprocessor and Associated Logic......................................... o4-16
8085 I/O Transfers .............................................................................4-16
Interrupts and Priority Assignments ...................................................4-16
8155 I/O Port and RAM Functions ....................................................4-17
Test Indicator Register .......................................................................4-18
8085 Memory and I/O Select Address Decoding.................................4-18
Power-Up and Manual Reset..............................................................
4-21
Inter-Processor Link (IPL) and Control Logic ............................................4-23
LSI-II Microprocessor and Associated Logic .............................................4-23
Clock Pulse Generator and Power Inverter ........................................
04-26
LSI-II I/O Transfer Sequence ........................................................... .4-28
LSI-II I/O Device Address Decoding................................................ .4-33
Function Control, Fast-Data-In and Interrupt
Request Logic.....................................................................................4-36
RAM
MODULE FUNCTIONS (DWG. NO. 5413275) .....................................4-40
RAM Matrix Configurations...................................................................... 4-43
Address Bus Distribution............................................................................4-44
Bank Select Decoder Logic .........................................................................4-44
Row/Column and Address MUltiplexer Logic ...........................................
04-47
RAM Refresh Logic ...................................................................................4-50
RAM Read or Write Operations................................................................ o4-50
Reply Logic................................................................................................4-50
PERIPHERAL MODULE FUNCTIONS (DWG. NO. 5413269) ..................... .4-51
Information Transfers ................................................................................ 4-51
Standard Device USARTs ..........................................................................4-53
Optional Device USARTs ..........................................................................4-57
Front Panel Indicators................................................................................4-58
Function Switch Selections.........................................................................4-59
EIA/TTL LEVEL CONVERTER FUNCTIONS ............................................. .4-59
Standard EIA Module Functions (DWG. NO. 5413267) .............................4-60
Cluster EIA Module Functions (DWG. NO. 5413427) ........................;.......4-64
FLEXIBLE DISK DESCRIPTION......................................;...........................
04-66
Recording Format ......................................................................................4-67
Header Field.......................................................................................4-68
Data Field ..........................................................................................4-68
Recording Method .....................................................................................4-68
Data Recording Patterns .................................................................... 4-68
Data and Address Mark Recording ................................................... .4-68
Synchronizing Fields ............................·..............................................4- 70
iv

4.10
4.10.1
4.10.1.1
4.10.1.2
4.10.2
4.10.3
4.10.4
4.10.5
4.10.5.1
4.10.5.2
4.10.6
4.10.6.1
4.10.6.2
4.11
4.11.1
4.11.1.1
4.11.1.2
4.11.2
4.11.3
4.11.3.1
4.11.3.2
4.11.3.3
CHAPTER 5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.2
5.3.2.1
5.3.2.2
5.3.3
5.3.3.1
5.3.3.2
5.3.4
CONTENTS (Cont)
Page
DISK CONTROLLER MODULE FUNCTIONS (DWG. NO. 5413273)..........4-70
8085 Controller Microprocessor .................................................................4-70
Power-up and Initialize Functions ......................................................4-73
Read
or Write Operations...................................................................4-74
Disk Drive Selections..................................................................................4-74
Self-Test Function Select and Indicator Logic.............................................4-
75
Head Load Control and Track/Index Hole Detection.................................4-76
Stepper Motor Direction and Control Logic ...............................................4-79
Stepper Motor Pulse Generation.........................................................4- 79
Stepper Motor Control and Drive Circuits..........................................4-82
FD 1771 Disk Controller and Associated Logic ...........................................4-86
Disk Write Operations........................................................................4-86
Disk Read Operations ........................................................................4-89
H7833
POWER SUPPLY MODULE (DWG. NO. 5413343)............................4-100
Input ac Voltage Circuits .......................................................................... 4-1 02
115 V ac Voltage Doubler Circuit......................................................4-102
230 V ac Full Wave Rectifier Circuit ................................................
.4-1 02
Flyback Inverter Circuit............................................................................ 4-1 04
Control Circuit......................................................................................... 4-1 04
Oscillator and Pulse Width Modulator..............................................4-107
Error Amplifier Circuit.....................................................................4-107
Current Limiter Circuit..................................................................... 4-1 08
SERVICE
PERFORMANCE TESTS AND FAULT ANALYSIS ....................................... 5-1
LED Indicator Locations .............................................................................5-4
Fault Isolation Procedures............................................................................5-4
Loading the System Exerciser Program.......................................................5-22
Exerciser Compatibility Test...........................
~ ...........................................5-26
Copying the System Exerciser Disk.............................................................5-27
Loading a System Program.........................................................................5-27
Changing a System Program.......................................................................5-28
POWER DISTRIBUTION ................................................................................5-28
Internal Cable and Connector Locations.....................................................5-28
Initial ac Power Checks...............................................................................
5-31
Initial de Power Checks ..............................................................................5-39
REMOVAL AND REPLACEMENT PROCEDURES .....................................5-49
Top Cover Assembly ..................................................................................5-49
Top Cover Removal ...........................................................................5-49
Top Cover Replacement .....................................................................5-49
Rear Panel Assembly, Disk Drive 0 Enclosure ............................................5-49
Rear Panel Assembly Removal ...........................................................5-49
Rear Panel Assembly Replacement.....................................................5-53
Rear Panel, Disk Drive 1Enclosure............................................................5-53
Rear Panel Removal...........................................................................5-53
Rear Panel Replacement.....................................................................5-53
TIM Group Assembly ................................................................................5-53
v

5.3.4.1
5.3.4.2
5.3.5
5.3.5.1
5.3.5.2
5.3.5.3
5.3.6
5.3.6.1
5.3.6.2
5.3.6.3
5.3.6.4
5.3.7
5.3.7.1
5.3.7.2
5.3.7.3
5.3.7.4
5.3.8
5.3.8.1
5.3.8.2
5.3.9
5.3.9.1
5.3.9.2
5.3.10
5.3.10.1
5.3.10.2
5.3.10.3
5.3.11
5.3.11.1
5.3.11.2
5.3.11.3
5.3.12
5.3.12.1
5.3.12.2
5.3.13
5.3.13.1
5.3.13.2
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
CONTENTS (Cont)
Page
TIM Group Assembly Removal..........................................................5-54
TIM Group Assembly Replacement ...................................................5-54
RAM Module.............................................................................................5-56
RAM Module Removal......................................................................5-56
RAM Module ROM IC Installation ................................................... 5-58
RAM Module Replacement................................................................5-60
Peripheral Module...................................................................................... 5-61
Peripheral Module Removal............................................................... 5-61
Peripheral Module USART IC Installation......................................... 5-63
Jumper Lead Installation....................................................................5-64
Peripheral Module Replacement.........................................................
5-65
Intelligence Module.................................................................................... 5-65
Intelligence Module Removal ...........................;................................. 5-65
ROM IC Installation ..........................................................................5-66
Jumper Lead Installation....................................................................5-66
Intelligence Module Installation .........................................................
5-68
Standard EIA Module ................................................................................ 5-68
Standard EIA Module Removal ......................................................... 5-68
Standard EIA Module Replacement ................................................... 5-68
Cluster EIA Module................................................................................... 5-68
Cluster EIA Module Removal ............................................................5-70
Cluster EIA Module Replacement ......................................................5-70
Disk Controller Module .............................................................................5-70
Disk Controller Module Removal.......................................................5-70
Disk Controller ROM IC Installation................................................. 5-71
Disk Controller Module Replacement ................................................5-74
Power Supply Assembly..............................................................................5-74
Power Supply Assembly Removal.......................................................
5-75
Power Supply Module Installation...................................................... 5-75
Power Supply Assembly Installation ...................................................5-78
Disk Drive 0 Assembly ...............................................................................
5-78
Disk Drive 0 Assembly Removal......................................................... 5-78
Disk Drive 0 Assembly Replacement ..................................................5-82
Disk Drive 1Assembly ....................................;..........................................5-82
Disk Drive 1Assembly Removal.........................................................5-82
Disk Drive 1Assembly Replacement ..................................................
5-83
MODULE AND ASSEMBLY COMPONENT LOCATIONS AND
SIGNALS..........................................................................................................5-84
Removable Module ICs..............................................................................5-84
Intelligence Module, Functional Layout and Signals...................................5-84
RAM Module, Functional Layout and Signals ...........................................5-84
Peripheral Module, Functional Layout and Signals.....................................
5-85
Standard EIA Module, Functional Layout and Signals ............................... 5-85
Cluster EIA Module, Functional Layout and Signals..................................5-85
Disk Controller Module, Functional Layout and Signals ............................
5-85
Power Supply Module, Component Layout ................................................ 5-85
VI

5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.1.5
5.5.2
5.5.3
CHAPTER 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.4.2.3
6.4.2.4
6.4.3
6.4.4
6.4.4.1
6.4.4.2
6.4.4.3
6.4.4.4
6.4.5
6.4.5.1
6.4.5.2
6.4.5.3
6.4.5.4
6.4.5.5
CONTENTS (Cont)
Page
DISK
DRIVE ASSEMBLY, FUNCTIONS AND ADJUSTMENTS ..............5-114
Mechanical Functions...............................................................................5-114
Spindle Rotation Mechanism ............................................................5-116
Flexible Disk Spindle Engagement....................................................5-116
Read/Write Head Positioning...........................................................5-118
Head Load Solenoid and·Actuator....................................................5-118
Track
00 and Index Hole Detectors...................................................5-118
Drive Belt and Pulley Alignment ...............................................................5-119
Disk Drive Assembly,
60 Hz to 50 Hz Conversion.....................................5-120
PROGRAMMING INFORMATION
SYSTEM CHARACTERISTICS ........................................................................ 6-1
PERIPHERAL DEVICE COMMUNICATION ................................................. 6-3
Console Device............................................................................................. 6-3
Communications Modem ............................................................................. 6-3
Line Printer Terminal................................................................................... 6-3
Cluster Option Terminals ............................................................................. 6-3
Power-Up and Manual Reset Conditions......................................................6-4
Programmed Reset Instruction (Initialize) ....................................................6-4
DEVICE
AND INTERRUPT VECTOR ADDRESS ASSIGNMENTS ..............6-4
USART Parameter Control Register Address...............................................6-6
Standard Terminal Addresses .......................................................................6-6
Optional (Cluster) Terminal Addresses .........................................................6-6
Disk Drive Addresses ...................................................................................6-6
Line Time Clock Addresses ..........................................................................6-6
STANDARD TERMINAL REGISTER FORMATS .........................................6-9
USART Parameter Register .........................................................................6-9
Console Device Interface ............................................................................6-12
Receiver Control/Status Register (RCSR)..........................................6-12
Receiver
Data Buffer (RBUF) ............................................................6-12
Transmitter
Control/Status Register (XCSR).....................................6-12
Transmitter
Data Buffer (XBUF) .......................................................6-12
Communications Interface (Modem) ..........................................................6-12
Asynchronous Modem Interface.................................................................6-16
Asynchronous Receiver
Control/Status Register (RCSR)...................6-16
Asynchronous Receiver
Data Buffer (RBUF) .....................................6-16
Asynchronous Transmitter
Control/Status Register
(XCSR) ..............................................................................................6-16
Asynchronous Transmitter
Data Buffer (XBUF) ................................6-16
Synchronous Modem Interface.........0
......................................................... 6-22
Parameter Control Register (PARCSR)..............................................6-22
Synchronous Receiver
Control/Status Register (RXCSR) ..................6-22
Synchronous Receiver
Data Buffer (RXDBUF) ..................................6-22
Synchronous Transmitter Control and Status Register
(TXCSR)............................................................................................6-22
Synchronous Transmitter
Data Buffer (TXDBUF) .............................6-22
V11

6.4.6
6.4.6.1
6.4.6.2
6.5
6.6
6.6.1
6.6.2
6.6.3
6.7
APPENDIX A
APPENDIXB
INDEX
Figure No.
1-1
1-2
2-1
2-2
2-3
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
CONTENTS (Cont)
Page
PrinterTerminal Interface .......................................................................... 6-31
Printer Control/Status Register (LPCSR)........................................... 6-31
Printer Data Buffer (LPDSR) ............................................................. 6-31
OPTIONAL TERMINAL REGISTER WORD FORMATS .............................6-33
DISK DRIVE REGISTER FORMATS .............................................................6-33
Drive Control/Status Register (RXCS).......................................................6-33
Disk Controller Data Buffer Register (RXDB) ...........................................6-37
Disk Controller Track and Sector Register (RXSA)....................................6-39
LINE TIME CLOCK (LTC)..............................................................................6-39
PDT-II/I50 COMPONENT PART LIST
GLOSSARY AND NOTATION
FIGURES
Title
Page
Typical PDT-II/ISO Flexible (Floppy) Disk Operating System ............................ 1-2
PDT-II/ISO Model Designations......................................................................... 1-3
PDT-II/ISO Unpacking Procedure ......................................................................2-2
PDT-II/ISO Single and Dual Disk Unit Dimensions............................................2-4
Rear Panel Assembly, Component and Connector Locations ...............................2-6
Front Panel Indicators ......................................................................................... 3-1
Loading the Disk into the Disk Drive ...................................................................3-5
Loopback Connector Installation.........................................................................3-6
PDT-II/ISO, Simplified Block Diagram ...............................................................4-2
PDT-II/ISO Bus Structure...................................................................................4-5
PDT-II/ISO Internal Signal Distribution .............................................................4-9
Intelligence Module, Simplified Function Diagram .............................................4-13
8085 I/O Microprocessor, Memory and Device Select Logic,
Simplified
Diagram ............................................................................................4-19
Power-up and Manual Reset Logic, Simplified Diagram.....................................4-22
IPL and Control Logic, Simplified Diagram .......................................................4-24
LSI-1I Microprocessor, Simplified Block Diagram .............................................4-25
Clock Pulse Generator and Power Inverter,
Simplified Block Diagram ..................................................................................
4-27
LSI-II Microprocessor, I/O Transfer Timing.....................................................4-29
Output Transfer Events ......................................................................................4-31
Input Transfer Events.........................................................................................4-32
Interrupt Transfer Events ...................................................................................4-34
LSI-II I/O Device Address Decoding Logic,
Simplified
Diagram ............................................................................................4-35
viii

Figure No.
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
4-48
4-49
4-50
4-51
4-52
5-1
5-2
5-3
5-4
5-5
FIGURES (Cont)
Title
Page
Function Control, Fast DIN and Interrupt Request Logic..................................4-37
RAM Module, Simplified Function Diagram .....................................................4-41
RAM Module, Memory Matrix Configurations .................................................4-43
Memory Address
Word Formats ........................................................................4-45
Bank Select Decoder Logic .................................................................................4-46
Row
/Column and Address Multiplexer, Control Logic ......................................4-48
Row /Column and Address Multiplexer, Timing Diagram ..................................4-49
Peripheral Module, Simplified Function Diagram ..............................................4-52
Front Panel Indicator Logic, Simplified Diagram ...............................................4-58
Standard EIA Module, Simplified Diagram........................................................4-63
Cluster EIA Module, Simplified Diagram...........................................................4-64
Flexible Disk
and Envelope ................................................................................4-66
Flexible Disk, Track and Sector Information......................................................4-67
Double Frequency (FM) Data Recording Pattern...............................................4-69
Double Frequency
(FM) Address Mark Pattern .................................................4-69
Disk Controller Module, Simplified Function Diagram......................................4-71
Self-Test Function Select
and Display, Simplified Diagram.................................4-75
Head Load Control
and Track and Index Hole Detection...................................4-77
Step Generator Circuit, Simplified Diagram .......................................................4-80
Step Generator Circuit, Timing Diagram............................................................4-81
Stepper Motor Control and Drive Logic (Revision K),
Simplified Diagram ............................................................................................4-83
Stepper
Motor Control and Drive Logic, Timing Diagram .................................4-84
Stepper Motor Control and Drive Logic (Revision L),
Simplified Diagram .............................................................................................4-85
Read/Write Head and Control Circuits, Simplified Diagram..............................4-88
Read Amplifier
and Data Separator Circuit (Revision K),
Simplified Diagram ............................................................................................4-90
Read Amplifier and Differentiator Circuit (Revision K),
Timing Diagram.................................................................................................4-91
Data Separator Circuit (Revision K), Timing Diagram .......................................4-92
Read Amplifier
and Data Separator Circuit (Revision L),
Simplified Diagram ............................................................................................4-94
Read Amplifier and Differentiator Circuit (Revision K),
Timing Diagram.................................................................................................4-95
Data SeparatorCircuit (Revision L), Timing Diagram........................................4-96
8- Bit Binary Counter Configuration and Load Counts........................................4-98
13- and 17-Count Intervals, Timing Diagram......................................................4-99
H7833 Power Supply, Simplified Block Diagram ..............................................4-101
115 V ac, Voltage Doubler Circuit, Simplified Diagram ....................................4-103
230 V ac, Full Wave Rectifier Circuit, Simplified Diagram ................................4-103
Flyback Inverter Circuit, Simplified Diagram ...................................................4-105
Output Control Circuit, Simplified Diagram.................................................... .4-1 06
Control Circuit, Timing Diagram .................................................................... .4-1 07
Self-Test LED Indicator Locations.......................................................................5-5
Self-Test Sequence Chart ......................................................................................5-6
PDT-ll/ 150 Internal Cables and Connectors .....................................................5-29
Internal ac Cables and Connectors, 50 Hz Units .................................................5-30
AC/DC Power Distribution, 60 Hz Units ...........................................................5-32
IX

Figure No.
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
6-1
FIGURES (Cont)
Title
Page
Rear Panel Assembly, ac Cable Pin Locations.....................................................5-34
Power Supply ac Cable, Connector Pin Locations...............................................5-35
AC Power Distribution, 50 Hz Units ..................................................................5-36
50 Hz Internal Cable Configurations ..................................................................5-37
Disk Drive Assembly, ac Cable Connector Pin Locations ...................................5-39
Power Supply, Connector Pins and Voltage ........................................................ 5-41
DC Power Distribution Cable, Connector Pip Locations ....................................5-42
Disk Controller Module,
Connector Pins and dc Voltages ..................................5-43
Intelligence Module,
Connector Pins and dc Voltages.........................................5-44
RAM Module, Connector Pins and dc Voltages..................................................5-45
Peripheral Module, Connector Pins and dc Voltages...........................................5-46
Standard EIA and Cluster EIA Modules, Connector Pins
and dc Voltages ..................................................................................................5-47
Cable Extender, Module Location
and Connections ...........................................5-48
PDT-ll/ 150 Removal and Replacement Reference Chart...................................5-50
Top Cover and TIM Group Assembly, Removal and Replacement..................... 5-51
Rear Panel Assembly, Removal and Replacement ..............................................5-52
TIM Group Assembly Connections.....................................................................5-55
RAM Module, Removal and Replacement.........................................................5-57
RAM Module, ROM IC Removal and Replacement ..........................................5-58
ROM IC, Pin Alignment and Mounting .............................................................5-59
Peripheral Module, Removal and Replacement ..................................................5-62
Peripheral Module, USART Locations..... ~ .........................................................5-63
Peripheral Module, Jumper Lead Locations .......................................................5-64
Intelligence Module,
ROM IC and Jumper Lead Locations ....:...........................5-67
Standard EIA and Cluster EIA Modules, Removal
and Replacement................................................................................................5-69
Disk Drive Cable Routing ..................................................................................5-72
Disk Controller Module,
ROM IC Location.......................................................5-73
Power Supply Assembly, Removal and Replacement..........................................5-76
Power Supply Module, Removal and Replacement.............................................5-77
Disk Drive
Ground Lead and ac Cable Connections...........................................5-79
Disk Drive
and Enclosure Mounting ..................................................................5-80
Front Bezel, Removal and Replacement ............................................................. 5-81
Intelligence Module, Functional Layout.............................................................5-86
RAM Module, Functional Layout......................................................................5-87
Peripheral Module, Functional Layout..~ ............................................................5-88
Standard EIA Module, Functional Layout .........................................................5-89
Cluster EIA Module, Functional Layout ................................
~ ...........................5-90
Disk Controller Module (Revision K), Functional Layout.................................. 5-91
Disk Controller Module (Revision L), Functional Layout ..................................5-92
Power Supply Module, Component Locations....................................................5-93
Disk Drive Assembly,
Component Locations....................................................5-114
Disk Drive Assembly, Wiring Diagram.............................................................5-115
Spindle
Rotation Mechanism............................................................................5-116
Centering Cone
and Spindle Drive Components ...............................................5-117
Read/Write Head Positioning Mechanism........................................................5-118
Pulley Alignment..............................................................................................5-119
PDT-ll/ 150 Program Development System .........................................................6-2
x

Figure No.
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
Table No.
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
FIGURES (Coot)
Title
Page
PDT-ll/150 Device Register Address Assignments..............................................6-5
USART Parameter Control Register UPCSR Format ..........................................6-9
Console Terminal Interface Register Formats.....................................................6-13
Communication Interface, Asynchronous/Synchronous Select...........................6-15
Asynchronous Communications Interface Register
Formats ................................6-17
Synchronous Communications Interface Register
Formats .................................6-23
Synchronous Communications ParameterControl Register
Format ...............................................................................................................6-24
Printer Terminal Interface Register Formats ....................................................... 6-31
Disk Drive Interface Register Formats ...............................................................6-34
Line Time Clock (TCSR)
Format .......................................................................6-40
TABLES
Title Page
PDT-ll/ 150 Available Hardware Options............................................................ 1-4
PDT-ll/150 Equipment Specifications................................................................. 1-5
Flexible Disk Specifications.................................................................................. 1-7
PDT-ll/ 150 Engineering Specifications ............................................................... 1-7
PDT-ll/150 Publications..................................................................................... 1-8
Vendor IC Reference Documentation................................................................... 1-9
DIGITAL LSI-II Microprocessor IC Specifications........................................... l-11
PDT-ll/ 150 Engineering Circuit Schematics......................................................1-12
AC Power Requirements......................................................................................2-5
Rear Panel Device Connector Assignments ..........................................................2-6
Available Device Cable Assemblies ......................................................................2-7
Standard EIA Connector Signals..............................,................ ~ ...........................2-8
Cluster EIA
Option Connector Signals .................................................................2-9
Front Panel Indicators .........................................................................................3-2
Rear Panel Switches and Fuse ..............................................................................3-2
Function Switch Positions During Self-Test..........................................................3-3
Function Switch Selections...................................................................................3-3
8259 Interrupt
and Priority Assignments.............................................................4-17
8085 Memory Select Decoding............................................................................4-18
8085 I/O Device Select Decoding........................................................................4-20
Function Decoder Outputs .................................................................................4-38
RAM Module Designations and Jumper Configurations ....................................4-43
USART Register Addressing..............................................................................4-53
Console
USAR T Signals ....................................................................................4-54
Modem
USART Signals..................................................................................... 4-~5
Printer USART Signals ......................................................................................4-56
USART Signals for Terminals No. I-No.3 ........................................................4-57
Function Switch (SI) Signals ..............................................................................4-59
Standard EIA Module Interface Signals..............................................................4-60
Cluster EIA Module Interface Signals........... ~ .....................................................4-64
8085 Controller Microprocessor Interrupt Request.............................................4-73
8085 Controller Microprocessor Address Decoding............................................4-73
Xl

Table No.
4-16
4-17
4-18
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
TABLES (Coot)
Title Page
Self-Test Function Select
and Octal Code ...........................................................4-76
E23 Decoder/Driver Functions ..........................................................................4-86
FD1771 Register Selection..................................................................................4-87
PDT-ll/150 Fault Isolation Chart .......................................................................5-2
TIM Group Assembly Fault Indications...............................................................5-9
Disk Controller Module Fault Indications (Phase
1) ...........................................5-16
Disk Controller Module Fault Indications (Phase
2) ...........................................5-17
LSI-II Microprocessor and RAM Module Fault Indications..............................5-19
Switch Register (SWR) Functions.......................................................................5-22
Device
Map (DEVM) Options............................................................................5-24
Removable Module ICs......................................................................................5-94
Intelligence ModuleJ1Connector Signals...........................................................5-95
Intelligence ModuleJ2 Connector Signals...........................................................5-96
Intelligence Module J3 Connector Signals...........................................................5-97
Intelligence ModuleJ4 Connector Signals...........................................................5-99
Intelligence ModuleJ5 Connector Signals.........................................................
5-1 01
RAM Module Jl Connector Signals .................................................................5-102
RAM ModuleJ2 Connector Signals .................................................................5-104
Peripheral ModuleJ1Connector Signals........................................................... 5-1 05
Peripheral ModuleJ2 Connector Signals...........................................................5-107
Peripheral Module J3 Connector Signals...........................................................5-109
Peripheral Module J4 Connector Signals........................................................... 5-11 0
Standard EIA Module J4 Connector Signals..................................................... 5-111
Cluster EIA Module J4 Connector Signals.........................................................5-112
Disk Controller Module J1Connector Signals ..................................................5-113
Maximum Device Baud
Rate ................................................................................ 6-3
Preselected Device Parameters..............................................................................6-4
Standard Device and Vector Addresses.................................................................
6- 7
Optional (Cluster) Terminals, Device and Vector Addresses ................................. 6-8
Disk Drive, Device and Vector Addresses............................................................. 6-9
LineTime Clock, Device and Vector Address .......................................................6-9
USART Parameter Register Bit Descriptions .....................................................6-10
Console Interface, Receiver Register Bit Descriptions.........................................6-12
Console Interface, Transmitter Register Bit Descriptions....................................6-14
Asynchronous Communication,
RCSR Bit Descriptions ....................................6-18
Asynchronous Communications,
RBUF Bit Descriptions...................................6-20
Asynchronous Communications, XCSR Bit Assignments................................... 6-21
Asynchronous Communications, XBUF Bit Descriptions................................... 6-21
Parameter Control Register, PARCSR Bit Descriptions .....................................6-25
Synchronous Communications,
RXCSR Bit Descriptions ..................................6-26
Synchronous Communications,
RXDBUF Bit Descriptions...............................6-28
Synchronous Communications,
TXCSR Bit Assignments...................................6-29
Synchronous Communications,
TXDBUF Bit Assignments ...............................6-30
PrinterInterface, LPCSR Bit Descriptions..........................................................6-32
Printer Interface, LPDSR Bit Descriptions .........;...............................................6-32
Disk Controller, RXCS Bit Descriptions ............................................................6-35
Disk Controller, RXDB Bit Descriptions............................................................6-37
Disk Controller, RXES Bit Descriptions.............................................................
6-38
Disk Controller, RXSA Bit Descriptions ............................................................6-39
LineTime Clock ControlfStatus Register (TCSR)..............................................6-39
XlI

PDT-11/150 DUAL DISK
DRIVE UNIT
VT100 CONSOLE TERMINAL
Ei@i!t@!"jit.I.j

PREFACE
The PDT -11 / 150 is an LSI-II microprocessor-based unit that contains one (or two) flexible (floppy)
disk drive(s) for program loading and data storage. The unit is available with one of several console
devices, each forming a complete programmable system.
This manual defines these systems
and provides the technical information required to install them,
monitor their performance, and isolate the malfunctions that may occur in each. Also included are
general and detailed descriptions of the operation of the modules and assemblies.
Chapter 1 provides a general description
of a PDT-II/ISO system containing an operator's console and
terminals. Also discussed are the features and capabilities of the system and the equipment specifica-
tions
and options available.
Chapter 2 shows how to install the unit, connect the peripheral devices
and initiate the internal self-test
program.
Chapter 3 describes the functions
of the operator controls and indicators, the loading of the flexible
disk into the disk drive, the initiation of the self-test program, and the loading of the system programs
contained on the flexible disk.
Chapter 4 provides a general description of the functional operation of the entire unit and detailed
descriptions
of the operations of each module and assembly.
Chapter 5 contains detailed information
on initiating the diagnostic program (on disk) and evaluating
its performance. Also discussed are the removal, replacement and repair of assemblies and modules,
and disk drive adjustments.
Chapter 6 describes the
hardware characteristics of the PDT-II/ISO and includes the addresses as-
signed to the internal registers, detailed descriptions of the register bit functions, and programming
considerations.
Appendix A lists the
PDT-II/ISO component parts and their part numbers.
Appendix B
is a glossary of terms and notation used in this manual.
xv

CHAPTER 1
INTRODUCTION
The PDT -11 / 150 is a small, user-programmable, intelligent terminal that contains a dual flexible
(floppy) disk drive assembly for program loading
and data storage. The basic unit can communicate
with a console terminal, a modem,
and a line printer. With the addition of the Cluster EIA (Electronic
Industries Association) option, three additional terminals can be connected
to operate with the POT-
11/150.
All terminals and devices transfer serial data that conforms to the requirements of EIA standard RS-
232-C.
The POT-l1/150 is available with 16K- or 30K-word resident RAM and can be programmed using the
standard LSI-II microprocessor instruction set. Programs can be developed by using a PO P-l1/V03
hardware system (or equivalent) running under the RT-ll/V3B software operating system.
1.1 TYPICAL SYSTEM CONFIGURATIONS
Figure 1-1 shows a typical POT-ll/150 hardware system with the maximum number of terminals and
devices attached. The Standard EIA Converter enables data transfer rates of up to 9.6K baud for the
console and line printer terminal. The communications modem operates asynchronously
or synchro-
nously with Bell 103, 113, 202, 212
data sets (or equivalents) in full- or half-duplex operatiQn.
The Cluster EIA converter provides the additional interfaces and connectors required to attach three
character printers
or video display units (VOUs). The maximum data transfer rates of these terminals
is 2.4K baud.
The data transfer rates to and from the devices and terminals depend on the applications program or
operating system and the nurnber and types of peripheral units connected to the PDT-II /150. Refer to
Paragraph 6.2 for detailed information on data transfer rates.
Model Designations
The PDT-II /150 is available with or without a console terminal and is wired to operate with either 50
Hz or 60 Hz ac input power. Any of the options listed in Table 1-1 may also be included.
The model designation specifies the system and unit configurtains of the PDT-II /150 delivered. The
designation is stamped on a metallic label attached to the rear panel of the unit. Figure 1-2 describes
the model designations and the equipment and options included.
1-1

PDT-11/150
DUAL
DISK
PROGRAMMABLE
DATA
TERMINAL
STANDARD
EIA
CONVERTER
CLUSTER
EIA J2
CONVERTER
CONSOLE
TERMINAL
(EIA)
50-9.6K BAUD
PRINTER
TERMINAL
(EIA)
50-9.6K BAUD
MODEM
BELL 103/113
203/212
HALF/FULL DUPLEX
----------------TELEPHONE
TERMINAL
NO 1
(EIA)
50-2.4K BAUD
TERMINAL
NO 2
(EIA)
50-2.4K BAUD
TERMINAL
N03
(EIA)
50-2.4K BAUD
L1NEI
MA-3574
Figure 1-1 Typical PDT-II / 150 Flexible (Floppy) Disk
Operating System
1-2

PDT-11/15 x-xx
...------I
T JI
r_----A'----_\t_-~A ..... --_".----------"'A-------,
CONSOLE RAM MEMORY AC
TERMINAL
OPTION (BYTES)
POWER INPUT
O=NONE
A=MST11-AB (16K) A=120 V 160 HZ
1=VT100-AA C=120 V/60
HZ
2=LA 120-AA, -BA B=MST11-AC (32K)
B=
*
150 HZ
3=LA34-DA
D=
*
150 HZ
4=LS120-HE C=MST11-AD (60K) E=120 V/60 HZ
5=LA36-HE H=120 V
160 HZ
F=
*
150 HZ
J= *
150 HZ
* AVAILABLE IN THE FOLLOWING VOLTAGE
RATINGS: 90-120 VAC, 100-132 VAC,
180-240 VAC, 200-264 VAC
CLUSTER
EIA OPTION
NONE
DFT11-AB
NONE
DFT11-AB
NONE
DFT11-AB
NONE
DFT11-AB
EXAMPLE: IPDT-11/151-BH IINCLUDES THE FOLLOWING
• VT100-AA CONSOLE
TERMINAL
• MST11-AC OPTION (32K BYTES OF RAM)
• 120 V/60 HZ AC POWER INPUT
DISK DRIVE
OPTION
} NONE
} RXT01-AA
} RXT01-AC
• DFT11-AB OPTION (THREE EIA TERM!NAL INTERFACES)
RXT01-AA OPTION (SECOND DISK DRIVE)
MR-2330
Figure 1-2 PDT-II/ISO Model Designations
1-3