Digital Equipment PDT 11/150 User manual

PDT
III
TECHNICAL MANUAL

EK·PT150·TM·001
PDT -11/150
TECHNICAL MANUAL
digital equipment corporation • marlboro, massachusetts

Copyright © 1980 by Digital Equipment Corporation
All Rights Reserved
The material in this manual is for informational pur-
poses
and is subject to change without notice.
Digital Equipment
Corporation assumes no responsi-
bility for any errors which may appear in this manual.
Printed in U.S.A.
1st Edition, April 1980
This document was set on DIGITAL's DECset-8000 computerized
typesetting system.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS
DECLAB
DECsystem-10
DECSYSTEM-20
DIBOL
EduSystem
VAX
VMS
MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS
MINC-II

PREFACE
CHAPTER 1
1.1
1.2
1.3
1.3.1
1.3.2
1.4
CHAPTER 2
2.1
2.2
2.2.1
2.2.2
2.2.2.1
2.2.2.2
2.3
CHAPTER 3
3.1
3.1.1
3.1.2
3.1.3
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
CHAPTER 4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
. 4.1.5
4.1.6
4.1.7
4.2
4.3
CONTENTS
Page
INTRODUCTION
TYPICAL SYSTEM
CONFIGURA TIONS........................................................ 1-1
EQUIPMENT AND MEDIA SPECIFICATIONS .............................................1-4
RELATED PUBLICATIONS............................................................................. 1-4
Ordering Information for DIGITAL Personnel ............................................ 1-8
Ordering Information for Customers............................................................ 1-8
TECHNICAL REFERENCE MATERIAL ........................................................ 1-9
UNPACKING/INSTALLATION
UNPACKING AND INSPECTION................................................................... 2-1
SITE PREPARATION AND CONNECTIONS ................................................. 2-3
AC Power Requirements .............................................................................. 2-3
Serial Line Cable Connectors........................................................................ 2-5
EIA Connector Pin Assignments .................. ~ ....................................... 2-5
Serial Line Cable Lengths.....................................................................2-5
SERIAL
LINE DATA CHARACTERISTICS .................................................... 2-5
OPERATING PROCEDURES
SWITCHES AND INDICATORS ...................................................................... 3-1
Front Panel Indicators.................................................................................. 3-1
Rear Panel Switches and Components .......................................................... 3-1
Function Switch ...........................................................................................3-2
DISK HANDLING AND STORAGE ................................................................3-4
TEST PROCEDURES ........................................................................................3-4
Preliminary Setup.........................................................................................3-6
Optional Loopback Connector.....................................................................3-6
Self-Test Procedures.....................................................................................
3-7
Loading a System Program........................................................................... 3-8
Changing a System Program.........................................................................3-9
TECHNICAL DESCRIPTION
GENERAL OPERATION .................................................................................. 4-1
Intelligence Module (KDT 11 )...................................................................... .4-1
RAM Module (MSTll) ................................................................................4-3
Peripheral Module (DLTll) .......................................................: .. -...............4-3
Standard and Cluster EIA Modules
(DFTll) ...............................................4-3
Disk Controller Module
(RXTl1) ................................................................4-3
Disk Drive Assemblies (RXTOl)...................................................................4-3
Power Supply Assembly (H7833) ..................................................................4-3
PDT-ll/150 BUS STRUCTURE ........................................................................4-4
SIGNAL DISTRIBUTION .................................................................................4-8
iii

404
404.1
404.2
404.3
40404
404.5
404.6
404.7
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.5.1.4
4.5.1.5
4.5.1.6
4.5.2
4.5.3
4.5.3.1
4.5.3.2
4.5.3.3
4.5.3.4
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.2
4.9
4.9.1
4.9.1.1
4.9.1.2
4.9.2
4.9.2.1
4.9.2.2
4.9.2.3
CONTENTS (Coot)
Page
SYSTEM OPERATION......................................................................................4-8
Power-Up Functions .....................................................................................4-8
I/O Microprocessor Control.......................................................................4-10
Data Transfer Operations.....................................,..................................... 4-1 0
LSI-II Resident Memory............................................................................
4-11
Peripheral Device Interface........................................................................ .4-11
EIA/TTL Level Converters.........................................................................4-12
Disk Controller ..........................................................................................4-12
INTELLIGENCE MODULE FUNCTIONS (DWG. NO. 5413271)..................4-12
8085 I/O Microprocessor and Associated Logic......................................... o4-16
8085 I/O Transfers .............................................................................4-16
Interrupts and Priority Assignments ...................................................4-16
8155 I/O Port and RAM Functions ....................................................4-17
Test Indicator Register .......................................................................4-18
8085 Memory and I/O Select Address Decoding.................................4-18
Power-Up and Manual Reset..............................................................
4-21
Inter-Processor Link (IPL) and Control Logic ............................................4-23
LSI-II Microprocessor and Associated Logic .............................................4-23
Clock Pulse Generator and Power Inverter ........................................
04-26
LSI-II I/O Transfer Sequence ........................................................... .4-28
LSI-II I/O Device Address Decoding................................................ .4-33
Function Control, Fast-Data-In and Interrupt
Request Logic.....................................................................................4-36
RAM
MODULE FUNCTIONS (DWG. NO. 5413275) .....................................4-40
RAM Matrix Configurations...................................................................... 4-43
Address Bus Distribution............................................................................4-44
Bank Select Decoder Logic .........................................................................4-44
Row/Column and Address MUltiplexer Logic ...........................................
04-47
RAM Refresh Logic ...................................................................................4-50
RAM Read or Write Operations................................................................ o4-50
Reply Logic................................................................................................4-50
PERIPHERAL MODULE FUNCTIONS (DWG. NO. 5413269) ..................... .4-51
Information Transfers ................................................................................ 4-51
Standard Device USARTs ..........................................................................4-53
Optional Device USARTs ..........................................................................4-57
Front Panel Indicators................................................................................4-58
Function Switch Selections.........................................................................4-59
EIA/TTL LEVEL CONVERTER FUNCTIONS ............................................. .4-59
Standard EIA Module Functions (DWG. NO. 5413267) .............................4-60
Cluster EIA Module Functions (DWG. NO. 5413427) ........................;.......4-64
FLEXIBLE DISK DESCRIPTION......................................;...........................
04-66
Recording Format ......................................................................................4-67
Header Field.......................................................................................4-68
Data Field ..........................................................................................4-68
Recording Method .....................................................................................4-68
Data Recording Patterns .................................................................... 4-68
Data and Address Mark Recording ................................................... .4-68
Synchronizing Fields ............................·..............................................4- 70
iv

4.10
4.10.1
4.10.1.1
4.10.1.2
4.10.2
4.10.3
4.10.4
4.10.5
4.10.5.1
4.10.5.2
4.10.6
4.10.6.1
4.10.6.2
4.11
4.11.1
4.11.1.1
4.11.1.2
4.11.2
4.11.3
4.11.3.1
4.11.3.2
4.11.3.3
CHAPTER 5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.2
5.3.2.1
5.3.2.2
5.3.3
5.3.3.1
5.3.3.2
5.3.4
CONTENTS (Cont)
Page
DISK CONTROLLER MODULE FUNCTIONS (DWG. NO. 5413273)..........4-70
8085 Controller Microprocessor .................................................................4-70
Power-up and Initialize Functions ......................................................4-73
Read
or Write Operations...................................................................4-74
Disk Drive Selections..................................................................................4-74
Self-Test Function Select and Indicator Logic.............................................4-
75
Head Load Control and Track/Index Hole Detection.................................4-76
Stepper Motor Direction and Control Logic ...............................................4-79
Stepper Motor Pulse Generation.........................................................4- 79
Stepper Motor Control and Drive Circuits..........................................4-82
FD 1771 Disk Controller and Associated Logic ...........................................4-86
Disk Write Operations........................................................................4-86
Disk Read Operations ........................................................................4-89
H7833
POWER SUPPLY MODULE (DWG. NO. 5413343)............................4-100
Input ac Voltage Circuits .......................................................................... 4-1 02
115 V ac Voltage Doubler Circuit......................................................4-102
230 V ac Full Wave Rectifier Circuit ................................................
.4-1 02
Flyback Inverter Circuit............................................................................ 4-1 04
Control Circuit......................................................................................... 4-1 04
Oscillator and Pulse Width Modulator..............................................4-107
Error Amplifier Circuit.....................................................................4-107
Current Limiter Circuit..................................................................... 4-1 08
SERVICE
PERFORMANCE TESTS AND FAULT ANALYSIS ....................................... 5-1
LED Indicator Locations .............................................................................5-4
Fault Isolation Procedures............................................................................5-4
Loading the System Exerciser Program.......................................................5-22
Exerciser Compatibility Test...........................
~ ...........................................5-26
Copying the System Exerciser Disk.............................................................5-27
Loading a System Program.........................................................................5-27
Changing a System Program.......................................................................5-28
POWER DISTRIBUTION ................................................................................5-28
Internal Cable and Connector Locations.....................................................5-28
Initial ac Power Checks...............................................................................
5-31
Initial de Power Checks ..............................................................................5-39
REMOVAL AND REPLACEMENT PROCEDURES .....................................5-49
Top Cover Assembly ..................................................................................5-49
Top Cover Removal ...........................................................................5-49
Top Cover Replacement .....................................................................5-49
Rear Panel Assembly, Disk Drive 0 Enclosure ............................................5-49
Rear Panel Assembly Removal ...........................................................5-49
Rear Panel Assembly Replacement.....................................................5-53
Rear Panel, Disk Drive 1Enclosure............................................................5-53
Rear Panel Removal...........................................................................5-53
Rear Panel Replacement.....................................................................5-53
TIM Group Assembly ................................................................................5-53
v

5.3.4.1
5.3.4.2
5.3.5
5.3.5.1
5.3.5.2
5.3.5.3
5.3.6
5.3.6.1
5.3.6.2
5.3.6.3
5.3.6.4
5.3.7
5.3.7.1
5.3.7.2
5.3.7.3
5.3.7.4
5.3.8
5.3.8.1
5.3.8.2
5.3.9
5.3.9.1
5.3.9.2
5.3.10
5.3.10.1
5.3.10.2
5.3.10.3
5.3.11
5.3.11.1
5.3.11.2
5.3.11.3
5.3.12
5.3.12.1
5.3.12.2
5.3.13
5.3.13.1
5.3.13.2
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
CONTENTS (Cont)
Page
TIM Group Assembly Removal..........................................................5-54
TIM Group Assembly Replacement ...................................................5-54
RAM Module.............................................................................................5-56
RAM Module Removal......................................................................5-56
RAM Module ROM IC Installation ................................................... 5-58
RAM Module Replacement................................................................5-60
Peripheral Module...................................................................................... 5-61
Peripheral Module Removal............................................................... 5-61
Peripheral Module USART IC Installation......................................... 5-63
Jumper Lead Installation....................................................................5-64
Peripheral Module Replacement.........................................................
5-65
Intelligence Module.................................................................................... 5-65
Intelligence Module Removal ...........................;................................. 5-65
ROM IC Installation ..........................................................................5-66
Jumper Lead Installation....................................................................5-66
Intelligence Module Installation .........................................................
5-68
Standard EIA Module ................................................................................ 5-68
Standard EIA Module Removal ......................................................... 5-68
Standard EIA Module Replacement ................................................... 5-68
Cluster EIA Module................................................................................... 5-68
Cluster EIA Module Removal ............................................................5-70
Cluster EIA Module Replacement ......................................................5-70
Disk Controller Module .............................................................................5-70
Disk Controller Module Removal.......................................................5-70
Disk Controller ROM IC Installation................................................. 5-71
Disk Controller Module Replacement ................................................5-74
Power Supply Assembly..............................................................................5-74
Power Supply Assembly Removal.......................................................
5-75
Power Supply Module Installation...................................................... 5-75
Power Supply Assembly Installation ...................................................5-78
Disk Drive 0 Assembly ...............................................................................
5-78
Disk Drive 0 Assembly Removal......................................................... 5-78
Disk Drive 0 Assembly Replacement ..................................................5-82
Disk Drive 1Assembly ....................................;..........................................5-82
Disk Drive 1Assembly Removal.........................................................5-82
Disk Drive 1Assembly Replacement ..................................................
5-83
MODULE AND ASSEMBLY COMPONENT LOCATIONS AND
SIGNALS..........................................................................................................5-84
Removable Module ICs..............................................................................5-84
Intelligence Module, Functional Layout and Signals...................................5-84
RAM Module, Functional Layout and Signals ...........................................5-84
Peripheral Module, Functional Layout and Signals.....................................
5-85
Standard EIA Module, Functional Layout and Signals ............................... 5-85
Cluster EIA Module, Functional Layout and Signals..................................5-85
Disk Controller Module, Functional Layout and Signals ............................
5-85
Power Supply Module, Component Layout ................................................ 5-85
VI

5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.1.5
5.5.2
5.5.3
CHAPTER 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.4.2.3
6.4.2.4
6.4.3
6.4.4
6.4.4.1
6.4.4.2
6.4.4.3
6.4.4.4
6.4.5
6.4.5.1
6.4.5.2
6.4.5.3
6.4.5.4
6.4.5.5
CONTENTS (Cont)
Page
DISK
DRIVE ASSEMBLY, FUNCTIONS AND ADJUSTMENTS ..............5-114
Mechanical Functions...............................................................................5-114
Spindle Rotation Mechanism ............................................................5-116
Flexible Disk Spindle Engagement....................................................5-116
Read/Write Head Positioning...........................................................5-118
Head Load Solenoid and·Actuator....................................................5-118
Track
00 and Index Hole Detectors...................................................5-118
Drive Belt and Pulley Alignment ...............................................................5-119
Disk Drive Assembly,
60 Hz to 50 Hz Conversion.....................................5-120
PROGRAMMING INFORMATION
SYSTEM CHARACTERISTICS ........................................................................ 6-1
PERIPHERAL DEVICE COMMUNICATION ................................................. 6-3
Console Device............................................................................................. 6-3
Communications Modem ............................................................................. 6-3
Line Printer Terminal................................................................................... 6-3
Cluster Option Terminals ............................................................................. 6-3
Power-Up and Manual Reset Conditions......................................................6-4
Programmed Reset Instruction (Initialize) ....................................................6-4
DEVICE
AND INTERRUPT VECTOR ADDRESS ASSIGNMENTS ..............6-4
USART Parameter Control Register Address...............................................6-6
Standard Terminal Addresses .......................................................................6-6
Optional (Cluster) Terminal Addresses .........................................................6-6
Disk Drive Addresses ...................................................................................6-6
Line Time Clock Addresses ..........................................................................6-6
STANDARD TERMINAL REGISTER FORMATS .........................................6-9
USART Parameter Register .........................................................................6-9
Console Device Interface ............................................................................6-12
Receiver Control/Status Register (RCSR)..........................................6-12
Receiver
Data Buffer (RBUF) ............................................................6-12
Transmitter
Control/Status Register (XCSR).....................................6-12
Transmitter
Data Buffer (XBUF) .......................................................6-12
Communications Interface (Modem) ..........................................................6-12
Asynchronous Modem Interface.................................................................6-16
Asynchronous Receiver
Control/Status Register (RCSR)...................6-16
Asynchronous Receiver
Data Buffer (RBUF) .....................................6-16
Asynchronous Transmitter
Control/Status Register
(XCSR) ..............................................................................................6-16
Asynchronous Transmitter
Data Buffer (XBUF) ................................6-16
Synchronous Modem Interface.........0
......................................................... 6-22
Parameter Control Register (PARCSR)..............................................6-22
Synchronous Receiver
Control/Status Register (RXCSR) ..................6-22
Synchronous Receiver
Data Buffer (RXDBUF) ..................................6-22
Synchronous Transmitter Control and Status Register
(TXCSR)............................................................................................6-22
Synchronous Transmitter
Data Buffer (TXDBUF) .............................6-22
V11

6.4.6
6.4.6.1
6.4.6.2
6.5
6.6
6.6.1
6.6.2
6.6.3
6.7
APPENDIX A
APPENDIXB
INDEX
Figure No.
1-1
1-2
2-1
2-2
2-3
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
CONTENTS (Cont)
Page
PrinterTerminal Interface .......................................................................... 6-31
Printer Control/Status Register (LPCSR)........................................... 6-31
Printer Data Buffer (LPDSR) ............................................................. 6-31
OPTIONAL TERMINAL REGISTER WORD FORMATS .............................6-33
DISK DRIVE REGISTER FORMATS .............................................................6-33
Drive Control/Status Register (RXCS).......................................................6-33
Disk Controller Data Buffer Register (RXDB) ...........................................6-37
Disk Controller Track and Sector Register (RXSA)....................................6-39
LINE TIME CLOCK (LTC)..............................................................................6-39
PDT-II/I50 COMPONENT PART LIST
GLOSSARY AND NOTATION
FIGURES
Title
Page
Typical PDT-II/ISO Flexible (Floppy) Disk Operating System ............................ 1-2
PDT-II/ISO Model Designations......................................................................... 1-3
PDT-II/ISO Unpacking Procedure ......................................................................2-2
PDT-II/ISO Single and Dual Disk Unit Dimensions............................................2-4
Rear Panel Assembly, Component and Connector Locations ...............................2-6
Front Panel Indicators ......................................................................................... 3-1
Loading the Disk into the Disk Drive ...................................................................3-5
Loopback Connector Installation.........................................................................3-6
PDT-II/ISO, Simplified Block Diagram ...............................................................4-2
PDT-II/ISO Bus Structure...................................................................................4-5
PDT-II/ISO Internal Signal Distribution .............................................................4-9
Intelligence Module, Simplified Function Diagram .............................................4-13
8085 I/O Microprocessor, Memory and Device Select Logic,
Simplified
Diagram ............................................................................................4-19
Power-up and Manual Reset Logic, Simplified Diagram.....................................4-22
IPL and Control Logic, Simplified Diagram .......................................................4-24
LSI-1I Microprocessor, Simplified Block Diagram .............................................4-25
Clock Pulse Generator and Power Inverter,
Simplified Block Diagram ..................................................................................
4-27
LSI-II Microprocessor, I/O Transfer Timing.....................................................4-29
Output Transfer Events ......................................................................................4-31
Input Transfer Events.........................................................................................4-32
Interrupt Transfer Events ...................................................................................4-34
LSI-II I/O Device Address Decoding Logic,
Simplified
Diagram ............................................................................................4-35
viii

Figure No.
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
4-48
4-49
4-50
4-51
4-52
5-1
5-2
5-3
5-4
5-5
FIGURES (Cont)
Title
Page
Function Control, Fast DIN and Interrupt Request Logic..................................4-37
RAM Module, Simplified Function Diagram .....................................................4-41
RAM Module, Memory Matrix Configurations .................................................4-43
Memory Address
Word Formats ........................................................................4-45
Bank Select Decoder Logic .................................................................................4-46
Row
/Column and Address Multiplexer, Control Logic ......................................4-48
Row /Column and Address Multiplexer, Timing Diagram ..................................4-49
Peripheral Module, Simplified Function Diagram ..............................................4-52
Front Panel Indicator Logic, Simplified Diagram ...............................................4-58
Standard EIA Module, Simplified Diagram........................................................4-63
Cluster EIA Module, Simplified Diagram...........................................................4-64
Flexible Disk
and Envelope ................................................................................4-66
Flexible Disk, Track and Sector Information......................................................4-67
Double Frequency (FM) Data Recording Pattern...............................................4-69
Double Frequency
(FM) Address Mark Pattern .................................................4-69
Disk Controller Module, Simplified Function Diagram......................................4-71
Self-Test Function Select
and Display, Simplified Diagram.................................4-75
Head Load Control
and Track and Index Hole Detection...................................4-77
Step Generator Circuit, Simplified Diagram .......................................................4-80
Step Generator Circuit, Timing Diagram............................................................4-81
Stepper Motor Control and Drive Logic (Revision K),
Simplified Diagram ............................................................................................4-83
Stepper
Motor Control and Drive Logic, Timing Diagram .................................4-84
Stepper Motor Control and Drive Logic (Revision L),
Simplified Diagram .............................................................................................4-85
Read/Write Head and Control Circuits, Simplified Diagram..............................4-88
Read Amplifier
and Data Separator Circuit (Revision K),
Simplified Diagram ............................................................................................4-90
Read Amplifier and Differentiator Circuit (Revision K),
Timing Diagram.................................................................................................4-91
Data Separator Circuit (Revision K), Timing Diagram .......................................4-92
Read Amplifier
and Data Separator Circuit (Revision L),
Simplified Diagram ............................................................................................4-94
Read Amplifier and Differentiator Circuit (Revision K),
Timing Diagram.................................................................................................4-95
Data SeparatorCircuit (Revision L), Timing Diagram........................................4-96
8- Bit Binary Counter Configuration and Load Counts........................................4-98
13- and 17-Count Intervals, Timing Diagram......................................................4-99
H7833 Power Supply, Simplified Block Diagram ..............................................4-101
115 V ac, Voltage Doubler Circuit, Simplified Diagram ....................................4-103
230 V ac, Full Wave Rectifier Circuit, Simplified Diagram ................................4-103
Flyback Inverter Circuit, Simplified Diagram ...................................................4-105
Output Control Circuit, Simplified Diagram.................................................... .4-1 06
Control Circuit, Timing Diagram .................................................................... .4-1 07
Self-Test LED Indicator Locations.......................................................................5-5
Self-Test Sequence Chart ......................................................................................5-6
PDT-ll/ 150 Internal Cables and Connectors .....................................................5-29
Internal ac Cables and Connectors, 50 Hz Units .................................................5-30
AC/DC Power Distribution, 60 Hz Units ...........................................................5-32
IX