Digital Equipment PDP-8 User manual

Digital
Equipment
Corporation
Maynard,
Massachusetts
PDP-8
Maintenance
Manual
DMO1
Data
Multiplexer
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lst
Printing
September
1967
2nd
Printing
September
1968
3rd
Printing
May
1969
4th
Printing
January
1970
Copyright
©
1967, 1968, 1969,
1970
by
Digital
Equipment
Corporation
The material
in
this manual is for
informa-
tion
purposes
and
is
subiect
to
change
with-
out notice.
The
following
are
trademarks of
Digital
Equipment
Corporation,
Maynard,
Massachusetts:
DEC PDP
FLIP
CHIP
FOCAL
DIGITAL COMPUTER
LAB

Chapter
1
2
3
3.1
3.2
3.2.]
3.2.2
3.2.3
3.2.4
5
6.1
6.1.1
6.2
7.1
7.2
7.3
8.1
Table
6-]
Figure
1-]
3-2
CONTENTS
Page
INTRODUCTION..........................
..... ...........
.
.....
.
l-l
SCOPE..
......
....... .2-1
OPERATION
................... . .. ............................
.
.....
3-1
General
.....
...............
....... ......3-i
Logic
Operation
..... . ............................
.
......
.
.......
3-1
Multiplexer
Control
(BS-D-DMOl-O-Z).
.. . . . . ............
.
.....
.
3-l
Level Production
from
Multiplexer
Control
(BS-D-DMOl-O-ll)
.....
3-3
Data
Address Line Selector
(BS-D-DMOl-0-4)
. .
. . .
. .
. . . . .
.
. .....
3-4
Data Bits
Line Selector
(BS-D-DMOl-0-3)
. .
.
. .
. .
.
.. .
.
. . . . .
. .
.
. ..
3-4
INTERFACE...... ....... .. ................ .................
4-]
POWER
SLJF’PLY
5-1
MAINTENANCE
................................................... .
6-]
Preventive
Maintenance
...... . .......... . . . . . .......... .
. . . .
..
. . .
6-]
Power
Supply
Checks .........................................
6-]
Corrective Maintenance
. . .
.
. ............. . ..................
'
.....
6-]
INSTALLATION
........ ............. ........... ........7-l
Mounting
......... . .............................................
7-1
Environmental
Conditions
. .............. .
... .
.
....................
7-l
Power
Requirements
. . ................... . .
.
.
.....................
7-l
SCHEMAT'ICS
........... . ............ . ...... .................
8-]
Semiconductor Substitution
........... . . ...
.
.
........
.
......
.
.
.
. . . .
8-1
TABLES
Type
728
Power
Supply Output
Checks
(Drawing
CS-B-728).
.
.
....... . . . . .
.
6-]
Semiconductor
Substitution
....... . ...... . . . . ... . . . ............
. ..... .
.
8—1
ILLUSTRATIONS
DMOl General
Block
Diagram......
......
........
l-l
DMOl
Data Break
Signals
.......
3-2
PDP-8
-
DMOl
Timing Diagram
.......
3-3

Figure
8-2
8-3
8-4
8-5
8-6
8-7
8—8
8-9
8—10
8-11
8-12
8-13
8—14
8-15
8-16
8-17
8—18
8-19
C O
N T
E N
T S
(continued)
Page
Power
Supply
(CS-B-728)
................ .
............................
8'2
Diode
Gate
(CS-B-Bl4l)
.............................................
8-2
Diode
Cluster
(RS-B-ROOZ)
.....................
8-3
Dual
Flip-Flop
(RS-B-R202)
...........................................
8-3
Invefler(CS-B-Sl07)
.................................................
8—4
Diode
Gate
(CS-B-Slll)
.............................................
8—4
DC
Carry
Chain
(RS-B-Sl8l)
..........................................
8-5
Dual
Flip-Flop
(CS-B-SZOZ)
...........................................
8-5
Clamped
Loads
(CS—B-W005)
..........................................
8—6
Signal
Cable Connector
(RS-B-W02l)
..................................
8—6
Pulse
Amplifier
(CS-B-W640)
.......................................... 8—7
Utilization
Module List
(UML-D-DMOl-O-S)
............................ 8-9
Multiplexer
Control
(BS-D-DMOl-O-Z)
.................................
8-H
Level Production
from
Multiplexer
Control
(BS-D-DMOl-O—ll)
.............
8-l3
Data
Address
Line
Selector
(BS-D-DMOl-0-4)
. .
.........................
8-15
Data Bits Line
Selector
(BS-D-DMOi-O—3)..............................;
8—17
DMOl
Interconnecting
Cable
Diagram
(IC-DMOl-O-l3)
................... 8—19
I/O
Connectors
(BS-D-DMOl—O-o)
.....................................
8-21
Data
Multiplexer
Connectors
(BS-D-DMOl-O-5)
..........................
8—23

CHAPTER]
INTRODUCTION
This
manual
covers
the maintenance
of the
data
multiplexer,
designated
as
Type
DMOl
,
now
in
production
at the
Digital
Equipment Corporation
of
Maynard,
Massachusetts.
The DMOl
is
essentially
a
switching
device
for use between the
PDP—8®and
a maximum of
seven
peripheral
or
I/O
devices,
as
shown in
figure
1-]
.
The.peripheral
devices include
high-speed
magnetic
tape
systems,
high-speed
drum
memories,
and
CRT
display
systems
containing
memory
elements,
all
of which use the PDP-8
data break
Facility.
MAXIMUM
or
SEVEN
PDP‘B
PERIPHERAL
DEVICES
DiviOi
DATA
MULTIPLEXER
P. 1 1 n In A I l I no
rlgure
l-l
UMUI
ueneral
BIOCK
Ungl‘Gm
®
PDP isfie
registered
trademark
of the
Programmed
Data Processor
manufactured
by
Digital
Equipment
Corporation
of
Maynard,
Massachusetts.
l-l

CHAPTERZ
SCOPE
TIA:1-
m
I
Type
DMOl . It
details
information on
logical
operation,
interface characteristics
and
connections,
and
installation
and
mounting
.
Uses
of
the
levels
and
pulses
produced
by
the
peripheral
devices
and
the
PDP-8
are not
covered
in this
manual.
For
further
information on such
signals,
reference to the
PDP-8
User's
Handbook
F-85
and instruction
manuals of the
specific peripheral
devices is advised
.
2-1

CHAPTER3
OPERATION
3
.l
GENERAL
The
Data
Multiplexer Type
DMOl,
as
noted,
acts
as
a
switch between the
PDP-8
and a
maximum
of
seven
high-speed peripheral
devices
which use
the
data
break
facility.
Whenever
a device
using
the data
break
facility
requests
a
break,
the
device
produces
a
number
of
signals.
As
figure
3—]
shows,
only
the
signals
from the selected
peripheral
device
pass
through
the
DMOl
into
the
PDP-8.
3
.2
LOGIC OPERATION
The
following
paragraphs
describe
the
logic
operation
of
the
DMOl Data
Multiplexer
as it re-
lates to the
PDP-8
and the
peripheral
devices connected
to
it.
(Each
maior
heading
references
directly
to an
engineering
drawing
found
in
chapter
8
of this
manual.)
3.2.l
Multiplexer
Control
(BS-D-DMOl-O—Z)
Figure
8-13
illustrates the
logic
control
circuitry
of the
DMOl
Data
MultipleXer.
Upon
receipt
of
PDP-8
timing
pulses
and a
BRK
REQ
(break
request)
level
from the
peripheral
device
requesting
the
data
break,
this control
logic
produces
MPX,
B
ENABLE,
and
BRK
REQ
levels and
ADD
ACC
(address
accepted)
pulse
.
For
ease
in
explanation,
it is
assumed
the
peripheral
device
producing
the
BRK
REQ
l
level
is
requesting
service.
Similar
operations
occur
when
other
peripheral
devices
request
data
breaks.
The
timing
diagram
in
figure
3-2 is used
in
coniunction
with the
multiplexer
control
descrip=
tion
.
During
the
PDP-8
turn-ion
period,
or
whenever
the
operator presses
the
START
key,
POWER
CLEAR
pulses
(=3v,
lOO-nsec
pulses
at
a
lO-kHz
rate)
clear
the
BREAK
IN
PROGRESS
(figure
8-4),
and
the
B
ENABLE,
and
MPX
flip-flops
(figure
8-8).
These
pulses
are
accepted,
and their function
imple—
mented,
without
the
need for device selection
through
addressing.
All
BRK
REQ
levels
enter the
DMOl
through
the
R002
diode network
(figure 8-3)
'at location
322
and
SI
ll
diode
gate
(figure
8-6)
at
823.
This
circuitry
is shown
in the
upper
right
corner of
the
drawing
.
The
ground
BRK
REQ
l
level
is
applied
to
terminal
L
of
the above
modules.
The
remaining
input
terminals
are at —3v
.

f
——
DAO—O THROUGH
DAM-O
——————-<>
—-
DAD-I THROUGH
DAI1—1 H
——
BAG —2
THROUGH
DAN-2
—<>
ADDRESSING
‘
-—
BAG —3 THROUGH DA11—3
—<> LINE
————————
OAO THROUGH DAII ————————¢
——
BAG -4 THROUGH
BAH—4
——<>
SELECTOR
—
OAO
—
5
THROUGH
mm —5 ————-<>
—
DAG -6
THROUGH
DAIt—G
—-———<>
ADDRESS
SELECTION
T
LINES
CYC SEL-O
SEL
-————-——
THROUGH
CYC
SEL
-
II
CYL
SEL
—-—-.
DAEX
3-0
—-
THROUGH
MPX
DAEX
3—6
7
LINES
DAEX 3
—.
DAEX
2-0
THROUGH
DAEX 2- 6
DAEX 2
——'—.
DAEX
I-O
THROUGH
DAEX 1-6
DAEX
1
—-—-—.
B X MPX
0
Av
THROUGH
B
<)(-
MPX 6
SEL
PERIPHERAL
_
DEVICES
i
B
ENABLE
O
>
Pop 8
THROUGH
———O
B
ENABLE
s
BREAK REQUEST
o
——
THROUGH
——-——<>
¥-—————-
BREAK
BREAK REQUEST
6
—————
BREAK REOUEST
—-—-—-—O
MULTIPLEXER
n
CONTROL
ADD ACC-O
_
ADDRESS
ACCEPTED
+——'~——
THROUGH
"——‘
—"""-———
POWER CLEAR
ADD ACC-G
WCOV
I
B ENABLE O
WCOV— 0 THROUGH
6
*—-—-——
THROUGH
WCOV
-
6
SEL
DATA
-OUT
-
0
——
THROUGH
—<)I
SEL
-—-—-
DA
TAIN
—.
DATA
-0UT-
6
l
SEL
I
T
DA SEL DEV
-
0
THROUGH —.l
DA
SEL
DEV-6
SEL
—
+1—.CA
INH
—9
—_
+ '
"T’Hca‘ln'féfl
‘
°
+1»
CA
INH
-
6
fl
—
OBO -0
THROUGH
OBn-o
————<>
”——
030
—l THROUGH
Dan-1
—O
—
DBO
—
2 THROUGH
0811—2
~—————-—-<>
DATA
—
030—3
THROUGH
Dan—3
———<>
LINE
-————
OBO THROUGH 0811
¢
—
D80
—4
THROUGH
Dan—4 —————-<>
SELECTOR
,
——
080- 5
THROUGH
0811—5
——<>
—
DaO-s THROUGH OBn-s
—<>
L
Figure
3—l
DMOI
Data
Break
Signals
The
-3v
output
of the
SI
II
diode
gate
is inverted
by
the
Sl07
module
(figure
8-5)
at
location
B32. The
resulting
BRK
REQUEST
ground
level
goes
to
the
PDP-8
major
state
generator
to
signal
the
computer
that
a
data
transfer
is
to
take
place
.
BRK
REQ
l is
also
applied
to terminal
E
of
the
W005
clamped
load
(figure
8-9)
at
location
B9
and
shown across
the
middle
of
the
drawing
.
The level
enables the
DCD
gate
associated
with
the
set
terminal of
the
MPX—I
flip-flop.
The
corresponding
gate
of the
remaining
MPX
flip-flops
is
inhibited.

A PDP-8 T1
timing
pulse
sets the
MPX-1
flip—flop,
enabling
the
DCD
gate
connected
to the
set terminal
of the
B
ENABLE
1
flip-flop.
The
ground
level
from the
1 side of
the
MPX-1
is
applied
to
terminal F
of the
S181
clc
carry
chain
(figure 8-7)
at
B12
and shown
across
the lower
portion
on
the
drawing. Through
this
operation,
all
MP“
flips—flops
that
are
less
significant
(to
the
rig..t
of)
tnan
MPX-1
are
held
in the
0
state.
Because
of this
Function,
the
peripheral
device
producing
BRK
REQ
1
is
given
priority
over
the less
significant
peripherals.
MEM
DONE
ADD
MEMSTART
T
1
ACC.
1’2
T1
Figure
3—2 PDP—8
—
DM01
Timing Diagram
A -3v level
is-
present
at
K
of the
S111
module at B30
and
also shown across
the
lower
part
of
the
drawing
.
When
an
ADDRESS ACCEPTED
pulse
arrives
from
the
PDP-8,
B ENABLE
1
is set and
a
-3v
ADD
ACC-1
pulse
is
generated
.
1
The levels
and
pulses produced by multiplexer
control
are used
by
other circuits of the
DM01,
as
covered
in
the
following
sections.
3.2.2
Level Production
from
Multiplexer
Control
(BS-D—DM01-0-11)
The
logic
circuitry
of
figure
8-14
uses the
output
levels
of
the
MPX
and
B
ENABLE
flip-flops
to
produce
levels
and
pulses
for use
by
both
the
DMO1
and the
peripheral
devices.
The
logic
element
on the
left side
of the
drawing
consists
of
seven,
2-input,
diode
gate-
inverter-clamped
load
networks.
The
$111
diode
gates
at locations
36, B8,
and
323 have
paired
inputs
which form
AND
gates.
One
terminal of each
gate
is
common,
and
is
at
—3v
whenever
a
break
is in
progress.
Proceeding
with the
example,
a -3v
level
from the set
B ENABLE
1
flip-flop provides
the
level
necessary
to
give
the desired -3v B
-
MPX
1
level
from
the
W005
clamped
load
at
B9.
The
gated
driver,
made
up
of the
$111
diode
gates
at
A16, A17,
and
A18
and
the
W640
pulse
converters
(figure
8-11)
at
B29,
A14,
and
A15
produce
a
-3v
WCOV
(word
count
overflow)
pulse
when
suitable
inputs
are
present.
Because
0
-3V
B ENABLE
level
is
present,
a -3v
WCOV-1
pulse
is
produced
when
0
-3V
WCOV
pulse
arrives. The
B
°
MPX
1
level
and
WCOV-1
pulse
go
to
peripheral
device
1
.
3-3

The
two
paralleled
inverters
on
the
right
side
of
the
drawing
produce
levels
that are used
by
DMOl
selector
networks.
A -3v DB SEL
DEV
T
level,
which
is used
by
the
selector networks shown
in
Figure
8-16
and discussed
in section
3.2.4,
is
generated
by applying
a
ground
level from the
B
ENABLE
l
flip—flop
to
terminal H
of the
Sl07
diode
gate
CIT
Al2. The
output
is at terminal
F
at
B4.
DA
SBL
DEV
l
is
used
by
the
logic
circuitry
of
figures
8—l5
and
8-l6,
and is
explained
in
section
3.2.3.
The
level
is
produced by
inverting
the
MPX—l
ground
level
present
at
terminal H
of the
Sl07
inverter at
B5. The
output
is
present
at
F,
location
Al3.
3.2.3
Data Address Line Selector
(BS—D-DMOl-0-4)
The
circuitry
shown across the
top
of
figure
8-15 serves
to
permit
the l2-bit
address from
the
peripheral
device
requesting
the break to enter
the
PDP—8
memory
address
register.
This
is
accomplished
through
a
logical
AND
operation
.
The
terminals labeled
E, H, K, M, P,
S,
and
U
of the
Bl 4l
Module
(figure 8-2)
at location
Cl
receive
the
levels
designated
DA SEL DEV
0
through
DA
SEL
DEV
6,
respectively.
The
most
signi-
ficant
data address
bit from the
peripheral
devices is
applied
to terminals
F,
J, L, N, R, T,
and
V
of
module
Cl;
the least
significant
is
applied
to module
Cl2.
Continuing
with the
example,
a
-3v
DA SEL
DEV
l
level,
applied
to
terminal
H,
provides
one level
needed
by
the
AND
gate.
The
data address
bits,
designated
DAO—l
through
DAll-l
,
are
applied
to the
remaining
terminal
of
the
gate
.
The
output
levels,
DAG
through
DAl
l
,
which
go
to the
PDP-8
memory
address
register,
appear
at the
SlO7
inverter
output
at locations
B7
and
Bl5
.
The
logic
circuitry
across
the lower
part
of
the
drawing
functions
in a
similar
manner.
DA SEL DEV
1
enables the same
terminal
of each
Bl
41
Module.
A CYC
SEL-l
level
from
peripheral
device
1
is
logically
ANDed
with
DA
SEL
DEV
l in the
diode
gate
at
Cl3.
The
output
CYC
SEL
level,
available
at
terminal R
of
the
inverter
at
Bl5,
goes
to
the
PDP-8
major
state
generator.
The
Bl4l
diode
gates
at
locations
Cl4, C15,
and
Cl6
permit
the extended
memory
address
bits from
peripheral
device l
to enter
the
PDP—S. The
output
levels,
designated
DAEX
l,
DAEX
2,
and
DAEX
3,
are available
at the
Sl07
inverter
terminals
F
and
D at
B25
and
T
at
315,
respectively.
3.2.4
Data
Bits
Line
Selector
(BS-D-DMOl-0-3)
Data
bits from the selected
peripheral
device
reach the
PDP-8
memory
buffer
register
through
the
logic
circuitry,
made
up
of the
Bl
4l diode
gates
at locations
Cl7
through
C28,
and
illustrated
across
the
top
of
figure
8-l6.

This
circuitry operates
in the
same manner as that used for data
addressing;
namely,
DB SEL DEV
I
provides
one
level
required by
the
gate
string,
and the
data
bits From
peripheral
device
I,
designated
DBO—I
thrOUgh
DBlI-I,
previde
the
remaining
levels.
The
l2-bit
output, comprised
of
the
bits labeled
D30
through
DBll,
are found at the
Sl07
inverter
outputs
at locations
325
and
B26.
An
INCREMENT
CA INHIBIT
(+1
—>
CA
INH)
level,
which
is used
during
3-cycle
breaks,
is
produced
by
ANDing
the
DB
SEL DEV
I
and
+I
-—>CA
INH
levels.
Similarly,
G
DATA IN
level,
which
specifies
the data transfer
direction,
is
produced by
ANDing
DA
SEL
DEV
I
with
DATA OUT.
These
two levels are terminated at
pins
N
and
R,
respectively,
of the
Sl07
diode
gate
at
location B32
.

CHAPTER4
INTERFACE
All
interface
connections
to the
DMOl
are made at
assigned
module
receptacle
connectors
at
the back
of the
multiplexer.
Theinterfacing
between
the
PDP-8, DMOl,
and the
peripheral
devices
is shown
in the
following figures:
Figure
8-17 DMOl
Interconnecting
Cable
Diagram (IC-DMOl-O—l3)
Figure
8-l8
I/O
Connectors
(BS-D-DMOl-O-é)
Figure
8-19
Data
Multiplexer
Connectors
(BS-D-DMOl-O-5)
4-1

CHAPTERS
POWER
SUPPLY
ADEC
Type
728
Power
Supply
(table
8—1) generates
the
voltage
levels
(+10
and
-l5
vdc)
required
for
operation
of
the
multiplexer.
Chapter
8
contains
the schematic of this
power supply
and
chapter
6,
the
output
check
data.
The
DEC
System
Modules
Catalog
(C-lOO)
provides
detailed information on the
operational
character-
istics
of the
supply
.
5-1

CHAPTER6
MAINTENANCE
6.1 PREVENTIVE
MAINTENANCE
The
general
preventive
maintenance
procedures provided
in the
PDP—8
Maintenance Manual
(F-87) apply
to the
multiplexer
control
logic
.
6.1
.l
Power
Supply
Checks
Table
6-] shows
the
output
voltage
checks
needed
for
the
Type
728
Power
Supply
used
in
1
terr‘
‘L “" "
l" checks
described
in
table 6-.
. Use
a
multimeter
to
make
the
this
equipment.
Per
l me
power supp y
output
voltage
measurements with the normal load
connected,
and an
oscilloscope
to
measure
the
peak-
to—peak ripple
content
on
all dc
outputs
of the
supply.
The
+’I0v
and
-I5v
supplies
are
not
adiustable;
therefore,
if
any output
voltage
or
ripple
content
is not within
specifications,
consider the
power
supply
defective
and initiate
troubleshooting
procedures.
TABLE
6—I
TYPE
728
POWER SUPPLY
OUTPUT CHECKS
(Drawing
CS-B-728)
fifgiiizrifsi
Nominal
Acceptable
Maximum Maximum
Power
Supply
Output
Output
Output
Peak-to-Peak
Output
(vdc) Range
(v)
Current
(a)
Output
Ripple
(v)
Red
(+)
to
+10
+9.5
to +1]
.0
7
0.7
Yellow
(—)
Yellow
(+)
to
—l5v
-I4.5
to
46.0
8
0.7
Blue
(-)
6.2 CORRECTIVE MAINTENANCE
The
simplicity
of the
system
and
the
logic
description provided
in this document
permit
the
use
of standard
troubleshooting
techniques
for
isolating
the
trouble
quickly
and
efficiently.
For
economical
maintenance under most
conditions,
replace
the
inoperative
module with one from
spares
and return the
defective
module to
DEC
for
repair
or
replacement.