Digital Equipment PDP-8/L User manual

DEC-8/L-HR1B-D
PDP-8/L
MAINTENANCE MANUAL
VOLUME I
DIGITAL EQUIPMENT CORPORATION •MAYNARD, MASSACHUSETTS

\st Printing October 1968
2ncl Printing May 1969
3rd Printing (Rev) December 1969
4th Printing July 1970
Copyright ©1968, 1969, 1970 by Digital Equipment Corporation
The material in this manual is for informa-
tion purposes and is subject to change with-
out notice.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC PDF
FLIP CHIP FOCAL
DIGITAL COMPUTER LAB

CONTENTS
CHAPTER 1
INTRODUCTION AND DESCRIPTION
1.1 IntroducHon
1.2 Description
1.3 Pertinent Documents
CHAPTER 2
INSTALLATION
2.1 Space Requirements
2.2 Environmental Requirements
2.3 Internal Option Installation
2.4 Interface
2.4.1 I/O Bus
2.4.2 I/O Cables
2.4.3 Cable Connectors
2.5 Interface Connections
2.6 External Equipment Cable Locations
2.7 Bus DriverAeceiver Modules
2.7.1 Mil 1/M906 Positive Input Circuit
2.7.2 M516 Positive Bus Receiver Input Circuit
2.7.3 M623/M906 Positive Output Circuit
2.7.4 M660 Bus Driver Output Circuit
CHAPTER 3
OPERATION
Page
1-1
1-1
1-1
2-1
2-3
2-3
2-3
2-3
2-4
2-4
2-4
2-5
2-5
2-5
2-6
2-7
2-7
3.1 Controls and Indicators 3-1
3.1.1 Computer 3-1
3.1.2 Teletype 3-4
3.2 Operating Procedures 3-4
3.2.1 Manual Loading Procedures 3-4
3.2.2 Teletype Loading Procedures 3-5
3.2.3 Off-Line Teletype Procedure 3-6

CONTENTS (Cont)
CHAPTER 4
THEORY
Page
Section I: Block Diagram Discussion
4.1 Registers
4.1.1 Accumulator (AC)
4.1.2 Link (L)
4.1.3 Program Counter (PC)
4.1.4 Memory Address Register (MA)
4.1.5 Memory Buffer Register (MB)
4.1.6 Sense Register (Sense)
4.1.7 Instruction Register (IR)
4.1.8 Switch Register (SR)
4.2 Major Register Gating Network
4.3 Timing and Control Elements
4.3.1 Timing Elements
4.3.2 Control Elements
4.4 Input/Output
4.5 Memory
4.5.1 Core Array
4.5.2 Memory Control
4.5.3 Address Selection
4.5.4 Inhibit Drivers
4.5.5 Sense Amplifiers
Section II: General Theory
4.6 Time States/Time Pulses
4.7 Major States
4.8 Internal Data Flow
4.9 Instructions
4.9.1 Memory Reference Instructions
4.9.2 Augmented Instructions
4.10 Program Interrupt
4.10.1 Instructions
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-4
4-4
4-4
4-5
4-6
4-11
4-11

CONTENTS (Cont)
Section III: Detailed Memory Theory
4.11 Overall Memory Theory
4.12 Memory Operation
4.12.1 Memory Control
4.12.2 Read/Write
4.12.3 Address Selection
Section IV: Detailed Processor Theory
4.13 Timing
4.13.1 Manual Function Timing Generator
4.13.2 Manual Operations
4.13.3 Time States
4.14 I/O Timing
4.15 Memory Protect
4.16 Major States
4.17 Internal Data Flow
4.17.1 Source
4.17.2 Route
4.17.3 Destination
4.18 Operating Instructions
4.18.1 Instructions
4.18.2 Memory Reference Instructions
4.18.3 Direct/Indirect Addressing
4.18.4 Augmented Instructions
CHAPTER 5
MAINTENANCE
5.1 Equipment
5.2 Programs
5.3 Preventive Maintenance
5.3.1 Weekly Checks
5.3.2 Preventive Maintenance Tasks
5.4 Corrective Maintenance
5.4.1 Preliminary Investigation
5.4.2 System Troubleshooting
Page
4-11
4-12
4-12
4-12
4-16
4-19
4-19
4-19
4-21
4-21
4-24
4-25
4-26
4-27
4-27
4-27
4-28
4-29
4-29
4-34
4-35
5-1
5-2
5-3
5-3
5-3
5-3
5-4
5-4

CONTENTS (ConO
Page
5.4.3 Logic TroubleshooHng 5-5
5.4.4 Circuit Troubleshooting 5-5
5.4.5 Repairs and Replacement 5-6
5.4.6 Validation Tests 5-6
5.4.7 Recording 5-7
5.5 Adjustments 5-7
5.5.1 Power-Up Threshold Adjustment 5-1
5.5.2 Memory Alignment Procedure 5-7
5.6 ASR33 Teleprinter and Control Maintenance 5-11
5.6.1 Equipment 5-11
5.6.2 Programs 5-12
5.6.3 Preventive Maintenance 5-12
5.6.4 Corrective Maintenance 5-15
ILLUSTRATIONS
1-1 PDP-8A
2-1 Table Top PDP-8A Dimensions 2-1
2-2 Rack-Mounted PDP-8/L 2-2
2-3 Chassis-Track Specifications 2-2
2-4 Rack-Mounted PDP-8/L Frame with Track -Slide Specifications 2-3
2-5 I/O Bus Configuration 2-4
2-6 I/O Signal Connections 2-5
2-7 Cable Location Convention on Option Mounting Panels 2-6
2-8 Ml 11/M906 Logic Diagram 2-6
2-9 Typical M516 Positive Bus Receiver Input Circuit 2-6
2-10 Typical M623/M906 Positive Output Circuit 2-7
2-11 Typical M660 Bus Driver Output Circuit 2-7
3-1 PDP-8/L Front Panel 3-1
3-2 Teletype Model ASR33 Console 3-3
4-1 System Block Diagram 4-2
4-2 Memory Reference Instruction Bit Reference 4-5
4-3 lOT Instruction Bit Assignments 4-6
4-4 Group 1Operate Instruction Bit Assignments 4-7

ILLUSTRATIONS (Cont)
Page
4-5 Group 2Operate Instruction Bit Assignments 4-9
4-6 Memory System, Block Diagram 4-13
4-7 Memory Timing Diagram 4-14
4-8 Simple Core Memory Plane 4-15
4-9 Memory Address Selector or Read/Write Current Control 4-17
4-10 Manual Function Timing Diagram 4-18
4-11 System Timing Diagram 4-22
4-12 I/O Timing Diagram 4-23
4-13 Data Flow 4-28
4-14 Direct and Indirect Address Selection, Simplified Flow Chart 4-36
5-1 IC Location 5-6
5-2 IC Pin Location 5-6
5-3 Memory Control Waveforms 5-9
5-4 Representative Read/Write Current Waveforms 5-10
5-5 Representative Inhibit Current Waveforms 5-12
5-6 Representative Sense Amplifier Waveforms 5-14
5-7 Teletype Connections 5-16
5-8 Teletype Signal Waveform and Bit Relationship for the Character "U" 5-17
TABLES
3-1 Computer Controls and Indicators 3-1
3-2 Teletype Controls and Indicators 3-4
3-3 Readin Mode Loader Program 3-5
4-1 Example of Register Contents During JMS Instruction 4-33
5-1 Maintenance Equipment 5-1
5-2 Maintenance Programs 5-2
5-3 Power Supply Specifications 5-4
5-4 Teletype Maintenance Tools 5-13
5-5 Teleprinter Maintenance Programs 5-13
VII

PDP-8/L MAINTENANCE MANUAL
VOLUME 1

Figure 1-1 PDP-8/L

CHAPTER 1
INTRODUCTION AND DESCRIPTION
1.1 INTRODUCTION
This manual covers installation, operation, theory,
and maintenance of The Programmed Data Processor -
8/L (PDP-8/L). It is the intent of this manual to
provide the field service engineer or maintenance
technician who is familiar with digital logic circuitry
with the information he needs to install and maintain
aPDP-8/L system. The bulk of the manual assumes
that the reader is conversant with DIGITAL'S system
of logic notation. If this is not the case, the reader
should refer to applicable sections in the appendix
for adescription.
1.2 DESCRIPTION
The Digital Equipment Corporation integrated-circuit
Programmed Data Processor-8/L (PDP-8/L) (see Fron-
tispiece) serves as asmall-scalegeneral-purposecom-
puter that functions as an independent information-
handling facility in alarge computer system, or as
the control element in acomplex processing system.
The PDP-8/L is aone-address, 12-bit, fixed-word-
length, parallel computer using two's complement
arithmetic. Normal cycle time of the 4096-word
(referred to as 4K) random-access, magnetic core
memory is 1.6 ^. An additional 4K of memory may
be available to the system simply by adding an MC
8/L memory expansion and control unit.
Standard features of the system include indirect ad-
dressing, facilities for instruction skipping and pro-
gram interruption as functions of input/output device
conditions, and optional high-speed information
transfers into peripheral mass memory devices via a
cycle stealing data break.
The PDP-8/L performs one addition in 3.2 |js (with
one number in the accumulator), permitting acompu-
tation rate of 312,500 additions per second to be
achieved. It performs subtraction in 6.4 |jts (with
the minuend in the accumulator) using two's comple-
ment addition. Multiplication takes approximately
384 |js, using asubroutine that operates on two signed
12-bit numbers to produce a24-bit product, leaving
the 12 most significant bits in the accumulator. Divi-
sion of two signed 12-bit numbers takes approximately
490 ps, using asubroutine that produces a 12-bit
quotient in the accumulator, and a12-bit remainder
in core memory
.
Flexible, high-capacity, input/output capabilities of
the computer allow it to operate avariety of periph-
eral equipment. In addition to the Teletype key-
board/printer and perforated-tape reader/punch
equipment supplied with abasic PDP-8/L, the system
can operate anumber of optional devices, such as a
high-speed perforated-tape reader and punch, card
reader, line printer, analog-to-digital converters,
cathode-ray-tube displays, magnetic-drum systems,
magnetic disk-file systems, and magnetic-tape equip-
ment. Instruments or equipment of special design can
also be connected into the PDP-8/L system. The
computer itself needs no modification for the addition
of these peripheral devices.
The PDP-8/L is completely self-contained, and, under
normal conditions, requires neither special power
sources nor rigidly controlled environmental condi-
tions. Asingle source of 105-130 Vac, 47-63-Hz,
single-phase power permits internal power supplies to
produce all required operating voltages. M-Series*
modules, using TTL-type integrated-circuit packs,
ensure reliable operation in ambient temperatures be-
tween +10° and +55 X.
1.3 PERTINENT DOCUMENTS
The following documents serve as source material and
complement the information in this manual:
1
.
Logic Handbook, C-105 (1969 edition) printed
by DIGITAL, which notes the function and speci-
fications of the M-Series modules and module ac-
cessories for the PDP-8/L.
2. PDP-8/L Users Handbook.
3. Technical Manual, Automatic Send and Re-
ceive Sets (ASR) (Bulletin 273B Volumes 1and 2).
This manual covers operation and maintenance of
the Teletype unit.
*M Series is aregistered trademark of Digital Equip-
ment Corporation.
1-1

4. Parts, Model 33 Page Printer Set (Bulletin
1184B) contains an illustrated parts breakdown to
serve as aguide to disassembly, reassembly, and
ordering replacement parts for the Teletype unit.
5. Instruction List F-816, printed by DIGITAL.
This is ashirt-pocket list of all memory reference
instructions, all augmented instructions, the most
common lOT instructions, and the ASCII code used
with many I/O devices.
6. Instruction manuals and MAINDEC programs
for appropriate input/output devices are prepared
by DIGITAL.
7. Digital Program Library Documents. Perfo-
rated program tapes and descriptive matter for the
Program Assembler Language (PAL III), FORTRAN,
FOCAL, utility subroutines, and the maintenance
programs (MAINDEC) prepared by DIGITAL are
available to PDP-8/L users. The list of programs
currently in the library and available is provided
in Appendix D.
1-2

CHAPTER 2
INSTALLATION
This chapter contains installation and interface infor-
mation for the PDP-8/L and its options.
2.1 SPACE REQUIREMENTS
If DEC cabinets are not purchased, the cabinets at
the instal lotion should provide for access to all doors
and panels for maintenance.
The PDP-8/L is available in either the table top or
rack-mounted configuration. The rack-mounted con-
figuration and peripherals may be purchased com-
pletely installed in DEC cabinets or unmounted for
installation in acustomer cabinet. The standard
teletype automatic send receive (ASR) set requires a
floor space of approximately 22-1/4 in. wide by
18-1/4 in. deep. The teletype signal cable requires
the teletype to be placed near the computer.
Figures 2-1 through 2-4 provide PDP-S/l dimensions
for both tape top and rack-mounted configurations.
Figure 2-1 illustrates the table top dimensions, and
Figure 2-2 illustrates the rack-mounted PDP-8/L.
The rack-mounted configuration is attached to the
cabinet on sliding chassis tracks. There are two sets
of tracks; one set for each frame side .The track sec-
tions interlock; one section being bolted to the cab-
inet and the other bolted to the logic main frame.
Figure 2-3 shows the chassis track specifications. A
rear view of the rack-mounted PDP-S/L and track-
slide specifications is illustrated in Figure 2-4.
Figure 2-1 Table top PDP-8/L Dimensions
2-1

Figure 2-2 Rack-Mounted PDP-8/L
-AUTOMATIC CHANNEL STOP
BASIC CABINET
CHASSIS
^' "^
AUTOMATIC LOCK OUT
QUICK DISCONNECT
RAISE MANUAL RELEASE ARM
TO REMOVE OR RETURN CHASSIS
245/64^T
rj
i^
1" FROM
TOP OF CHASSIS
li_ OF MOUNTING HOLES
(I OF SLIDE
TtOF £
5/32"
21 7/8"
SIDE VIEW OF
MOUNTING HARDWARE
Figure 2-3 Chassis-Track Specifications
2-2

REAR VIEW OF
MOUNTING HARDWARE
Hh
I1/4
"tOF SLIDE
Figure 2-4 Rack- Mounted PDP-8/L Frame with
Track-Slide Specifications
2.2 ENVIRONMENTAL REQUIREMENTS
5-0
The PDP-8/L is designed to operate between 32° and
130° F(0°and 55° C). The life-expectancy of the
system, however, can be extended if the temperature
at the installation site is maintained at between 70°
and 85° F(between 21 °and 30° C).
During shipping or storing of the system, the ambient
temperature should be maintained within 32° to
130° Fto prevent damage to the system. Although
all exposed surfaces of Digital cabinets and hardware
are treated to prevent corrosion, exposure of systems
to extreme humidity for long periods of time should
be avoided.
For external options, forced air cooling should be used
if more than afew module-filled H911 mounting pan-
els are needed. The low power consumption of M-
series modules results in approximately 15W dissipation
in atypical H911 mounting panel of 64 modules. If
only one or two panels of logic are used, convection
cooling is sufficient.
2.3 INTERNAL OPTION INSTALLATION
The installation of the internal options involves the
addition of the logic modules in the proper locations.
WHEN INSERTING OR REMOVING ANY MODULES
IN THE LOGIC FRAME THE 8/L SYSTEM MUST BE
TURNED-OFF. Refer to the module utilization draw-
ing for the locations of each module of all internal
options. If an option involves an external device,
dress connecting cables through the opening at the
rear of the PDP-8/L to the option.
2.4 INTERFACE
2.4.1 I/O Bus
The PDP-8/L uses aseries l/O bus system to permit
interface connections to be made between external
devices and the 8/L without modifying the computer
wiring. In aseries I/O bus, the computer sends all
I/O signals to the first device. This device uses the
pertinent signals and sends all of the signals to the
next I/O device (see Figure 2-5). This allows one set
of cables to be connected to the PDP-8/L and two
sets connected to each device: one receiving the
I/O bus signals from the computer itself or the previ-
ous device, and one passing the l/O bus signals to
the next device. The data break cables are used in
the same manner.
When the equipment location does not make series bus
connections feasible, or when cable length becomes
excessive, additional interface connectors can be
provided near the computer.
2-3

10 CABLES
DEVICE
2
(2) ®-® ^
DATA BREAK
CABLES DATA BREAK CABLES
10 CABLES TO
'ADDITIONAL DEVICES
DATA BREAK CABLES
'TO ADDITIONAL DEVICES
Figure 2-5 I/O Bus Configuration
2.4.2 I/O Cables
Eighteen conductor coaxial cables or flexprint cables
with either M904 or M903 coble connectors, respec-
tively, provide signal connection between the com-
puter and optional equipment. These cables are con-
nected by plugging the connectors into standard FLIP
CHIP module receptacles. Use of coaxial cable pro-
tects systems from radiated noise and cross talk be-
tween individual lines. Coaxial cable used between
the PDP-8/L and options has the following specifica-
tions:
Zq =95Q ±5%
C=13.75 pf/ft approximately (unterminated)
L=124 Nhy/ft approximately
R=0.095 ohm per foot nominal
Y=79% of velocity of light, approximately
(=; 1.5ns/ft.).
The flexprint cable is generally used because of its
high flexibility. The conductors ore '*'30 AWG flat
copper
.
The maximum length of I/O cabling, from the PDP-
8/L to the last device is 50 ft. This can be 50 ft. of
coax or acombination of coax and flexprint, in which
case the flexprint cannot exceed atotal length of
15 ft.
2.4.3 Cable Connectors
The M903 and M904 cable connectors are used with
the coble types described above. M903 connectors
are used with flexprint cable. The M904 connectors
terminate the coaxial coble ends.
Both connectors are wired double-sided with 36 pin
contacts. Each connector terminates two coaxial or
flexprint cables. The conductors from both types of
cables terminate at the connector pin locations indi-
cated below. Each signal conductor is isolated by a
ground conductor. The connector pin locations for
signals are: Bl ,Dl, El, HI, Jl, LI, Ml, Pi, SI,
and D2, E2, H2, K2, M2, P2, S2, T2, V2. The
ground pin locations on each connector are: Al ,CI
,
Fl, Kl, Nl, Rl, Tl, and C2, F2, J2, L2, N2, R2,
U2.
2.5 INTERFACE CONNECTIONS
All interface connections to the PDP-8/L are made at
assigned module receptacle connectors in the mounting
frame. Capitol letters designate horizontal rows of
modules within amounting frame from top to bottom,
i.e., Ais the first row, Bis the second row, etc.
Module receptacles are numbered from left to right as
viewed from the wiring side (right to left from the
module side). Terminals of aconnector or module are
assigned capital letters from top to bottom omitting
G, I, O, and Q. Double sided connectors or mod-
ules are used with the suffix number "1" designating
the one side and suffix number "2" designating the
other side.
Figure 2-6 shows the signals and pin locations at each
connector block. The I/O cable connectors are in-
serted into these locations to form the I/O bus. The
arrows associated with each signal show the signal
direction. The arrows pointing to the connectorblock
2-4

DATA ee
DATA ei
DATA 82
DATA 03
DATA e^l
DATA 85
DATA 86
DATA 07
DATA 88
DATA 09
DATA 10
DATA 11
3CYCLE
CA INCREMENT
BWC OVERFLOW
EXT DATA ADD
^UNUSED
DATA ADD 08
DATA ADD 01
DATA ADD 02
DATA ADD 03
DATA ADD 04
DATA ADD 05
DATA ADD 06
DATA ADD 07
DATA ADD "06
DATA ADD "g9
DATA ADD 10
EAIA^,
DATA IN
BBREAK (01
BADD ACCEPTED (1)
MEMORY INCREMENT
BINITIALIZE
INPUT BUS 00
INPUT BUS 01
INPUT BUS 02
INPUT BUS 03
INPUT BUS 04
INPUT BUS 05
INPUT BUS 06
INPUT BUS 07
INPUT BUS 08
INPUT BUS 09
INPUT BUS 10
NPUT BUS I I
I/O SKIP
INT RQST
AC CLEAR
BRUN (0)
BMB00 (I)
BMB0I II)
BMB02 (I)
BMB03 (0)
BMB03(ll
BMB04(0)
BMB04(I)
BMB05(0)
»BMBe5(l)
BMB06(e)
BMB06(I)
BMB07(0)
BMB07II)
BMB08(0)
BMB08(I)
BMB09(I)
BMBI0 (I)
BMB I I (I)
BAC00
BAC01
BAC02
BAC03
BAC04
BAC05
BAC06
BAC07
BAC08
8AC09
•BAC 1
BACH
BI0P1
BI0P2
8I0P4
BTS 3(I)
BTS 1(1)
*• BINITIALIZE
Figure 2-6 I/O Signal ConnecHons
indicate signals coming to the computer from tiie I/O
bus. Similarly, the arrows pointing away from the
connector block indicate signals from the computer to
external devices through the l/O bus.
option mounting panel are wired in parallel with the
top module slot locations 1through 5. To continue
the I/O cabling to the next device, the bottom slots
are used.
2.6 EXTERNAL EQUIPMENT CABLE LOCATIONS
The I/O cables connected within the computer at the
locations specified by Figure 2-6 are generally con-
nected on an option mounting panel as indicated in
Figure 2-7. This illustration shows the DEC conven-
tion for cable terminations.
Module slot locations 1through 3(looking at the
wiring pin side) in the Arow of an option mounting
panel are reserved for program interrupt cable con-
nections in (or out). Module slot locations 4and 5
are reserved for Data Break cable connections In
(or out).
Module slot locations Ithrough 5in the Brow of the
2,7 BUS DRIVE IVRECEIVER MODULES
The following paragraphs describe each bus driver
and receiver module type shown on Engineering
Drawing BS-8L-&-10. These circuits provide isola-
tion and drive for signals between the processor and
l/O cables.
2.7.1 Min/M906 Positive Input Circuit
Figure 2-8 shows the M111/M906 logic configuration.
The Ml 11 Inverter module is used in conjunction with
the M906 Cable Terminator module which clamps the
Input to prevent excursions beyond +3V and ground.
2-5

BACOO
to
BAcn
BIOP 1, 2, 4
BTS 3, 1
BINITIALIZE
BMBOO
to
BMBll
ACOO BUS
to
AC 11 BUS
SKIP BUS
INT RQST BUS
AC CLEAR
CONT BUS
BRUN
DATA ADDOO
to
DATA ADD 11
BRK RQST
DATA IN
MB INCREMENT
BADD
ACCEPTED
DATAOO
to
DATA 11
3CYCLE
CA INCREMENT
EXT DATA ADD
BBREAK
BINITIALIZE
BWC
OVERFLOW
SAME ASSIGNMENTS AS ABOVE
^f
-^ f
-! S-
32
Figure 2-7 Cable Location Convention on Option Mounting Panels
The incoming DATA and DATA ADD signals for data
break and other signals (Drawing BS-8L-0-10) are
inverted and isolated from the I/O cables through
this logic.
rBl pOUTPUT SIGNAL TO PROCESSOR n
A
r
MIt t
IISINVERTERTS)
n
-V^ +5V M906
(ta CIRCU ITS)
BIO POSITIVE BUS INPUT SIGNAL
(FROM EXTERNAL DEVICE)
2.7.2 M516 Positive Bus Receiver Input Circuit
Figure 2-9 shows the M516 logic configuration. Six
four-input NAND gates with overshoot and undershoot
'B19OUTPUT SIGNAL TO PROCESSOR '
?TO
-O Bl
-V^ +5V
U5I6
(SI XGATES )
INTERNALLY
Al 6POSITIVE BUS INPUT SIGNAL
(FROM EXTERNAL DEVICE)
Figure 2-8 Mil 1/M906 Logic Diagram
Figure 2-9 Typical M516 Positive Bus Receiver
Input Circuit
2-6

clamp on one input of each gate. The I/O SKIP gate
(Drawing BS-8L-0-10) is an example of M516 appli-
cation. The input signals applied to pins Bl, CI,
and Dl are from internal options .With the I/O SKIP
gate, these signals are PWR SKIP, RDR SKIP, and
TTSKIP,
2.7.3 M623/M906 Positive Output Circuit
Figure 2-lOshows the M623/M906 logic configuration
.
The M623 Bus Driver module contains 12 negative
NAND circuits. Used with the M906 Cable Termin-
ator module, the output is clamped to prevent excur-
sions beyond +3V and ground. The output can drive
+5 mA at the high level and sink 20 mA at the low
level. The ACOO through ACl 1signals (Drawing
BS-8L-0-10) are examples of M623 applicotion.
2.7.4 M660 Bus Driver Output Circuit
Figure 2-1 1shows the M660 logic configuration .This
bus driver circuitry provides low impedance 100 ohm
terminated cable driving capability, using M-Series
levels, or pulses of duration greater than 100 ns.
Each output can drive +5 mA at the high level and
sink 20 mA at the low level, in addition to the term-
ination current required by the G717 Termination
module. The M660 module is used in the PDP-8/L
for the following output signals: lOP 1,lOP 2,
lOP 4, TS 3and TSl (Drawing BS-8L-0-10).
IM906
I(18 CIRCUITS) n
POSITIVE BUS OUTPUT SIGNALS
(TO EXTERNAL DEVICE)
rM623
(12 CIRCUITS)
AlO =•" 681
IOUTPUT SIGNALS FROM PROCESSOR J
rn
POSITIVE BUS OUTPUT SIGNAL
(TO EXTERNAL DEVICE)
M660
(3CIRCUITS)
LOUTPUT SIGNAL
FROM PROCESSOR J
Figure 2-10
Typical M623/M906 Positive Output Circuit
Figure 2-1
1
Typical M660 Bus Driver Output Circuit
2-7