EG&G ORTEC 444 User manual

INSTRUCTION
,~,
MANUAL
:* d‘-‘~’444
‘. _ I,
GATED
:, I
;,t. BIASED
,$: AMPLIFIER
:p.-.

TABLE OF CONTENTS
WARRANTY
PHOTOGRAPHS
1. DESCRIPTION
1.1 General
1.2 Basic Functions
2 SPECIFICATIONS
2.1 Inputs
2.2 Outputs
2.3 Performance
2.4- Controls
25 Connectors
2.6 Power and Mechanical
2.7 Related Equipment
3. INSTALLATION
3.1 General Installation Considerations
3.2 Connection to Power
3.3 Linear Input Connection
3.4 Linear Output Connections
3.6 Gate Input
3.6 Connection for Busy Output
3.7 Use of Inhibit Input
3.8 Use of External Strobe
4. OPERATION
4.1 Selection of Input Circuit Coupling
4.2 Discriminator Level Adjustment
4.3 Output Delay Adjustment
4.4 Gain Adjustment
4.5 Bias Level Adjjstment
4.6 Output DC Adjustment
4.7 Gated Operation
4.8 Overall Logic
4.9 Internal Adjustment
5. CIRCUIT DESCRIPTION
5.1 Baseline Restorer
6.2 buffer Amplifier
6.3 Input Gate
5.4 Bury output
6.6 Oixriminator
5.8 Stretch Amplifier
6.7 Output Pulse Delay
6.8 Output Pulse Width
6.9 External Strobe
5.10 Output Linear Gate
6.11 Bias Amplifier Stage
5.12 Post Amplification and Output Stages
,’
Page
1-l
1.1
l-l
2-l
2-1
2-1
2-l
2-2
2-3
2-3
2-3
3-l
3-1
3-1
3-1
3-l
3-2
3-2
3-3
3-3
4.1
4-1
4-1
4-l
4-1
4-1
4-2
4-2
4.2
4-2
6-1
5-l
S-1
5-l
6-l
5-1
5-4
6-4
6-4
6-4
5-4
5-6
5-6

w
A NEW STANDARD TWO-YEAR WARRANTY FOR ORTEC ELECTRONIC INSTRUMENTS
ORTEC warrants its nuclear instrument products to be free from defects in workmanship and materials. other
than VBCUU~ tubes and semiconductors, for a period of twenty-four months from date of shipment, provided
that the equipment has been used in a proper manner and not subjected to abuse. Repairs or replacement, at
ORTEC option, will be made without charge at the ORTEC factory. Shipping expense will be to the account
of the customer except in cases of defects discovered upon initial operation. Warranties of vacuum tuber and
semiconductors, as made by their manufacturers, will be extended to our customers only to the extent of the
manufacturers’ liability to ORTEC. Specially selected wcwm tubes or semiconductors cannot be warranted.
ORTEC reservestheright to modify the design of its products without incurring responsibility for modification
of previously manufactured units. Since installation conditions are beyond our control, ORTEC does not
assume any risks or liabilities associated with methods of installation other than specified in the instructions,
or installation results.
QUALITY CONTROL
Before being approved far shipment, each ORTEC instrument must pass a stringent set of quality control tests
designed to expose any flaws in materials or workmanship. Permanent records of these tests are maintained for
use in warranty repair and as a source of statistical information for design improvements.
REPAIR SERVICE
ORTEC instruments not in warranty may ba returned to the factory for repairs or checkout at modest expense
to the customer. Standard procedure requires that returned instruments pass the same quality control tests 8s
those used for new production instruments. Please contact the factory for instructions before shipping
equipment.
DAMAGE IN TRANSIT
Shipments shduld be examined immediately upon receipt for evidence of external or concealed damage. The
carrier making delivery should be notified immediately of any wch damage, since the carrier is normally liable
for damage in shipment. Packing materials, waybills, and other such documentation should be presewed in
order to establish claims. After such notification to the carrier, please notify ORTEC of the circumstances so
that we may assist in damage claims and in providing replacement equipment if necesrarv.

1.1
ORTEC 444 GATE0 BIASED AMPLIFIER
1. DESCRIPTION
1.1 Ganaral
The ORTEC 444 Gated Biased Amplifier is an instrument module dasignad to permit an assured linear
rasponse of details in an expanded fraction of a total input spactrum. It includes a pulse stretcher,
a biased amplifier, a linear gate, and a dc restorer. It featura positiva-on-positive pulse pilaup rejaction,
and a fixed output pulse shape at an adjustable delay time or an external strobe time. Since amplitude is
the only variable parameter of each linear output pulse, ambiguities ara virtually eliminated from the
system. Its correlated functions are intarconnactad within the module to provide optimum response and
high performance. The 444 is compatible with all linear and logic instruments in the ORTEC 400 Series
of modular instrumentation, designed in accordance with the preferred practices provisions of AEC
Report TID-20893 (Rev. 2).
1.2 Sasic Functions
The ORTEC 444 Gated Biased Amplifier axpands a region of interest in a spectrum to allow maximum
utilization of existing multichannel analyzers in high rerolution and high counting rata spectroscopy
applications
The 444 features excellent temper&we stability. integral linearity. rasponsa to highcountingrates, and
simplicity of operation. In addition. the linear gate saction faatures total dc coupling with essentially
Z~KI PedStal and feedthrough and the internal automatic pulse pileup rejection reduces spectra
distortion at high count rates.
The 444 is typically used between the main amplifier and a subsequent multichannel arylyzer for
spectrum expansion to permit better measurement of system resolution. Overall system resolution is
improved by the utilization of baseline restoration, pulse pileup rejection, and linear gating facilitias.
Interfacing from the biasad amplifier to the multichannel analyzer is accomplished with the internal
strobed pulse stretcher which provides compatible standardized output pulsas to the ADC input of any
analyzer. The shape of these p&as is assantially independent of the original input pulse shape and bias
level setting. This unit is especially useful in experiments utilizing Ge(Li) Detectors where the pulse
shaping for best resolution typically rasults in an output pulsa that does not satisfy the input raquire-
merits of the subsequent multichannel analyzer. Input pulsa shapes from all available main amplifiers
are directly compatible with the 444, e.g., active filter, RC, or delay line, either unipolar or bipolar
waveshape.
The bias leval features excellent temperature stability, e2OppM par dagree C, and has a range of 0 to
10 volts controlled by a ten-turn bias control. Post gain above the bias level is continuously variable from
0.33 to 30 by a coarse gain witch and a tan.turn fine gain control providing excellent resetability.
The 444 output may be enabled or disabled by a positive gating pulse from 3 to 25 volts, e.g., the
positive logic output from any NIM compatible module can be used for either coincidence or anticoinci-
dence gating. In many applications it is desirable to process a linear signal according to selected Coinci-
dence and/or timing requirements, and thereby reduce the counting rate in subs8quent linear analysis
aquipment, such as multichannel analyzers.

;w s
2-1 .
2. SPECIFICATIONS
2.1
LINEAR Positive unipolar or bipolar, 0.1 to 1OV (1OO:l dynamic
WI*). *12V map, T, 100 OMC min. Zin ~1000~. dc-
i coupled or aecoupled and dc.rWored
GATE
INHIBIT
$tzWply IMX), width X00 “w, Zin XOWQ,
a3V (*25V maw), Zin >lOUOa, dc+Xuplad
STROBE
2.2 cwpua
LINEAR
;W3V (k25V max). Zin >lOOCQ dc+ouplsd
Two linear outputs, WSITIVE and NEGATIVE, simultan-
eous through frdnt panel (2, <1n, and rear panel (2, -
Q3Q), range 0 to 1OV. Tr z 0.5@sac.~ flat topped puke with
width adjustable from 1 to 5psac.
BUSY .Nominal +5V pulss, width equal to the time from the peak
of the input signal to the tid of the output pulse, as set
by the pulse width control, or until tha input discrimin-
ator has been r&et, whichever is longer. Output impedance
<lOQ, decoupled with T, 650 nsec
2.3 Performance
Integral Non-Linearity -.05% (DC-Cwpled or BLR-lo!&, &0.075% (BLR-highl
for T, >300 nsec; (tO.l% for T, >lOO nsec and <3LW
nsec. Specified for dynamic range of 0.1 to 1OV at pulse
width *4M) nsec, and Gain -15; 0.3 to 1OV for Gain
>x15
Temp. Stability Specified in % of full scale input, 0 to 5OoC
Bias Level
Post Gain
Output dc Level
Note:
020 ppm (or 2OO#WC
(t20 ppmPC
(t10 ppm (or WJOpV)/oC
Worst casa is sum of above or e50 ppm/W
Discriminator 0.00596/0c
Automatic Pile-up Rejection
Noise Contribution <lWV, referred to input
Count Rate The centroid of a pulser spectrum at 86% of full scale will
shift less than 0.1% when modulated by 5 x l@ cp of
random signals from a l”Cs sourcedetector combination
with photopeak at 70% of full scale, using ORTEC 450 or
451 amplifier with active filter time constant of lpwc
After an input pulse has reached its peak, the input linear
gate is closed and will not accept any subsequent input
signals until both the output pulse has ended and the input
discriminator is reset

Gate Fe&through
Gate Pedestal
Gain
Stretcher Droop
24 co”trols
GAIN
BIAS LEVEL
INPUT COUPLING
BLR HIGH
BLR LOW
DC COUPLE
MODE
NORMAL
GATED
GATE PERIOD
DISC. LEVEL
OUTPUT DELAY
DC ADJ.
,GATE
STROBE
2-2
Adjustable to OV DC
Continuously variable from X0.33 to X30, product of
COARSE and FINE Gein Settings
The output pulse is essentially flat topped and will change
less than lmVlps9c
COARSE switch (0.68, 2. 5, 10, 201 and FINE l&turn
precision botentiometer (0.5-1.5). for continuous Post Gain
factor from X0.33 through X30, with msetability <o.Ol%
Continuously edjustable 0 to 1OV. l&turn precision po
tentiometer, with resetability u).l%
3.position locking toggle switch, selects input coupling
circuit
AGcoupled input with active baseline restore, fovinput
pul# duty cycle >20%
AC.coupled input with pessive beseline restorer. for input
pulx) duty cycle C20% 1
DCcwpld input, for input pulses from a dc-coupled source
with no baseline offset
Z-position locking toggle switch, ssiects inclusion or ex-
elusion of getinp circuit
Linear Gate circuit is bypassed
Linear Gate circuit is included, for either coincidence or
snticoincidenca mode as selected by rew panel switch
Controls effective enable/diseble period for geted mode.
Range is 0.5 tow
Adjusts the delay period from peek of an input signal to
to’& of output pulse when using Internal Strobe. Range
is0.5tow
22 turn control permits adiustment of output baseline to
flV
Rear panel slide switch. selects either Coincidence of
Anticoincidence Gated Mode,operation
Rear panel slide switch, selects either lntwnal w External
Strobe to determine the output pulse time. Internal Strobe
timing is delayed 0.5 to Ajax after an input pulsa peak by
the Output Delay control. External Strobe timing is prompt

2.5 co”“ecton
LINEAR INPUT
GATE INPUT
POSITIVE OUTPUT
NEGATIVE OUTPUT
BUSY OUT
EXT INHIBIT
STROBE IN
2.6 Power and Mechanical
Power Required
Weight (Shipping)
Weight (Nat)
Dimensions
.
2-3
with the incidence of the external Strobe input pulse. Auto.
matic ceret at,26&4socmaximum if notstrobed, dependmx on
Output Delay adjua$%tW
6NC (UG:lOg4/A). front ~“el (Zi” %l~)on)
BNC (UG-1094/U). front p”el (Zi”>2m)
BNC (UG-1094/U). front panel (2, <l&I,, and mar pati
(20 = 93su
BNC (UG-IOWIU), front panel &, <lfl), and mw p”el
(4, = 93i-a
BNC (UG-1094/U). rear panel (z, <ran)
BNC KlG-1094/UI. rear payI (Zi” .lOWSZ)
BNC (UG-lOB4/U), r-r w (Zi” >lWOQ)
+24V 16SmA +12v 1BOmA
-24V 165mA -12v 6O”lA
lllbs(6kg)
6.6 Iba (3 kg)
Standard double width module (2.70 by 8.714 incherl pw
TID.20893 (Rev.1
2.7 Related Equipment
The ORTEC 444 accepti.signal input pulses from any shaping linear amplifier with a” wtput compatible
with its input requirements, such as ORTEC 410, 435A. 440A, 460, 451, or 486. The outputs an
intended for measurement with a multichannel snalyzw or a single channel analyzer, such as ORTEC
406A. 420A. or 455. They may also be used for increasing the sensitivity of any discrimlnetw, aI
included in many other types of instruments.

3. INSTALLATION
3.1 Geneml lnstellstion Conridemtioos
The ORTEC 444 is designed for installation in 8 stendard Bin and Power Supply, such es the ORTEC
401A/402A. Since this bin isintended for reck mounting, it is IWCBSIB(~to ensure that envvecuum tube
equipment operated in the seme rack will have adequate cooling air circulation to prevent any localized
heating of the 444 transistorized circuits. The temperature of equipment mounted in recks ten easily
exceed the recommended maximum unless precautions are observed. The ORTEC 444 should not be
subjected to temperatures in excessof 1200F KQOC).
3.2 connection to Power
The ORTEC 444 contains no internal power supply; therefore, it obteins its dc operating power from
the standard Bin and Power Supply in which it isinstalled. Always turn power off for die Bin and Power
Supply before inserting or removing any modules. The ORTEC 400 Series of moduler instruments we
designed such that it is not possible to overload the power supply with e full complement of modules in
the bin. However, this may not be true when the bin contains modules other than those of ORTEC
design; check the power supply for any werloed conditions bv testing the dc power levelsafter insertion
of ali modules.
The ORTEC 444 may be operated outside the 4OlA/402A Bin and Power Supply. using e power ex-
tension cable. Be sure that the cable used accents properly for the grounding circuits recommended in
AEC standards of TID-20893 (Rev.). Ground connections ere included to ensure proper reference
voltage feedback into the power rupplv, and these mun be preserve&by the remote cable. Be careful
to avoid ground loops when the module is not phvsicellv installed in the bin during operation.
3.3
3.4
/
Lineer Input Connection .
Lineer input pulses ten be furnished from any ORTEC linear module of the 400 Series. These include
amplifiers, delay circuits, gates, and other pulse handling equipment. The effective input range will be
from the adjusted discriminator level (to.1 to 1Vi up through +lO volts.
When the linear input signalsere furnished through e cable more than four feet long (approximately).
the input should be terminated with the characteristic impedance of the cable. This ten usually be
avoided when shorter cables ere used.
Linear Output Connections
The shaped linear output pulses can be furnished into any other ORTEC Series 409 linear module. or
directly into the ADC input of a multichannel analyzer. It is impoftent to preswye the pulse shape and
amplitude of the output, thus the interoonwcting cable should always be properly terminated. Either of
two standard output impedances may be selected, according to the type cad length of interconnecting
cable and the input impedance of the instrument to which it is connected. The output is available
through e front panel connector, with an output impedsnce of lessthan 1 ohm. or through II rear panel
cowwctor, with 2, - 93 ohms. For most applicetiom proper resistive termination of the cable is
attained by either of two methods indicated below.
One method is the seriesn/pa tormination.“sing the reer panel 93fi Output connector and an appro.
priate length of 93 ohm coaxial cable to transfer the signal into the next module or inrtrument. The
input impedance of the next equipment will probably be on the order of 1ODOohms or more. The total
amplitude of each output pulse will be divided between the 93 ohm output impedance of the 444 and
the input impedsnce of the next module, so e high input impedance is desirable when this se&a
termination method is used.
An alternate method depends upon hunt termination et the remote end of the cable. For this, “se the
front penel 1R Output connector, and whatever type cosxial cable is desired. Then use a ENC Tee et
the input to the next module, to eccept both the cable and e BNC Terminator, selected to match the
characteristic impedance of the cable when connected in parallel with the instrument’s input impedance.
For convenience, ORTEC otockra limited quantity of BNC Tee.conrwctors. in both SOand 100 ohm BNC
. Terminators.

‘3 - 2
3.5 Gate Input
When Gate input signals are required, they will be furnished through the BNC connector on the front
panel of the 444. The function of en input pulse will be to enable,or diseble the 444 Linear Input gete
through an adjusted Gate Period. The enable or disable function must be selected as either Coincidence
or Anticoincidence by a mar panel slide switch.
.
3.6
Gate Input pulses are effective when they rise through +3 volts for a period of et Ieest 100 “sec. A
standard NIM Slow Logic positive pulse source may ba used. The Gate Input circuit is protected to
*25 volts, so a wide variety of alternate sowxs can be used to initiate this control. When OiWatinQ in
the Coincidence mode, the Gate Period must be triggered before the peak of the linaar.input pulse end
must be continued until after the peek hes safely been sensed. When operating in the Anticoincidence
mode, the Gate Period must be triggared prior to e discriminator rasponsn to tha linear input end must
be continued until the discriminator has been reset. Refer to Figure 3.1.
I I I
I I I
I I
I I I
200381 I I I
Jl
I I I
I I
Discriminatorlevel
LinearInput- - - ; - - - ‘T___---- - --w--s
I
I
I I I
I I I
Figure 3-l. Timing Diagram ror Coincidence end Anticoincidence eat&
No Gate Input is required if the front panel MODE switch is set et NORMAL. Likewise, if the front
panel switch is .set et GATED, and the rear panel mode selector is set at ANTI COINC, a Gate Input
pulse is not required except when a linear input signal is to be rejected. When tha~e switchas are set for
GATED and COINCIDENCE. respectively, a linear input pulse will beaccepted only if itit ?uxOIWdd
by e time coincident Gate Input ~“1%.
Connection for Busy Output
The duration of each Busy Output signal is from the time an input pulse peak is detected until the
resulting output pulse has been generated end the input diwiminator hes $en reset if no INHIBIT
signal is present. This identifies each period during which a new input pulse cennot be eCx%Xed in tha

.
3-3
444. This output can be integrated externally to indicate the total deed time, or it ten be furnished es e
control to the pulse source and prevent generation of pulses when they cannot be accepted.
3.7 Use of Inhibit Input
The purpore of the Inhibit input is to permit blocking the 444 Linear Gate during periods beyond its
own busy period to account for system deed time. When any linear signals processed by the 444 cannot
be measured in subsequent instruments of e system such es e multichannel analyzer, and e signal indicet-
ing such a condition (e.g. ADC busy) is evsilable, the INHIBIT function can be used in the 444 to reduce
unnecessery loading for the remaining sytem components.
3.8 Use of External Strobe
During normal operation of the 444. eech output pulse will be generated es e function of e linear input
peak end a linear delay from 0.5 to 5j~sec eccwding to the adjustment of the front panel control. If
external time synchronization of the output pulses is desired, the Strobe switch on the reer penel ten b,
set et External and each output pulse will then occur when it is triggered by e signal through the Ext.
Strobe connector on the reer panel.
Typical examples of conditions which could use the External Strobe to edvantege include (1) delay
required greater than the 5&sec maximum or (2) en output pulse time which isnotdependentupon the
peak detection time. In either cese. consider the logic when setting up the Ext. Strobe wise source. If
the strobe occurs before the input peak, the output pulse will not have its characteristic flat top and
may even fail to reach its full amplitude. If the strobe is delayed longer then 25m. an output will not
be generated; this is because the stretcher will automatically wet without generating en output at 8
delay of 5 to 25wsec depending on the setting of the front panel output delay control.

4-l
4. OPERATION
4.1 Selectiix~oflnput Circuit Coupling
Any of three linear input circuits can be selected with the locking toggle switch OR the front panel. They
are OCCoupled, Active Baseline Restorer (HIGHt, or Passive Baseline Restorer (LOW). The proper
selexion will depend on the type of output circuit in the module from which linear pulses are furnished
into the 444.
The DC Couple switch position provides an optimum signal transfer circuit with 1000 ohms input im-
pedance if the pulses are furnished from an amplifier with a decoupled output and a properly adjusted
zero baseline. If the source does not include baseline restoratiqn. use e capacitive coupling into the 444
and select either HIGH or LOW baseline restoration as the input circuit.
For any accoupled linear signal input, select one of the DC-Restore input circuits in the444. In general,
the Active (HIGH) circuit is intended for higher count rates. and Passive (LOW) for lower count rates.
There is no precise dividing line, because of the various shaping time constants which may affect pulse
shape. For lpseaz pulses, the division is approximately 15.000 counts per second. The most practical
method for selecting between Active and Passive is an observation of the Output, using the circuit which
provides the better results.
4.2 Discriminator Level Adjustment
The purpose for the adjustable discriminator level is to prevent response to alI noise pulser. Therefore, it
should beadjusted high enough in its tO.1 to +1 volt rang to ensure discrimination against the maximum
noise amplitude which may exist at the input to the 444 in the system. Since the logic in the 444 pre
van” response to a new input pulse until the discriminator is reset, but permits acceptance at that time
unless an output pulse has not been generated, t[hidr
small amount of pileup to occur if the input pulse has a ver/ long time qonstant decay. Although this
16iterference is possible, it is unlikely in mat applications. Still, an unnecessarily high adjustment is not
recommended.
4.3 Output Delay Adjuslment
When using the Internal Strobe, the delay adjustmeni permits normalizing timing in the system in which
the 444 is operated. The delay interval is measured from the time the internal stretch amplifier senses8
peak amplitude in the accep~ad linear input pulse, and is adjustable through the range of 0.5 to ~/MC.. At
the end of this delay period, the Width control opens the output gate and applies the peak amplitude
pulse to the input of the biased amplifier portion of the 444.
4.4 Gain Adjustment
The Coarse and Fine Gain controls permit adjustment of the amplification factor used to expand the
linear pulse amplitude which exce,eds the bias cut. Since there is an overlap of the combined gain factors,
the gain may be adjusted for any value between 0.33 and 30. The pott amplification factors of less than
1, that is, gains of 0.33 to 1, are provided to allow an output full range compression from +lO volts down
to t3.3 volts. This simplifier the interface with analog~to digital converters with alinear rangeof less than
10 volts.
4.5 Bias Level Adjusbnent
After chasing the desired expansion factor. this is the pat gain, the bias control should be adjusted such
that the radiation peak of principal interest is conveniently located within the input voltage range of the
ADC which is to encode the lineer signal.
The front panel Bias Level &mtrol consist of a ten-turn dial and precision potentiometer which reads
directly the adjusted bias level in volts. It may be set at any level within its 0.00 through 10.00 volts
rang+ and locked to prevent accidental readjustment. The selected level will be the bias cut point for all
linear pulses as they pass through the biased amplifier, and the amplitude by which each linear pulse
.

4-2
4.6
4.7
4.8
4.9
exceeds the bias level will be expended by a factor of 0.33 through 30, determined by the Gain controls,
and furnished promptly to all four Output connectors. In e pulsa height analysis wtem. the adjusted
bias level will determine the equivalent energy level in the spectrum which will be meeswed es the
minimum energy.
Output DC Adjustment
The quiescent level for the output, through both the front end rear panel conneCtor% should be at
ground potential. Use the test point for the front panel Output connector which is to be wed (either
Negative or Positive), and adjust the wewdriver control es necesse~ to sat the level at ground potential
when there are no input signals to the 444.
Gated Operation
No Gate Input pulse is required if the front panel Mode witch is set et Normal. Likewiwr, if this switch
is set et Gated and the rear penel slide switch is set et Anti-~pincidence. linear input pulse8 can be
accepted when there is no signal through the Gate Input connector. Whenever e signal is furnished
through the Gate Inputand AntiCoincidence is effective, all linear input signals ere inhibited thmvghwt
the triggered Gate Period. To be effective, the Gate Period must be edjusted to overlap the duration of
discriminator response to any pulse which is to be inhibited by the Gate Input signal. If the lineer input
triggers the discriminator before the Gate Input, or if the Gate Period permits termination of the Gate
control prier to discriminator recovery, there will be en output but its amplitude will not usually
reflect the input peek amplitude.
When the 444 is set for Gated Coincidence operation, e linear input signal will be accepted for stretch-
ing only if there is e time coincident Gate Input. The Gate Input signal must occur before the linear
input peak, and the Gate Period must be long enough to continue the control bewnd the internal
detection of the peek amplitude. Refer to figure Fl. 1
Overall Logic
When en input pulse arrives et the Linear Input, it is applied directly to the discriminator. As its am-
plitude rises through the adjusted discriminstor threshold, the discriminator may be fired or it may still
be set because of not having recwered from e previous input pulse. The linear input pulse will not be
accepted unless the discriminator had recaered and ten be triggered by the new pulse; it will also be
rejected if (1) en output pulse her not been completed for e previously accepted input: (2) the operating
mode is Gated Coincidence and no Gate Input has been furnished; (31 the operating mode is Gated
Anti-Coincidence, e Gate Input signal has been furnished, and the Gate Period is still effective: or (4)
there is en lnhihit signal present.
When the discriminator is triggered prior to a Coincidence Gate Input, the linear input signal is applied
to the stretch circuit et the leading edge of the Gate Input. This is e critical time, and en output signal
will result: its amplitude is equal to (1) the peek input amplitude, or (2) the amplitude et the release
(critical) time if this occurs after the peek. Thus. it is important that the gete be released duringtherise
time of e linear input pulse. By similar logic, the end of en effective Gate Period should never occur
before the peek amplitude has been sensed, or there will bee false amplitude output.
internal Adiustment
The output pulse width is fixed et 2.5~ fwhm when the 444 Iewes the fectory. These pulse widths
ten be readjusted, if required with en internal control.

Refer to the Block Diagram and Schematics at the end of this manual.
5.1
5.2
5.3
Beselins Restorer
The input signals to the 444 will pees either through or erwnd the Beeoline Restorer circuit, 88 selected
by front panel switch Sl. When the twitch is set et DC Couple, the circuit is bypassed. If be&in* ‘.
restoration is desired, the switch can be set et either Low or High, according to the relative count rete of
the input signals. When Sl Is set at Low, the wine is restored by e constant current of lC@&, plovid.
ing e restoration ra” of approximately lOmV/#sec. When Sl is set et High, the current is 3mA, for e
WStOratiOn rateof about 3oOmV/#ee~. These voltege rcatoretion ret= ten be varied by changing the velue
Of C2. The baseline restoration circuit includm Ql, CU. (13, Q4, and Dl.
Buffer Amplifier
The restoration circuit is followed by e non-invwting buffer amplifier, including 05 through Q8 end
Q53. with e gain of approximetely one. The gein of this step is given by the ratio R21 + R15 Thee04
R15 .
is dc-coupled from this etege to the output, so en adjustment is provided in ee& etege to set its dc level
et LWO. Potentiometer R13 should be adjusted for a zero volt level et the output of the buffer amplifier,
meesured at TPl. The Buffer Amplifier drivef the Input Geteend the Discriminator.
Input Gate
Transistor 09 is the shunt type Input Gate. When the front panel Mode witch is sat et Normal, Q9
retr#eins off until the peek of the input pulse, when it saturates and clamps the gate of 010 to ground.
09 continues in Pturetion until the input signal fells below the Discriminator level end the 444 Output
pul~a has been completed, and the Input Gate is closed through this time. This preuenr, the 444 from
accepting a second pulse until it has completed processing the first pulse, end elimineter positive on
positive pile-up. Details we shown in Figures 5-l end 5.2.
When the Mode switch is set et its Gated position, the functional mode must be selected by the rear
panel CoinclAnti switch, and the Input Gate provides the edded function together with its pile-up
rejection function. When the Coincidence mode is selected, 09 will be normally turned on and raturated.
clamping the gate of 010 to ground. In order to open the gate. e logic pulse mun be furnished through
the Gate input BNC to turn 09 off. The input logic pulse is reshaped for en adjusted Gate Pried by
IC5, 1331, and Q32, and applied to the input gets drive circuit, Q24, 025, and 027, to open Bate 09
for the duration of the Gate Period. The Gate Period must overlsp the peek of the linear input signel if
the input signal is to be accepted.
When the AntiCoincidence mode is selected, the control of Q9 is the inverse of the above discussion.
09 will normally be off, the gate will be open except when it is closad bye Gateinput logic pulse, end
lineer input signals will normally~ be eccepted. In order to obtain proper Anti-Coincidence control. the
Gate Period which is triggered by the Gate input pulse must totally overlep the timeduring which the
linear input pulse exceeds the discrimination level. If the range of the Gate Period needs to be increesed.
change the value of C34 to e larger capacity for the longer control period.
5.4
5.5
Busy Output
The Busy Output is e monitor of the internally created deed time in the 444. This signal begins at the
peek of the linear input and continues to the completion of the 444 output pulse, ending then only if all
of the conditions which will enable the Input Gate have been fulfilled. Refer to the timing diagems of
Figures 5-l and 52, and to Section 4.8.
Discriminator
.
5-l
5. CIRCUIT DESCRIPTION
The Disqiminetor permits the 444 to reject all input pulses which fail to rise above the Selected
disriminetion level, such 86 noise pulses. The discriminator level can be adjusted from +O.l throu&
+lV with front panel control R125. When the discriminator level is exceeded by e linear input signal end
the input Gate is open, e signal is sent to the Stretch Amplifier to stretch the input pulse.

6-2
Peak
DiscriminatorLevel
output
DelayPulse (KM) I I
output
Width Pulse (IC4-141
Input linear Gate
t ~--II
I
444 Positive
Note:
Remarksin parenthesis indicate component
and pin where signals can be monitored.

Peak
Discriminater.,LeveC,
DiscriminatorOutput
Output DelayPulse
(IC3-8) r 1
OutputWidth Pulse
(IC4-14) I I
Input linear 6ate
t
Busyoutput I
444 Positive
Linear Output
2co380 Remarksin parenthesisindicate component
and pin where signals can be monitored.
.
Figure 52 444 Timing Diagram for PileUp Input Pulses

,
6-4
6.6
6.7
6.8
5.9
&r&h Amplifier
The Stretch Amplifier is a non-inverting amplifier composed of QlO through Q23, 061. and 052. The
amplifier loop is normally cloaad, with currant through 029 and D 11. When the Discriminator sands im
signal to stretch the input pulse, the current through Q29 is switched to Q28. Then stretch capacitor
Cl0 is charged through Dll to the peek voltage of the input signal. After the peak has occurred, Dll Is
back biased and the peak voltage is stored on Cl0 until 029 is switched on again at the end of the
output pulse. A high input impedance, non-inverting amplifier, Q18 to Q20 and 021 to 023. acts as a
buffer and driver for the voltage on capacitor ClO. This amplifier is included imide the stretch amplifier
loop to provide better linearity and stability. 015.(117 monitors the voltage acmes Dll and produces a
peak detect signal when Dll becomes back biased. The peak detwt signal is routed to the control logic
to initiete the delay signal. which will initiate the output width signai. Potentiometer R42 is provided to
adjust the voltage at TP2 to zero when the input voltage to 010 is zero.
output Pulse Deisy
The Delay circuit consists of 041 and Q42 and two gates of iC3 which form a one shot multivibrator.
The leading edge of the peak detect signal trigger this stage at IC3 Pin 6, and initiates the delay. The
width of the Delay pulse can be varied from 500 nsec to 5#sec with front penel control Rl17; this range
can be increased by using a larger value for C30.
The leading edge of the Delay pulse, at iC4 Pin 6, sets the fiipfiop, iC3 and RX, which in turn controls
the input Gate through IC2 and iC8. The circuit of IC3 and IC4 is actually a one shot multivibrator,
with the additional feature that it can be reset at IC3 Pin 1, and thus is normally operated as a flip-flop.
Output Pulse Width
The Delay pulse is routed to the Output Pulse Width control circuit, including Q47 and gates in 164 and
IC7. The trailing edge of the Delay pulse energizes the Width circuit at IC4 Pin 2, to generate en output
pulse width of 0.5 to 5usec. depending on the setting of R81. This internal adjustment is preset at the
factory for an output pulse width of 2.5~~. The range :f adjustable widths can be increased by using a
larger value for capacitor C25. This output pulse will drive the Output Linear Gate, which includes Q26,
and 035 to 038.
External Strobe
The External Strobe circuit is enabled when the rear panel switch S3is set et External. C32 increases the
duration of the Delay pulse for this control mode. The Output Pulse Width control circuit can be
triggered only by the Strobe Input, ICI Pin D. If an External Strobe signal is supplied while the output
Delay circuit is set, an output will be ganerated promptly, controlled by the Width control circuit. The
Width pulse is differentiated, and its trailing edge raaem the IC3/IC4 flip-flop at IC3 Pin 1 through Q48.
Simultaneously, the Delay oneshot is reset with the current switch, CM-Q46. to recharge C30 and C32
rapidly.
in the event that no Strobe pulse is furnished while the Delay flip-flop is set, the trailing edge of the Delay
pulse. differentiated at Q47, resem the IU/lGl flip-flop and enables the Linear Gate.
The duration of the Delay before automatic reset of the logic without generating an Output (because the
Width circuit is not triggered) is controlled by the setting of R117. The range is 5 to 25psec. since C32 is
included in the circuit.
510 Output Linear Gate
The Stretch Amplifier is followed by an Output Gate, which in turn connects to the Bias Amplifier. The
Gate circuit, Q35Q338. will normally drain wrrant from the Bias stage through Rl jon 444-0301-Sl) to
keep diodeD1 in a back biased condition. This effectively disconnects the Stretch Amplifier output from
the Post Amplification stages and the 444 Linear Outpum. The Output Pulse Width circuit will turn
038 off, to strobe the Stretch Amplifier output into the Bias stags for a time equal to the Width pulse
duration.

6-6
6.11 Bias Amplifier Stage
Operational amplifier A3 is the Bias Amplifier Stag%. It is a summing junction for the current, i+ from
the Stretcher output and the current, ib. from the bias level current source, as shown in Figure 5-3. The
amplifier feedback toop is divided into two paraiM branches by diodes Dl and D2, and the non-linear
,chsracteristics of the diodes allows only ona feedback path to be active at any one time. When the net
input currant, is - ib, is positive, D2 conducts and current flows through RS to close the feedback loop
with * total gain of unity for the 5tagn since&&j = 1.; when the net input current is negative. Dl
conducts and current flows through R4; ib this case, the gain of the stage is R4+R(Dlj 1
R75 + R, zs The signal
current, is is given by A,; the bias current, ib. is determined by the setting of the Bias Level
control, R47. By this method, a signal which exceeds the bias level will be furnished through to the Post
Amplifier, while all signal levels less than the bias will be effectively disconrwcted from the Post
Amplifier.
The dc balance for the A3 amplifier is obtained by monitoring TP3 while adjusting R3 on the 444-0301
printed circuit. The bias current supply is encapsulated to obtain b8tter temperatufe stability, and is
factory adjusted for a 10 volt bias level range using R46.
R75 2K
@SW
I
R4 51.1 0’
N
R5 4.02K
I 2p 02
l e out
~7 ib
R47 Bias Level
F
Control [FP]
Fipum 53. Bias Amplifier Stage
‘R75 is located on Drawing 444-020161

S-6
5.12 Post Amplification and Oumt Stases
The Bias Amplifiarstaga is followed by a 31 passive attanuatoy, R6 through RS. which make up tha Fine
Gain control. 1310 is adjusted to compensate for the negative Output Amplifier input current when no
signal is present.
Amplifier Al is feedback in a non-inverting configuration, with a closed loop gain given by:
The first factor is Fine Gain, ranging from 0.5 to 1.5. The second factor is Coarse Gain, with valuer of
0.66, 2, 5, 10. and 20. R7x is defined as the resistance between the wiper arm of R7 and R6. Rn takas
the value of R16 through R24, depending on the Coarse Gain switch setting.
The Negative Output of the 444 is the output of amplifier Al. The Positive Output is obtained by
simply inverting the Negative Output with Amplifier A2. where the closed loop gain is given by%. In
both Amplifiers, the de baseline is balanced with the DC Adjust control. R46, located on the front panel.
Transistors Ql through Cl4 provide current limitation for the linear outputs, to prevent damage by a
short across one of the wtput connectors. If the output duty cycle is such that it exceeds the power
dissipation rating of the operational amplifier, these same transistors will current-limit the supplies to
avoid any damage to the instrument.