Enclustra Mercury CA1 User manual

Mercury CA1 FPGA Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mercury CA1 FPGA module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury CA1 FPGA
module.
Summary
This document first gives an overview of the Mercury CA1 FPGA module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product ME-CA1 Mercury CA1 FPGA Module
Document Information Reference Version Date
Reference / Version / Date D-0000-421-002 05 25.07.2019
Approval Information Name Position Date
Written by DIUN Design Engineer 13.08.2016
Verified by GLAC Design Expert 10.10.2016
Approved by DIUN Manager, BU SP 25.07.2019
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2019 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior
written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the date
of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
05 25.07.2019 DIUN Added information on power supplies and heat sink, updated DDR
memory and SPI flash types, other style updates. Added information
on R6.1 modules.
04 21.08.2018 DIUN Minor corrections and style updates
03 19.01.2018 DIUN Added module variant, other style updates
02 04.05.2017 DIUN Updated EEPROM map, block diagram and footprint information
01 27.12.2016 DIUN Version 01
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Table of Contents
1 Overview 5
1.1 General ................................................... 5
1.1.1 Introduction ................................................ 5
1.1.2 Warranty .................................................. 5
1.1.3 RoHS .................................................... 5
1.1.4 DisposalandWEEE ............................................ 5
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.6 ElectrostaticDischarge .......................................... 6
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features................................................... 6
1.3 Deliverables ................................................ 6
1.4 Accessories................................................. 6
1.4.1 ReferenceDesign ............................................. 6
1.4.2 Mercury+PE1BaseBoard ........................................ 7
1.5 IntelToolSupport............................................. 7
2 Module Description 8
2.1 BlockDiagram............................................... 8
2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 TopandBottomViews .......................................... 11
2.4.1 TopView .................................................. 11
2.4.2 BottomView................................................ 11
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.1 TopAssemblyDrawing .......................................... 12
2.5.2 BottomAssemblyDrawing........................................ 12
2.6 ModuleFootprint ............................................. 13
2.7 MechanicalData.............................................. 14
2.8 ModuleConnector ............................................ 14
2.9 UserI/O................................................... 15
2.9.1 Pinout.................................................... 15
2.9.2 Dual-PurposePins............................................. 17
2.9.3 DifferentialI/Os .............................................. 18
2.9.4 I/OBanks.................................................. 18
2.9.5 VREFUsage................................................. 19
2.9.6 VCC_IOUsage ............................................... 19
2.9.7 SignalTerminations ............................................ 21
2.10 Power.................................................... 21
2.10.1 PowerGenerationOverview ....................................... 21
2.10.2 PowerEnable/PowerGood........................................ 21
2.10.3 VoltageSupplyInputs........................................... 22
2.10.4 VoltageSupplyOutputs ......................................... 22
2.10.5 PowerConsumption............................................ 23
2.10.6 HeatDissipation.............................................. 23
2.11 ClockGeneration ............................................. 24
2.12 Reset .................................................... 24
2.13 LEDs..................................................... 24
2.14 DDR2SDRAM ............................................... 25
2.14.1 DDR2SDRAMType ............................................ 25
2.14.2 SignalDescription............................................. 26
2.14.3 Termination................................................. 26
2.14.4 Parameters................................................. 26
2.15 SPIFlash .................................................. 27
2.15.1 SPIFlashType ............................................... 27
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2.15.2 SignalDescription............................................. 28
2.16 GigabitEthernet.............................................. 28
2.16.1 EthernetPHYType............................................. 28
2.16.2 SignalDescription............................................. 28
2.16.3 ExternalConnectivity ........................................... 29
2.16.4 MDIOAddress............................................... 29
2.16.5 PHYConfiguration............................................. 29
2.17 FTDIUSB2.0Controller.......................................... 31
2.17.1 FTDIType.................................................. 31
2.17.2 FTDI Synchronous FIFO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.18 Real-TimeClock(RTC)........................................... 32
2.18.1 RTCType .................................................. 32
2.19 SecureEEPROM .............................................. 32
2.19.1 EEPROMType ............................................... 33
2.20 CurrentandPowerMonitor ....................................... 33
2.20.1 MonitorType................................................ 33
3 Device Configuration 34
3.1 ConfigurationSignals........................................... 34
3.2 ConfigurationMode............................................ 35
3.3 JTAG..................................................... 35
3.3.1 JTAGonModuleConnector ....................................... 35
3.3.2 ExternalConnectivity ........................................... 35
3.4 PassiveSerialConfiguration ....................................... 35
3.4.1 SignalDescription............................................. 36
3.5 ActiveSerialConfiguration........................................ 36
3.5.1 SignalDescription............................................. 37
3.6 SPIFlashProgrammingviaJTAG..................................... 37
3.7 SPI Flash In-System-Programming using Quartus-II Programmer . . . . . . . . . . . . . . . . . . 37
3.8 SPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8.1 SignalDescription............................................. 39
3.9 Module Configuration via FTDI USB 2.0 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9.1 FTDIPortBConfiguration ........................................ 39
3.9.2 FPGA Passive Serial Configuration via FTDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.9.3 SPI Flash Programming via FTDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.10 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4 I2C Communication 42
4.1 Overview .................................................. 42
4.2 SignalDescription............................................. 42
4.3 I2CAddressMap ............................................. 42
4.4 SecureEEPROM .............................................. 43
4.4.1 MemoryMap ............................................... 43
5 Operating Conditions 46
5.1 AbsoluteMaximumRatings ....................................... 46
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 Ordering and Support 47
6.1 Ordering .................................................. 47
6.2 Support................................................... 47
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1 Overview
1.1 General
1.1.1 Introduction
The Mercury CA1 FPGA module combines the low-cost Intel® Cyclone® IV FPGA device with DDR2 SDRAM,
FTDI USB 2.0 controller, Gigabit Ethernet, LVDS I/Os, forming a high-performance and low-cost processing
system ideal for high-speed and DSP applications.
The use of the Mercury CA1 FPGA module, in contrast to building a custom FPGA hardware, significantly
simplifies system design and thus shortens time to market and decreases the development effort of your
product.
Together with Mercury base boards, the Mercury CA1 FPGA module allows the user to quickly build a system
prototype and start with application development.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
1.1.3 RoHS
The Mercury CA1 FPGA module is designed and produced according to the Restriction of Hazardous Sub-
stances (RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mercury CA1 FPGA module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mer-
cury CA1 FPGA module.
1.1.5 Safety Recommendations and Warnings
Mercury modules are not designed to be “ready for operation” for the end-user. These can only be used in
combination with suitable base boards. Proper configuration of the hardware before usage is required.
Ensure that the power supply is disconnected from the board before inserting or removing the Mercury CA1
FPGA module, connecting interfaces, replacing batteries, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-
voltage on power or signal lines can also cause permanent damage to the module.
Warning!
It is possible to mount the Mercury CA1 FPGA module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
CA1 FPGA module.
The base board and module may be damaged if the module is mounted the wrong way round and
powered up.
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1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mercury CA1 FPGA module is a Class A product and is not intended for use in domestic environments.
The product may cause electromagnetic interference, for which appropriate measures must be taken.
1.2 Features
•Intel Cyclone IV 60 nm FPGA EP4CE30/EP4CE75/EP4CE115, FBGA 484 package
•Up to 168 user I/Os up to 3.3 V, available in one of the following combinations:
•25 differential pairs and 98 single-ended I/Os
•146 single-ended I/Os
•168 single-ended I/Os (in custom configuration where the differential input termination resistors
are removed)
•Up to 256 MB DDR2 SDRAM
•16 MB SPI flash
•Gigabit Ethernet
•FTDI USB 2.0 device controller
•Real-time clock
•Power and current monitor
•Small form factor (56 ×54 mm)
•5 to 15 V supply voltage
1.3 Deliverables
•Mercury CA1 FPGA module
•Mercury CA1 FPGA module documentation, available via download:
•Mercury CA1 FPGA Module User Manual (this document)
•Mercury CA1 FPGA Module Reference Design [2]
•Mercury CA1 FPGA Module IO Net Length Excel Sheet [3]
•Mercury CA1 FPGA Module FPGA Pinout Excel Sheet [4]
•Mercury CA1 FPGA Module User Schematics (PDF) [5]
•Mercury CA1 FPGA Module Known Issues and Changes [6]
•Mercury CA1 FPGA Module Footprint (Altium, Eagle, Orcad and PADS) [7]
•Mercury CA1 FPGA Module 3D Model (PDF) [8]
•Mercury CA1 FPGA Module STEP 3D Model [9]
•Module Pin Connection Guidelines [10]
•Mercury Master Pinout [11]
•Enclustra Modules Heat Sink Application Note [15]
1.4 Accessories
1.4.1 Reference Design
The Mercury CA1 FPGA module reference design features an example configuration for the Cyclone IV FPGA
device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
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The reference design can be downloaded from the Enclustra download page [2].
1.4.2 Mercury+ PE1 Base Board
•168-pin Hirose FX10 module connectors (PE1-200: 2 connectors; PE1-300/400: 3 connectors)
•System controller
•Power control
•System monitor (PE1-300/400)
•Current sense (PE1-300/400)
•Low-jitter clock generator (PE1-300/400)
•Accelerometer/magnetometer/temperature sensor (PE1-300/400)
•microSD card holder
•User EEPROM
•eMMC managed NAND flash (PE1-300/400)
•PCIe ×4 interface
•USB 3.0 device connector
•USB 2.0 host connector (PE1-200: 1 connector; PE1-300/400: 4 connectors)
•Micro USB 2.0 device (UART, SPI, I2C, JTAG) connector
•2×RJ45 Gigabit Ethernet connectors
•mPCIe/mSATA card holder (USB only) (PE1-300/400)
•SIM card holder (optional, PE1-300/400 only)
•SMA clock and data in/out (optional, PE1-300/400 only)
•1×FMC LPC connector (PE1-200)
•1×FMC HPC connector (PE1-300)
•2×FMC LPC connector (PE1-400)
•2×40-pin Anios pin header
•3×12-pin Pmod™ pin header
•5 to 15 V DC supply voltage
•USB bus power (with restrictions)
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
1.5 Intel Tool Support
The FPGA devices equipped on the Mercury CA1 FPGA module are supported by the Quartus Prime Lite
Edition (or Quartus II Web Edition, for older software versions), which is available free of charge. Please
contact Intel for further information.
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2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mercury CA1 FPGA module is the Intel Cyclone IV FPGA device. Most of its I/O
pins are connected to the Mercury module connectors, making 25 differential pairs and 98 single-ended
user I/Os or 146 single-ended user I/Os (168 in custom configuration where the differential input termination
resistors are removed) available to the user.
The FPGA device can be configured with a bitstream residing in the on-board SPI flash, via FTDI USB 2.0
controller fitted on the module, via an external microcontroller or via the JTAG interface connected to Mer-
cury module connector.
The memory subsystem is built from a 16 MB SPI flash and 128 or 256 MB DDR2 SDRAM in the standard
configuration.
Further, the module is equipped with a Gigabit Ethernet PHY, making it ideal for communication applications.
An FTDI USB 2.0 controller is fitted on the module to easily implement a communication link to a host PC.
A real-time clock is available on the module and is connected to the global I2C bus. A power and current
monitor may be optionally equipped on the module and connected to the global I2C bus.
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On-board clock generation is based on a 50 MHz crystal oscillator.
The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of
these voltages are available on the Mercury module connectors to supply circuits on the base board.
Up to four LEDs are connected to the FPGA pins for status signaling. Another LED is connected to the FTDI
USB 2.0 controller user pin for the same purpose.
2.2 Module Configuration and Product Codes
Table 1 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
Product Code FPGA DDR2 SDRAM FTDI USB 2.0 Temperature Range
ME-CA1-30-8C-D7 EP4CE30F23C8N 128 MB X0 to +70◦C
ME-CA1-75-8C-D7 EP4CE75F23C8N 128 MB X0 to +70◦C
ME-CA1-115-8C-D8 EP4CE115F23C8N 256 MB X0 to +70◦C
ME-CA1-115-7I-D8 EP4CE115F23I7N 256 MB X-40 to +85◦C
Table 1: Standard Module Configurations
The product code indicates the module type and main features. Figure 2 describes the fields within the
product code.
Figure 2: Product Code Fields
Please note that for the first revision modules or early access modules, the product code may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 Article Numbers and Article Codes
Every module is uniquely labeled, showing the article number and serial number. An example is presented
in Figure 3.
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Figure 3: Module Label
The correspondence between article number and article code is shown in Table 2. The article code repre-
sents the product code, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mercury CA1 FPGA Module Known
Issues and Changes document [6].
Article Number Article Code
EN100009 ME-CA1-30-8C-D7-R5
EN100010 ME-CA1-75-8C-D7-R5
EN100046 ME-CA1-115-8C-D8-R5
EN100929 ME-CA1-75-8C-D7-R4
EN100930 ME-CA1-30-8C-D7-R4
EN101222 ME-CA1-30-8C-D7-R6
EN101224 ME-CA1-30-8C-D7-X2-R6
EN101225 ME-CA1-75-8C-D7-R6
EN101227 ME-CA1-115-8C-D8-R6
EN101228 ME-CA1-115-7I-D8-R6
EN101229 ME-CA1-115-8C-D8-NEF-X1-R6
EN102569 ME-CA1-30-8C-D7-R6.1
EN102570 ME-CA1-30-8C-D7-X2-R6.1
EN102571 ME-CA1-75-8C-D7-R6.1
EN102572 ME-CA1-115-8C-D8-R6.1
EN102573 ME-CA1-115-7I-D8-R6.1
EN102574 ME-CA1-115-8C-D8-NEF-X1-R6.1
Table 2: Article Numbers and Article Codes
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2.4 Top and Bottom Views
2.4.1 Top View
Figure 4: Module Top View
2.4.2 Bottom View
Figure 5: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 6: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 7: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.6 Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board.
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 72 or 74
mm and having different topologies for the mounting holes. If different module types shall be fixed on the
base board by screws, additional mounting holes may be required to accommodate different modules. The
footprints of the module connectors for the base board design are available for different PCB design tools
(Altium, PADS, Eagle, Orcad) [7] and include the required information on the module sizes and holes.
The maximum component height on the base board under the module is dependent on the connector
type. Please refer to the Hirose FX10 series product website for detailed connector information [12]. The two
connectors are called A (J700) and B (7801).
Figure 8: Module Footprint - Top View
Warning!
It is possible to mount the Mercury CA1 FPGA module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
CA1 FPGA module.
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2.7 Mechanical Data
Table 3 describes the mechanical characteristics of the Mercury CA1 FPGA module. A 3D model (PDF) and
a STEP 3D model are available [8], [9].
Symbol Value
Size 56 ×54 mm
Component height top 3.0 mm
Component height bottom 1.2 mm
Weight 18 g
Table 3: Mechanical Data
2.8 Module Connector
Two Hirose FX10 168-pin 0.5 mm pitch headers with a total of 336 pins have to be integrated on the base
board. Up to four M3 screws may be used to mechanically fasten the module to the base board. Do not
use excessive force to tighten the screws, as this could damage the module.
The pinout of the module connector is found in the Mercury Master Pinout Excel Sheet [11]. The connector
is available in different packaging options and different stacking heights. Some examples are presented in
Table 4. Please refer to the connector datasheet for more information.
Reference Type Description
Mercury module connector FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm pitch
Base board connector FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4 mm stacking
height
Base board connector FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5 mm stacking
height
Table 4: Module Connector Types
Figure 9 indicates the pin numbering for the Mercury module connectors from the top view of the base
board. The connector pins are numbered as follows:
•Connector A: from J700-1 to J700-168
•Connector B: from J701-1 to J701-168
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Figure 9: Pin Numbering for the Module Connector
Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9 User I/O
2.9.1 Pinout
Information on the Mercury CA1 FPGA module pinout can be found in the Enclustra Mercury Master Pinout
[11], and in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mercury CA1 FPGA module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The available I/O types on the Mercury CA1 FPGA module, possible limitations, and the naming convention
for the user I/Os are presented in Table 5.
The clock capable pins are marked with “CLK” in the signal name. For details on their function and usage,
please refer to the Intel documentation.
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Signal Name Description Dir. Term. Comment
IN_B<n>_CLK<x>_<PP>_<p> Differential input clock
pair
In 100 ΩEach differential input
clock pair can optionally
be used as two single-
ended input clocks. For
that purpose the 100
Ωtermination resistor
must be removed.
IN_B<n>_CLK<y>_<PP> Single-ended input
clock
In -
IO_B<n>_L<z>_<PP>_<p> Differential I/O pair In/Out - Each differential I/O pair
can optionally be used
as two single-ended
I/Os.
IO_B<n>_RX_L<z>_<PP>_<p> Differential input pair In 100 ΩEach differential input
pair can optionally be
used as two single-
ended inputs. For that
purpose the 100 Ωter-
mination resistor must
be removed.
IO_B<n>_<PP> Single-ended I/O pin In/Out - -
IO_B<n>_S_<PP> Restricted single-ended
I/O pin
In/Out - These I/Os can only be
used if no differential
modes of any FPGA
banks are used.
IO_B<n>_<f>_<PP> Single-ended I/O pin,
optional function
In/Out -
IO_B<n>_S_VREF_<PP> Restricted single-ended
I/O pin, optional VREF
pin
In/Out - These I/Os can only be
used if no differential
modes of any FPGA
banks are used.
Table 5: I/O Types Description and Naming Convention
Where:
•<n> represents the FPGA bank number
•<x> represents the differential clock pin number
•<z> represents the differential pin number
•<PP> represents the package pin
•<p> represents the polarity (P = positive, N = negative)
•<f> represents the optional function (e.g. VREF, RUP, RDN)
For example, IO_B4_VREF_AA18 is located on pin AA18 of I/O bank 4 and it can be used as a VREF pin for
that specific bank.
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Warning!
Using differential signals in single-ended mode may have an effect on other differential signals located
in the same FPGA bank. Always check your pinout with Intel Quartus software.
Table 6 includes information related to the available I/O types in each I/O bank and to the number of I/Os.
Bank 2 Bank 3 Bank 4 Bank 5 Bank 6
Signal Name D1SE1D SE D SE D SE D SE Total
IN_B<n>_CLK<x>_<PP>_<p> 1 - 1 - 1 - - - - - 3 pairs
IN_B<n>_CLK<y>_<PP> - - - - - - - 2 - 2 4 pins
IO_B<n>_L<z>_<PP>_<p> 9 - - - - - 5 - - - 14 pairs
IO_B<n>_<PP> - 7 - 18 - 16 - 7 - 26 74 pins
IO_B<n>_S_<PP> - 3 - 2 - 2 - 8 - - 15 pins
IO_B<n>_S_VREF_<PP> - 1 - 1 - 1 - 2 - - 5 pins
IO_B<n>_<f>_<PP> - 4 - 3 - 5 - 4 - 4 20 pins
IO_B<n>_RX_L<z>_<PP>_<p> - - 4 - 4 - - - - - 8 pairs
Total 10 15 5 24 5 24 5 23 0 32
Table 6: I/O Types Availability per I/O Banks
2.9.2 Dual-Purpose Pins
Table 7 lists pins that have special functions during the FPGA configuration or when they are activated in
the bitstream. These pins can be configured in Quartus software. Please refer to Intel Cyclone IV Device
Handbook [17] and to the Cyclone IV Device Family Pin Connection Guidelines [20] for details on these pins.
Dedicated Function Signal Name Description
CRC_ERROR IO_B6_L21 Active-high signal that indicates that the error-detection cir-
cuit has detected errors in the configuration SRAM bits. This
pin is optional and is used when the CRC error-detection cir-
cuit is enabled. This pin can be configured to support open-
drain output.
DEV_CLR# IO_B5_L3_N21_P Optional pin that allows you to override all clears on all de-
vice registers (device-wide reset). When this pin is driven
low, all registers are cleared; when this pin is driven high, all
registers behave as programmed.
Continued on next page...
1D = differential, SE = single-ended
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Dedicated Function Signal Name Description
DEV_OE IO_B5_L3_N22_N Optional pin that allows you to override all tri-states on the
device (device-wide output enable). When this pin is driven
low, all I/O pins are tri-stated; when this pin is driven high,
all I/O pins behave as defined in the design.
INIT_DONE IO_B6_L22 This is a dual-purpose pin and can be used as an I/O pin
when not enabled as INIT_DONE. When enabled, a transition
from low to high at the pin indicates when the device has
entered user mode. If the INIT_DONE output is enabled,
the INIT_DONE pin cannot be used as a user I/O pin after
configuration.
Table 7: Dual-Purpose Pins
2.9.3 Differential I/Os
When using differential pairs, a differential impedance of 100 Ωmust be matched on the base board, and
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the FPGA device to the module connector is
available in Mercury CA1 FPGA Module IO Net Length Excel Sheet [3]. This enables the user to match the
total length of the differential pairs on the base board if required by the application.
2.9.4 I/O Banks
Table 8 describes the main attributes of the FPGA I/O banks, and indicates which peripherals are connected
to each I/O bank. All I/O pins within a particular I/O bank must use the same I/O (VCC_IO) and reference
(VREF) voltages.
Bank Connectivity VCC_IO VREF
Bank 1 Gigabit Ethernet PHY, FTDI USB 2.0 controller, 3.3 V Not supported
SPI flash, on-board I2C bus, FPGA configuration
Bank 2 Module connector
User selectable IO_B2_S_VREF_M5
VCC_IO_B2 IO_B2_VREF_T3
IO_B2_VREF_R5
Bank 3 Module connector
IO_B3_VREF_Y4
User selectable IO_B3_VREF_AB4
VCC_IO_B3 IO_B3_VREF_V9
IO_B3_S_VREF_U11
Continued on next page...
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Bank Connectivity VCC_IO VREF
Bank 4 Module connector
User selectable IO_B4_S_VREF_V12
VCC_IO_B4 IO_B4_VREF_W14
IO_B4_VREF_V16
Bank 5 Module connector
IO_B5_VREF_W19
User selectable IO_B5_VREF_R17
VCC_IO_B5 IO_B5_S_VREF_P20
IO_B5_S_VREF_N19
Bank 6 Module connector, LEDs
IO_B6_VREF_K19
User selectable IO_B6_VREF_J18
VCC_IO_B6 IO_B6_VREF_H18
IO_B6_VREF_D20
Bank 7 DDR2 SDRAM 1.8 V 0.9 V
Bank 8 DDR2 SDRAM, Gigabit Ethernet PHY 1.8 V 0.9 V
Table 8: I/O Banks
2.9.5 VREF Usage
I/O standards referenced using VREF can be used on the Mercury module connector. The reference voltage
has to be applied to all VREF pins of the respective I/O banks. If a bank is configured to use an I/O standard
that does not need a reference voltage, the VREF pins of this bank on the Mercury module connector are
available as user I/O pins.
The VREF pins are listed in the Mercury Master Pinout Excel Sheet [11].
Warning!
Use only VREF voltages compliant with the equipped FPGA device; any other voltages may damage
the equipped FPGA device, as well as other devices on the Mercury CA1 FPGA module.
Do not leave a VREF pin floating when the used I/O standard requires a reference voltage, as this may
damage the equipped FPGA device, as well as other devices on the Mercury CA1 FPGA module.
2.9.6 VCC_IO Usage
The VCC_IO voltages for the I/O banks located on the module connector are configurable by applying the
required voltage to the VCC_IO_B[x] pins. All VCC_IO_B[x] pins of the same bank must be connected to the
same voltage.
For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per
module connector.
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Signal Name FPGA Pins Supported Voltages Connector A Pins Connector B Pins
VCC_IO_B2 VCCIO2 1.2 V - 3.3 V ±5% - 140, 143
VCC_IO_B3 VCCIO3 1.2 V - 3.3 V ±5% - 88, 95
VCC_IO_B4 VCCIO4 1.2 V - 3.3 V ±5% - 64, 67
VCC_IO_B5 VCCIO5 1.2 V - 3.3 V ±5% 38, 41 -
VCC_IO_B62VCCIO6 1.2 V - 3.3 V ±5% 74, 77 -
Table 9: VCC_IO Pins
Warning!
Use only VCC_IO voltages compliant with the equipped FPGA device; any other voltages may damage
the equipped FPGA device, as well as other devices on the Mercury CA1 FPGA module.
Do not leave a VCC_IO pin floating, as this may damage the equipped FPGA device, as well as other
devices on the Mercury CA1 FPGA module.
Warning!
Do not power the VCC_IO pins when PWR_GOOD and PWR_EN signals are not active. If the module
is not powered, you need to make sure that the VCC_IO voltages are disabled (for example, by using a
switch on the base board, which uses PWR_GOOD as enable signal). Figure 10 illustrates the VCC_IO
power requirements.
Figure 10: Power-Up Sequence - VCC_IO in Relation with PWR_GOOD and PWR_EN Signals
2VCC_IO_B6 is connected to configuration voltage pins (VIN_CFG) for compatibility with other Enclustra modules. The FPGA
configuration signals are at 3.3 V level on the module connector.
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