Enclustra Mars XU3 User manual

Mars XU3 SoC Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mars XU3 SoC module to the user, and to
provide the user with a comprehensive guide to understanding and using the Mars XU3 SoC module.
Summary
This document first gives an overview of the Mars XU3 SoC module followed by a detailed description of its
features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product MA-XU3 Mars XU3 SoC Module
Document Information Reference Version Date
Reference / Version / Date D-0000-432-001 04 25.07.2019
Approval Information Name Position Date
Written by DIUN Design Engineer 16.02.2017
Verified by GLAC Design Expert 24.02.2017
Approved by DIUN Manager, BU SP 25.07.2019
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2019 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior
written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the date
of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
04 25.07.2019 DIUN Added information on RGMII skews, power supplies, voltage moni-
toring, heat sink, Linux how-to guide, corrected supported voltage
range for VCC_BAT, corrected minimum MDIO clock frequency, other
style updates
03 21.08.2018 DIUN Minor corrections and style updates
02 20.04.2018 DIUN Updated for revision 2
01 26.04.2017 DIUN Version 01, preliminary
D-0000-432-001 2 / 52 Version 04, 25.07.2019

Table of Contents
1 Overview 6
1.1 General ................................................... 6
1.1.1 Introduction ................................................ 6
1.1.2 Warranty .................................................. 6
1.1.3 RoHS .................................................... 6
1.1.4 DisposalandWEEE ............................................ 6
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.6 ElectrostaticDischarge .......................................... 7
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features................................................... 7
1.3 Deliverables ................................................ 7
1.4 Accessories................................................. 8
1.4.1 ReferenceDesign ............................................. 8
1.4.2 EnclustraBuildEnvironment ....................................... 8
1.4.3 MarsPM3BaseBoard........................................... 8
1.4.4 MarsEB1BaseBoard ........................................... 8
1.4.5 MarsST3BaseBoard ........................................... 9
1.5 XilinxToolSupport ............................................ 9
2 Module Description 10
2.1 BlockDiagram............................................... 10
2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 TopandBottomViews .......................................... 13
2.4.1 TopView .................................................. 13
2.4.2 BottomView................................................ 13
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1 TopAssemblyDrawing .......................................... 14
2.5.2 BottomAssemblyDrawing........................................ 14
2.6 ModuleFootprint ............................................. 15
2.7 MechanicalData.............................................. 15
2.8 ModuleConnector ............................................ 15
2.9 UserI/O................................................... 16
2.9.1 Pinout.................................................... 16
2.9.2 I/OPinExceptions............................................. 17
2.9.3 DifferentialI/Os .............................................. 17
2.9.4 I/OBanks.................................................. 17
2.9.5 VCC_IOUsage ............................................... 18
2.9.6 SignalTerminations ............................................ 19
2.9.7 MultiplexedI/O(MIO)Pins........................................ 19
2.9.8 AnalogInputs ............................................... 20
2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11 Power.................................................... 22
2.11.1 PowerGenerationOverview ....................................... 22
2.11.2 PowerEnable/PowerGood........................................ 23
2.11.3 VoltageSupplyInputs........................................... 23
2.11.4 VoltageSupplyOutputs ......................................... 24
2.11.5 PowerConsumption............................................ 24
2.11.6 HeatDissipation.............................................. 24
2.11.7 VoltageMonitoring ............................................ 25
2.12 ClockGeneration ............................................. 25
2.13 Reset .................................................... 26
2.14 LEDs..................................................... 27
2.15 DDR4SDRAM ............................................... 27
D-0000-432-001 3 / 52 Version 04, 25.07.2019

2.15.1 DDR4SDRAMType ............................................ 27
2.15.2 SignalDescription............................................. 28
2.15.3 Termination................................................. 28
2.15.4 Parameters................................................. 28
2.16 QSPIFlash ................................................. 29
2.16.1 QSPIFlashType .............................................. 29
2.16.2 SignalDescription............................................. 30
2.16.3 Configuration ............................................... 30
2.16.4 QSPIFlashCorruptionRisk........................................ 30
2.17 eMMCFlash ................................................ 31
2.17.1 eMMCFlashType ............................................. 31
2.17.2 SignalDescription............................................. 31
2.18 SDCard................................................... 31
2.19 GigabitEthernet.............................................. 31
2.19.1 EthernetPHYType............................................. 31
2.19.2 SignalDescription............................................. 32
2.19.3 ExternalConnectivity ........................................... 32
2.19.4 MDIOAddress............................................... 32
2.19.5 PHYConfiguration............................................. 32
2.19.6 RGMIIDelaysConfiguration ....................................... 32
2.20 USB2.0 ................................................... 33
2.20.1 USBPHYType ............................................... 33
2.20.2 SignalDescription............................................. 33
2.21 USB3.0 ................................................... 33
2.22 DisplayPort ................................................ 34
2.23 Real-TimeClock(RTC)........................................... 34
2.24 SecureEEPROM .............................................. 35
2.24.1 EEPROMType ............................................... 35
3 Device Configuration 36
3.1 ConfigurationSignals........................................... 36
3.2 Pull-UpDuringConfiguration ...................................... 37
3.3 Power-onResetDelayOverride ..................................... 38
3.4 BootMode................................................. 39
3.5 JTAG..................................................... 39
3.5.1 JTAGonModuleConnector ....................................... 40
3.5.2 ExternalConnectivity ........................................... 40
3.6 eMMCBootMode............................................. 40
3.7 QSPIBootMode.............................................. 40
3.8 SDCardBootMode............................................ 40
3.9 eMMCFlashProgramming........................................ 41
3.10 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.11 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . 41
3.12 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 I2C Communication 43
4.1 Overview .................................................. 43
4.2 SignalDescription............................................. 43
4.3 I2CAddressMap ............................................. 43
4.4 SecureEEPROM .............................................. 44
4.4.1 MemoryMap ............................................... 44
5 Operating Conditions 47
5.1 AbsoluteMaximumRatings ....................................... 47
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6 Ordering and Support 49
D-0000-432-001 4 / 52 Version 04, 25.07.2019

6.1 Ordering .................................................. 49
6.2 Support................................................... 49
D-0000-432-001 5 / 52 Version 04, 25.07.2019

1 Overview
1.1 General
1.1.1 Introduction
The Mars XU3 SoC module combines the Xilinx Zynq® UltraScale+ MPSoC (Multiprocessor System-on-Chip)
device with USB 3.0, PCIe® Gen2 ×4, USB 2.0 On-The-Go PHY, Gigabit Ethernet, DDR4 SDRAM, eMMC flash,
high-speed LVDS I/O, and is available in industrial temperature range, forming a complete and powerful em-
bedded processing system.
The use of the Mars XU3 SoC module, in contrast to building a custom MPSoC hardware, significantly re-
duces development effort and redesign risk and improves time-to-market for the embedded system.
Together with Mars base boards, the Mars XU3 SoC module allows the user to quickly build a system pro-
totype and start with application development.
The Enclustra Build Environment [15] is available for the Mars XU3 SoC module. This build system allows
the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the
desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader).
It downloads and compiles all required software, such as U-Boot, Linux, and BusyBox based root file system.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
1.1.3 RoHS
The Mars XU3 SoC module is designed and produced according to the Restriction of Hazardous Substances
(RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mars XU3 SoC module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mars
XU3 SoC module.
1.1.5 Safety Recommendations and Warnings
Mars modules are not designed to be “ready for operation” for the end-user. These can only be used in
combination with suitable base boards. Proper configuration of the hardware before usage is required.
Ensure that the power supply is disconnected from the board before inserting or removing the Mars XU3
SoC module, connecting interfaces, replacing batteries, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-
voltage on power or signal lines can also cause permanent damage to the module.
Warning!
Use the Mars XU3 SoC module only with base boards designed for the Enclustra Mars module family.
Inserting the Mars XU3 SoC module into a SO-DIMM connector designed for memory (e.g. a computer
main board) may damage the module and the carrier board.
D-0000-432-001 6 / 52 Version 04, 25.07.2019

1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mars XU3 SoC module is a Class A product and is not intended for use in domestic environments. The
product may cause electromagnetic interference, for which appropriate measures must be taken.
1.2 Features
•Xilinx Zynq® UltraScale+™ MPSoC
•XCZU2CG/XCZU2EG/XCZU3EG device
•SBVA484 package
•Quad-core/dual-core ARM® Cortex™-A53 MPCore™ up to 1.33 GHz
•Dual-core ARM® Cortex™-R5 MPCore™ up to 533 MHz
•Mali-400 MP2 GPU (not for CG variants)
•Xilinx 16nm FinFET+ FPGA fabric
•108 user I/Os
•12 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)
•76 FPGA I/Os (single-ended, differential or analog)
•52 HP I/Os (up to 1.8 V)
•24 HD I/Os (up to 3.3 V)
•20 GTR MGT signals (clock and data)
•4 GTR MGTs @ 5 Gbit/sec and 2 reference input clock differential pairs
•PCIe Gen2 ×4 (Xilinx built-in PCIe hard block using GTR lines)
•Up to 2 GB DDR4 SDRAM
•64 MB quad SPI flash
•16 GB eMMC flash
•Gigabit Ethernet
•USB 2.0 On-The-Go (OTG)
•USB 3.0 (Xilinx built-in USB 3.0 hard block using GTR lines)
•Real-time clock
•SO-DIMM form factor (30 ×67.6 mm, 200 pins)
1.3 Deliverables
•Mars XU3 SoC module
•Mars XU3 SoC module documentation, available via download:
•Mars XU3 SoC Module User Manual (this document)
•Mars XU3 SoC Module Reference Design [2]
•Mars XU3 SoC Module IO Net Length Excel Sheet [3]
•Mars XU3 SoC Module FPGA Pinout Excel Sheet [4]
•Mars XU3 SoC Module User Schematics (PDF) [5]
•Mars XU3 SoC Module Known Issues and Changes [6]
•Mars XU3 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [7]
•Mars XU3 SoC Module 3D Model (PDF) [8]
•Mars XU3 SoC Module STEP 3D Model [9]
•Module Pin Connection Guidelines [10]
•Mars Master Pinout [11]
•Enclustra Modules Heat Sink Application Note [18]
•Enclustra Build Environment [15] (Linux build environment; refer to Section 1.4.2 for details)
•Enclustra Build Environment How-To Guide [16]
D-0000-432-001 7 / 52 Version 04, 25.07.2019

1.4 Accessories
1.4.1 Reference Design
The Mars XU3 SoC module reference design features an example configuration for the Zynq Ultrascale+
MPSoC device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from the Enclustra download page [2].
1.4.2 Enclustra Build Environment
The Enclustra Build Environment (EBE) [15] enables the user to quickly set up and run Linux on any Enclustra
SoC module or system board. It allows the user to choose the desired target, and download all the required
binaries, such as bitstream and FSBL. It downloads and compiles all required software, such as U-Boot, Linux,
and BusyBox based root file system.
The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface (CLI)
that facilitates the automatic build flow.
The Enclustra Build Environment How-To Guide [16] describes in more detail how to use the EBE to customize
the provided software for the user application. The document provides information on the configuration
options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications, customization
of device trees and integration of existing or new kernel drivers.
1.4.3 Mars PM3 Base Board
The current Mars PM3 base board revision does not support the Mars XU3 SoC module. Please contact
Enclustra for further information.
1.4.4 Mars EB1 Base Board
•Mars 200-pin SO-DIMM socket
•2×Mini Camera Link connectors (requires FPGA support)
•HDMI 1.3 connector (requires FPGA support)
•40-pin GPIO connector (Anios)
•3×12-pin GPIO connector (two of the connectors with Pmod™ compatible pinout)
•RJ45 Ethernet connector
•USB 2.0 A host connector
•Micro USB 2.0 device connector (shared)
•FTDI USB 2.0 device controller with micro USB device connector
•microSD card holder
•Various switches and LEDs
•Integrated Xilinx compatible JTAG adapter
•Single 12 V DC supply voltage or USB bus-powered (with restrictions)
•Form factor: 120 ×80 mm
Please note that the available features depend on the equipped Mars module type.
D-0000-432-001 8 / 52 Version 04, 25.07.2019

1.4.5 Mars ST3 Base Board
•Mars 200-pin SO-DIMM socket
•MIPI D-PHY connector (requires FPGA support)
•Mini DisplayPort connector (requires FPGA support)
•HDMI connector (requires FPGA support)
•USB 3.0 host connector
•RJ45 Ethernet connector
•2×40-pin GPIO connector (Anios)
•1×8-pin and 1 ×4-pin GPIO connectors (Pmod™ compatible pinout)
•FTDI USB 2.0 device controller with micro USB device connector
•microSD card holder
•User LEDs
•Integrated Xilinx compatible JTAG adapter
•Support for low I/O voltages (1.2 V, 1.8 V)
•Single 12 V DC supply voltage
•Form factor: 100 ×80 mm
Please note that the available features depend on the equipped Mars module type.
1.5 Xilinx Tool Support
The MPSoC devices equipped on the Mars XU3 SoC module are supported by the Vivado HL WebPACK
Edition software, which is available free of charge. Please contact Xilinx for further information.
D-0000-432-001 9 / 52 Version 04, 25.07.2019

2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mars XU3 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most of
its I/O pins are connected to the Mars module connector, making 88 regular user I/Os available to the user.
Further, four MGT GTR pairs are available on the module connector, making possible the implementation of
several high-speed protocols such as PCIe Gen2 ×4 and USB 3.0 (simultaneous usage of all the interfaces
is limited to the available hardware resources i.e. number of transceivers and lane mapping).
The MPSoC device can boot from the on-board QSPI flash, from the eMMC flash or from an external SD
card. For development purposes, a JTAG interface is connected to Mars module connector.
The available standard configurations include a 16 GB eMMC flash, a 64 MB quad SPI flash and 1 GB or 2 GB
DDR4 SDRAM.
Further, the module is equipped with a Gigabit Ethernet PHY and a USB 2.0 OTG PHY, making it ideal for
communication applications.
A real-time clock is available on the Xilinx Zynq Ultrascale+ MPSoC device.
On-board clock generation is based on a 33.33 MHz crystal oscillator. In addition, two oscillators delivering
100 MHz and 27 MHz reference clocks for the MGT GTR lines, are equipped on the module.
The module can be operated using a 3.3 V DC input, from which all necessary supply voltages are generated.
Some of these voltages are available on the Mars module connector to supply circuits on the base board,
or can be used as voltage inputs for the FPGA banks.
Four LEDs are connected to the MPSoC pins for status signaling.
D-0000-432-001 10 / 52 Version 04, 25.07.2019

2.2 Module Configuration and Product Codes
Table 1 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
Product Code MPSoC DDR4 SDRAM Temperature Range
MA-XU3-2CG-1E-D10 XCZU2CG-1SBVA484E 1 GB 0 to +85◦C
MA-XU3-2EG-1I-D10 XCZU2EG-1SBVA484I 1 GB -40 to +85◦C
MA-XU3-3EG-2I-D11 XCZU3EG-2SBVA484I 2 GB -40 to +85◦C
Table 1: Standard Module Configurations
The product code indicates the module type and main features. Figure 2 describes the fields within the
product code.
Figure 2: Product Code Fields
Please note that for the first revision modules or early access modules, the product code may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 Article Numbers and Article Codes
Every module is uniquely labeled, showing the article number and serial number. An example is presented
in Figure 3.
D-0000-432-001 11 / 52 Version 04, 25.07.2019

Figure 3: Module Label
The correspondence between article number and article code is shown in Table 2. The article code repre-
sents the product code, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mars XU3 SoC Module Known Issues
and Changes document [6].
Article Number Article Code
EN101824 MA-XU3-3EG-1EES-D10-R1
EN101801 MA-XU3-2CG-1E-D10-R1
EN101814 MA-XU3-3EG-2I-D11-R1
EN101981 MA-XU3-2CG-1E-D10-R2
EN101982 MA-XU3-2EG-1I-D10-R2
EN101983 MA-XU3-3EG-2I-D11-R2
Table 2: Article Numbers and Article Codes
D-0000-432-001 12 / 52 Version 04, 25.07.2019

2.4 Top and Bottom Views
2.4.1 Top View
Figure 4: Module Top View
2.4.2 Bottom View
Figure 5: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
D-0000-432-001 13 / 52 Version 04, 25.07.2019

2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 6: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 7: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
D-0000-432-001 14 / 52 Version 04, 25.07.2019

2.6 Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board.
The maximum component height under the module is dependent on the connector type - refer to Section
2.8 for detailed connector information.
Figure 8: Module Footprint - Top View
The footprint of the module connector is available for different PCB design tools (Altium, Eagle, Orcad, PADS)
[7].
2.7 Mechanical Data
Table 3 describes the mechanical characteristics of the Mars XU3 SoC module. A 3D model (PDF) and a STEP
3D model are available [8], [9].
Symbol Value
Size 67.6 ×30 mm
Component height top 2.61 mm
Component height bottom 1.2 mm
Weight 9 g
Table 3: Mechanical Data
2.8 Module Connector
The Mars XU3 SoC module fits into a 200-pin DDR2 SO-DIMM (1.8 V) socket. Up to four M2 screws may be
used to mechanically fasten the module to the base board. Do not use excessive force to tighten the screws,
as this could damage the module.
The pinout of the module connector is found in the Mars Master Pinout Excel Sheet [11]. The connector to
be mounted on the base board is available in different heights. Some examples are presented in Table 4.
Please refer to the connector datasheet for more information.
D-0000-432-001 15 / 52 Version 04, 25.07.2019

Height Type Description Max component height under the module
4.0 mm TE 292406-4 DDR2-SODIMM, 1.8 V 0 mm
5.2 mm TE 1565917-4 DDR2-SODIMM, 1.8 V 1 mm
6.5 mm TE 5-1746530-4 DDR2-SODIMM, 1.8 V 2 mm
8.0 mm TE 1827341-4 DDR2-SODIMM, 1.8 V 4 mm
Table 4: Module Connector Types
2.9 User I/O
2.9.1 Pinout
Information on the Mars XU3 SoC module pinout can be found in the Enclustra Mars Master Pinout [11], and
in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mars XU3 SoC module it may be possible that the
connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B65_L6_AD6_P5_P is located on pin P5 of I/O bank 65, pair 6, it is a System Monitor differ-
ential auxiliary analog input capable pin and it has positive polarity, when used in a differential pair.
The global clock capable pins are marked with “GC” (HP I/O banks) or with “HDGC” (HD I/O banks) in the
signal name. For details on their function and usage, please refer to the Xilinx documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name Signals Pairs Differential Single-ended I/O Bank
IO_B65_<...> 48 24 In/Out In/Out 65 (HP)1
IO_B66_<...> 4 2 In/Out In/Out 66 (HP)1
IO_B26_<...> 24 12 In/Out (no LVDS/LVPECL outputs sup-
ported; internal differential termina-
tion not supported)
In/Out 26 (HD)1
Refer to Section 2.9.3 for details.
Total 76 38 - - -
Table 5: User I/Os
The multi-gigabit transceiver (MGT) are described in section 2.10.
1HD = high density pins, HP = high performance pins; Refer to the Zynq UltraScale+ MPSoC Overview [23] for details.
D-0000-432-001 16 / 52 Version 04, 25.07.2019

2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination
with certain Mars boards they may have a specific role).
PCIe Reset Signal (PERST#)
Table 6 lists the I/O pin exceptions on the Mars XU3 SoC module related to the PCIe reset connection.
I/O Name Module Connector Pin Description
PS_MIO42_PERST# 148 Connected via a 1 kΩresistor to MIO pin 30 for PCIe
PERST# connection implementation
Table 6: I/O Pin Exceptions - PERST
The PERST# connection to module connector pin 148 is implemented for future support of PCIe interface
on Enclustra Mars base boards.
2.9.3 Differential I/Os
When using differential pairs, a differential impedance of 100 Ωmust be matched on the base board, and
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the MPSoC device to the module connector is
available in Mars XU3 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total
length of the differential pairs on the base board if required by the application.
The I/Os in the HD bank (26) can be used only as differential inputs when LVDS/LVPECL standards are used;
LVDS/LVPECL outputs are not supported.
Internal differential termination is not supported for the HD pins; differential input pairs on the module
connector may be terminated by external termination resistors on the base board (close to the module
pins).
2.9.4 I/O Banks
Table 7 describes the main attributes of the FPGA and PS I/O banks, and indicates which peripherals are
connected to each I/O bank. All I/O pins within a particular I/O bank must use the same I/O (VCC_IO) and
reference (VREF) voltages.
2
Bank Connectivity VCC_IO VREF
Bank 65 Module connector, I2C2, LEDs User selectable GND
VCC_IO_B65
Bank 66 Module connector, Ethernet PHY User selectable GND
VCC_IO_B65
Continued on next page...
2I2C on PL side is available starting with revision 2 modules.
D-0000-432-001 17 / 52 Version 04, 25.07.2019

Bank Connectivity VCC_IO VREF
Bank 26 Module connector User selectable -
VCC_IO_B26
Bank 503 FPGA PS Configuration User selectable -
VCC_CFG_MIO
PS DDR Bank 504 DDR4 SDRAM 1.2 V -
PS Bank 500 eMMC and QSPI flash devices, I2C, LEDs, GTR oscillators 1.8 V -
PS Bank 501 Module connector, power circuitry User selectable -
VCC_CFG_MIO
PS Bank 502 Gigabit Ethernet PHY and USB PHYs 1.8 V -
PS GTR Bank 505 Module connector, GTR oscillators VCC_PSINT -
Table 7: I/O Banks
2.9.5 VCC_IO Usage
The VCC_IO voltages for the I/O banks located on the module connector are configurable by applying the
required voltage to the VCC_IO_B[x], respectively VCC_CFG_[x] pins. All VCC_IO_B[x] or VCC_CFG_[x] pins of
the same bank must be connected to the same voltage.
For compatibility with other Enclustra Mars base boards and modules, it is recommended to use a single
I/O voltage.
Signal Name MPSoC Pins Supported Voltages Connector Pins
VCC_CFG_MIO VCCO_PSIO1_501, VCCO_PSIO3_503 1.8 V - 3.3 V ±5% 137, 146
VCC_IO_B26 VCCO_26 1.2 V - 3.3 V ±5%353, 62, 73
VCC_IO_B65 VCCO_65 1.0 V - 1.8 V4±5% 82, 117, 126
Table 8: VCC_IO Pins
3 4
Warning!
Use only VCC_IO voltages compliant with the equipped MPSoC device; any other voltages may dam-
age the equipped MPSoC device, as well as other devices on the Mars XU3 SoC module.
Do not leave a VCC_IO pin floating, as this may damage the equipped MPSoC device, as well as other
devices on the Mars XU3 SoC module.
3For voltages of 3.3 V for VCC_IO_B26, the tolerance range is -5% to +3%.
4When using voltages lower than 1.8 V for VCC_IO_B65, the I2C bus on FPGA bank 65 is not operational (I2C on PL side is available
starting with revision 2).
D-0000-432-001 18 / 52 Version 04, 25.07.2019

Warning!
Do not power the VCC_IO pins when PWR_GOOD and PWR_EN signals are not active. If the module
is not powered, you need to make sure that the VCC_IO voltages are disabled (for example, by using
a switch on the base board, which uses PWR_GOOD as enable signal). Figure 9 illustrates the VCC_IO
power requirements.
Figure 9: Power-Up Sequence - VCC_IO in Relation with PWR_GOOD and PWR_EN Signals
2.9.6 Signal Terminations
Differential Inputs
Internal differential termination is not supported for the HD pins (bank 26). Differential input pairs on the
module connector may be terminated by external termination resistors on the base board (close to the
module pins).
Single-Ended Outputs
There are no series termination resistors on the Mars XU3 SoC module for single-ended outputs. If required,
series termination resistors may be equipped on the base board (close to the module pins).
2.9.7 Multiplexed I/O (MIO) Pins
Details on the MIO/EMIO terminology are available in the Zynq UltraScale+ MPSoC Technical Reference
Manual [19].
Some of the MIO pins on the Mars XU3 SoC module are connected to on-board peripherals, while others
are available as GPIOs; the suggested functions below are for reference only - always verify your MIO pinout
with the Xilinx device handbook.
Table 9 gives an overview over the MIO pin connections on the Mars XU3 SoC module. Only the pins marked
with “user functionality” are available on the module connector.
D-0000-432-001 19 / 52 Version 04, 25.07.2019

MIO Group Function Connection
0-5 QSPI flash QSPI flash
6 QSPI feedback clock -
7-9 LEDs 0-2 On-board LEDs
10-11 I2C On-board I2C bus and module connec-
tor via level shifter
12 I2C interrupt On-board I2C bus
13-22 eMMC flash eMMC flash
23 LED3 On-board LEDs
24 Enable signal for the 100 MHz oscillator On-board GTR 100 MHz oscillator
25 Enable signal for the 27 MHz oscillator On-board GTR 27 MHz oscillator
26-29, 32-37, 40-41 Unused -
30 PCIe block PERST# signal/user func-
tionality
Module connector and MIO42 via series
resistor
31 Enable low power mode (PWR_LP_EN#
signal)
Power generation circuitry; refer to Sec-
tion 2.11.1 for details
38 UART RX5/user functionality Module connector
39 UART TX5/user functionality
42 PCIe block PERST# signal/user func-
tionality
Module connector
43-44 User functionality Module connector
45-51 SD card/user functionality Module connector
52-63 USB USB 2.0 PHY
64-75 Ethernet Gigabit Ethernet PHY
76-77 Ethernet MDIO Gigabit Ethernet PHY
Table 9: MIO Pins Connections Overview
2.9.8 Analog Inputs
The Zynq Ultrascale+ MPSoC devices contain a system monitor in the PL and an additional system monitor
block in the PS. These are used to sample analog inputs and to collect information on the internal voltages
and temperatures.
The system monitor block in the PL provides a 10-bit ADC, which supports up to 17 external analog lines (1
dedicated differential input, 16 auxiliary differential inputs). The auxiliary analog lines of the MPSoC device
5UART RX is an MPSoC input; UART TX is an MPSoC output.
D-0000-432-001 20 / 52 Version 04, 25.07.2019