Enclustra Mercury XU5 User manual

Mercury XU5 SoC Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mercury XU5 SoC module to the user, and
to provide the user with a comprehensive guide to understanding and using the Mercury XU5 SoC module.
Summary
This document first gives an overview of the Mercury XU5 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product ME-XU5 Mercury XU5 SoC Module
Document Information Reference Version Date
Reference / Version / Date D-0000-445-001 07 25.07.2019
Approval Information Name Position Date
Written by DIUN Design Engineer 08.06.2018
Verified by GKOE, GLAC Design Expert 22.06.2018
Approved by DIUN Manager, BU SP 25.07.2019
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2019 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior
written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the date
of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
07 25.07.2019 DIUN Added information on new variants, on power supplies, corrected
supported voltage range for VCC_BAT, corrected minimum MDIO
clock frequency, other style updates
06 17.05.2019 DIUN Added information on new variants, updated EEPROM map accord-
ingly, added information on RGMII delays, added information on
Linux how-to guide
05 18.01.2019 DIUN Minor correction in the block diagrams
04 16.01.2019 DIUN Added information on voltage monitoring and heat sink, updated
information on assembly variants
03 12.09.2018 DIUN Updated EEPROM map, other minor corrections
02 22.08.2018 DIUN Updates, corrections and additions based on revision 1 modules
01 26.06.2018 DIUN Version 01, preliminary
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Table of Contents
1 Overview 6
1.1 General ................................................... 6
1.1.1 Introduction ................................................ 6
1.1.2 Warranty .................................................. 6
1.1.3 RoHS .................................................... 6
1.1.4 DisposalandWEEE ............................................ 6
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.6 ElectrostaticDischarge .......................................... 7
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features................................................... 7
1.3 Deliverables ................................................ 8
1.4 Accessories................................................. 8
1.4.1 ReferenceDesign ............................................. 8
1.4.2 EnclustraBuildEnvironment ....................................... 8
1.4.3 Mercury+PE1BaseBoard ........................................ 9
1.5 XilinxToolSupport ............................................ 9
2 Module Description 10
2.1 BlockDiagram............................................... 10
2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 TopandBottomViews .......................................... 15
2.4.1 TopView .................................................. 15
2.4.2 BottomView................................................ 15
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.1 TopAssemblyDrawing .......................................... 16
2.5.2 BottomAssemblyDrawing........................................ 16
2.6 ModuleFootprint ............................................. 17
2.7 MechanicalData.............................................. 17
2.8 ModuleConnector ............................................ 18
2.9 UserI/O................................................... 19
2.9.1 Pinout.................................................... 19
2.9.2 I/OPinExceptions............................................. 20
2.9.3 DifferentialI/Os .............................................. 25
2.9.4 I/OBanks.................................................. 25
2.9.5 VCC_IOUsage ............................................... 26
2.9.6 SignalTerminations ............................................ 28
2.9.7 MultiplexedI/O(MIO)Pins........................................ 28
2.9.8 AnalogInputs ............................................... 29
2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.11 Power.................................................... 32
2.11.1 PowerGenerationOverview ....................................... 32
2.11.2 PowerEnable/PowerGood........................................ 33
2.11.3 VoltageSupplyInputs........................................... 33
2.11.4 VoltageSupplyOutputs ......................................... 34
2.11.5 PowerConsumption............................................ 34
2.11.6 HeatDissipation.............................................. 34
2.11.7 VoltageMonitoring ............................................ 35
2.12 ClockGeneration ............................................. 35
2.13 Reset .................................................... 36
2.14 LEDs..................................................... 36
2.15 DDR4SDRAM(PS)............................................. 37
2.15.1 DDR4SDRAMType ............................................ 38
2.15.2 SignalDescription............................................. 38
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2.15.3 Termination................................................. 38
2.15.4 Parameters................................................. 39
2.16 DDR4SDRAM(PL)............................................. 39
2.16.1 DDR4SDRAMType ............................................ 40
2.16.2 SignalDescription............................................. 40
2.16.3 Termination................................................. 40
2.16.4 Parameters................................................. 41
2.17 QSPIFlash ................................................. 41
2.17.1 QSPIFlashType .............................................. 41
2.17.2 SignalDescription............................................. 42
2.17.3 Configuration ............................................... 42
2.17.4 QSPIFlashCorruptionRisk........................................ 42
2.18 eMMCFlash ................................................ 42
2.18.1 eMMCFlashType ............................................. 42
2.18.2 SignalDescription............................................. 43
2.19 SDCard................................................... 43
2.20 GigabitEthernet(PS) ........................................... 43
2.20.1 EthernetPHYType............................................. 43
2.20.2 SignalDescription............................................. 43
2.20.3 ExternalConnectivity ........................................... 44
2.20.4 MDIOAddress............................................... 44
2.20.5 PHYConfiguration............................................. 44
2.20.6 RGMIIDelaysConfiguration ....................................... 44
2.21 GigabitEthernet(PL) ........................................... 45
2.21.1 EthernetPHYType............................................. 45
2.21.2 SignalDescription............................................. 45
2.21.3 ExternalConnectivity ........................................... 45
2.21.4 MDIOAddress............................................... 45
2.21.5 PHYConfiguration............................................. 45
2.21.6 RGMIIDelaysConfiguration ....................................... 46
2.22 USB2.0 ................................................... 46
2.22.1 USBPHYType ............................................... 46
2.22.2 SignalDescription............................................. 46
2.23 USB3.0 ................................................... 46
2.24 DisplayPort ................................................ 47
2.25 Real-TimeClock(RTC)........................................... 48
2.26 SecureEEPROM .............................................. 48
2.26.1 EEPROMType ............................................... 48
3 Device Configuration 49
3.1 ConfigurationSignals........................................... 49
3.2 Pull-UpDuringConfiguration ...................................... 50
3.3 Power-onResetDelayOverride ..................................... 51
3.4 BootMode................................................. 51
3.5 JTAG..................................................... 51
3.5.1 JTAGonModuleConnector ....................................... 52
3.5.2 ExternalConnectivity ........................................... 52
3.6 eMMCBootMode............................................. 52
3.7 QSPIBootMode.............................................. 52
3.8 SDCardBootMode............................................ 52
3.9 eMMCFlashProgramming........................................ 53
3.10 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.11 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . 53
3.12 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4 I2C Communication 55
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4.1 Overview .................................................. 55
4.2 SignalDescription............................................. 55
4.3 I2CAddressMap ............................................. 55
4.4 SecureEEPROM .............................................. 56
4.4.1 MemoryMap ............................................... 56
5 Operating Conditions 59
5.1 AbsoluteMaximumRatings ....................................... 59
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6 Ordering and Support 61
6.1 Ordering .................................................. 61
6.2 Support................................................... 61
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1 Overview
1.1 General
1.1.1 Introduction
The Mercury XU5 SoC module combines the Xilinx Zynq® UltraScale+ MPSoC (Multiprocessor System-on-
Chip) device with USB 3.0, PCIe® Gen3 ×4, PCIe® Gen2 ×4, two USB 2.0 PHYs, two Gigabit Ethernet PHYs,
DDR4 SDRAM with Error Correction Code (ECC), eMMC flash, multi-gigabit transceivers, high-speed LVDS
I/O, and is available in industrial temperature range, forming a complete and powerful embedded process-
ing system.
The use of the Mercury XU5 SoC module, in contrast to building a custom MPSoC hardware, significantly
reduces development effort and redesign risk and improves time-to-market for the embedded system.
Together with Mercury base boards, the Mercury XU5 SoC module allows the user to quickly build a system
prototype and start with application development.
The Enclustra Build Environment [15] is available for the Mercury XU5 SoC module. This build system allows
the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the
desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader).
It downloads and compiles all required software, such as U-Boot, Linux, and BusyBox based root file system.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
1.1.3 RoHS
The Mercury XU5 SoC module is designed and produced according to the Restriction of Hazardous Sub-
stances (RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mercury XU5 SoC module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mer-
cury XU5 SoC module.
1.1.5 Safety Recommendations and Warnings
Mercury modules are not designed to be “ready for operation” for the end-user. These can only be used in
combination with suitable base boards. Proper configuration of the hardware before usage is required.
Ensure that the power supply is disconnected from the board before inserting or removing the Mercury XU5
SoC module, connecting interfaces, replacing batteries, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-
voltage on power or signal lines can also cause permanent damage to the module.
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Warning!
It is possible to mount the Mercury XU5 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
XU5 SoC module.
The base board and module may be damaged if the module is mounted the wrong way round and
powered up.
1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mercury XU5 SoC module is a Class A product and is not intended for use in domestic environments.
The product may cause electromagnetic interference, for which appropriate measures must be taken.
1.2 Features
•Xilinx Zynq® UltraScale+™ MPSoC
•XCZU2CG/XCZU2EG/XCZU3EG/XCZU4CG/XCZU4EV/XCZU5EV device
•SFVC784 package
•Dual-/Quad-core ARM® Cortex™-A53 MPCore™ up to 1.500 GHz
•Dual-core ARM® Cortex™-R5 MPCore™ up to 600 MHz
•Mali-400 MP2 GPU (not for CG variants)
•H.264 / H.265 Video Codec (only for EV variants)
•Xilinx 16nm FinFET+ FPGA fabric
•ZU2CG/ZU2EG/ZU3EG: 178 user I/Os
•14 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)
•144 FPGA I/Os (single-ended, differential or analog)
•92 HP I/Os (up to 1.8 V)
•52 HD I/Os (up to 3.3 V)
•20 GTR MGT signals (clock and data)
•ZU4CG/ZU4EV/ZU5EV: 178 user I/Os
•14 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)
•124 FPGA I/Os (single-ended, differential or analog)
•72 HP I/Os (up to 1.8 V)
•52 HD I/Os (up to 3.3 V)
•40 MGT signals (clock and data)
•20 GTH MGT signals
•20 GTR MGT signals
•ZU4CG/ZU4EV/ZU5EV devices: 4 GTH MGTs @ 12.5 Gbit/sec and 2 reference input clock differential
pairs
•ZU4CG/ZU4EV/ZU5EV devices: PCIe Gen3 ×4 (Xilinx built-in PCIe integrated block using GTH lines)
•4 GTR MGTs @ 6 Gbit/sec and 2 reference input clock differential pairs
•PCIe Gen2 ×4 (Xilinx built-in PCIe hard block using GTR lines)
•Up to 8 GB DDR4 SDRAM with ECC on PS side
•Up to 2 GB DDR4 SDRAM on PL side
•64 MB quad SPI flash
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•16 GB eMMC flash
•2×Gigabit Ethernet PHYs
•2×USB 2.0 PHYs (host and host/device)
•USB 3.0 (Xilinx built-in USB 3.0 hard block using GTR lines)
•Real-time clock
•CAN, UART, SPI, I2C, SDIO/MMC
•Small form factor (56 ×54 mm)
•5 to 15 V supply voltage
1.3 Deliverables
•Mercury XU5 SoC module
•Mercury XU5 SoC module documentation, available via download:
•Mercury XU5 SoC Module User Manual (this document)
•Mercury XU5 SoC Module Reference Design [2]
•Mercury XU5 SoC Module IO Net Length Excel Sheet [3]
•Mercury XU5 SoC Module FPGA Pinout Excel Sheet [4]
•Mercury XU5 SoC Module FPGA Pinout Assembly Variants Excel Sheet [5]
•Mercury XU5 SoC Module User Schematics (PDF) [6]
•Mercury XU5 SoC Module Known Issues and Changes [7]
•Mercury XU5 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [8]
•Mercury XU5 SoC Module 3D Model (PDF) [9]
•Mercury XU5 SoC Module STEP 3D Model [10]
•Module Pin Connection Guidelines [11]
•Mercury Master Pinout [12]
•Enclustra Modules Heat Sink Application Note [18]
•Enclustra Build Environment [15] (Linux build environment; refer to Section 1.4.2 for details)
•Enclustra Build Environment How-To Guide [16]
1.4 Accessories
1.4.1 Reference Design
The Mercury XU5 SoC module reference design features an example configuration for the Zynq Ultrascale+
MPSoC device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from the Enclustra download page [2].
1.4.2 Enclustra Build Environment
The Enclustra Build Environment (EBE) [15] enables the user to quickly set up and run Linux on any Enclustra
SoC module or system board. It allows the user to choose the desired target, and download all the required
binaries, such as bitstream and FSBL. It downloads and compiles all required software, such as U-Boot, Linux,
and BusyBox based root file system.
The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface (CLI)
that facilitates the automatic build flow.
The Enclustra Build Environment How-To Guide [16] describes in more detail how to use the EBE to customize
the provided software for the user application. The document provides information on the configuration
options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications, customization
of device trees and integration of existing or new kernel drivers.
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1.4.3 Mercury+ PE1 Base Board
•168-pin Hirose FX10 module connectors (PE1-200: 2 connectors; PE1-300/400: 3 connectors)
•System controller
•Power control
•System monitor (PE1-300/400)
•Current sense (PE1-300/400)
•Low-jitter clock generator (PE1-300/400)
•Accelerometer/magnetometer/temperature sensor (PE1-300/400)
•microSD card holder
•User EEPROM
•eMMC managed NAND flash (PE1-300/400)
•PCIe ×4 interface
•USB 3.0 device connector
•USB 2.0 host connector (PE1-200: 1 connector; PE1-300/400: 4 connectors)
•Micro USB 2.0 device (UART, SPI, I2C, JTAG) connector
•2×RJ45 Gigabit Ethernet connectors
•mPCIe/mSATA card holder (USB only) (PE1-300/400)
•SIM card holder (optional, PE1-300/400 only)
•SMA clock and data in/out (optional, PE1-300/400 only)
•1×FMC LPC connector (PE1-200)
•1×FMC HPC connector (PE1-300)
•2×FMC LPC connector (PE1-400)
•2×40-pin Anios pin header
•3×12-pin Pmod™ pin header
•5 to 15 V DC supply voltage
•USB bus power (with restrictions)
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
1.5 Xilinx Tool Support
The MPSoC devices equipped on the Mercury XU5 SoC module are supported by the Vivado HL WebPACK
Edition software, which is available free of charge. Please contact Xilinx for further information.
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2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
Figure 2: Hardware Block Diagram - G1 Variants
The main component of the Mercury XU5 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most
of its I/O pins are connected to the Mercury module connector, making up to 158 regular user I/Os available
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to the user. Further, up to 8 MGT pairs are available on the module connector, making possible the imple-
mentation of several high-speed protocols such as PCIe Gen3/Gen2 ×4 and USB 3.0 (simultaneous usage of
all the interfaces is limited to the available hardware resources i.e. number of transceivers and lane mapping).
The “G1” module variants offer 158 regular I/Os and 4 GTH MGT lines on the module connector at the trade-
off of no GTR transceivers available. Section 2.9.2 describes in more detail the module assembly variants
and routing options around the Processing System (PS) and Programmable Logic (PL) transceivers and I/Os.
The MPSoC device can boot from the on-board QSPI flash, from the eMMC flash or from an external SD
card. For development purposes, a JTAG interface is connected to Mercury module connector.
The available standard configurations include a 16 GB eMMC flash, a 64 MB quad SPI flash, up to 8 GB DDR4
SDRAM with ECC connected to the Processing System (PS) and up to 2 GB DDR4 SDRAM connected to the
Programmable Logic (PL). The DDR configuration on the smallest module variant (ME-XU5-2CG-1E-D10H)
does not support ECC and has only half of the DDR4 bandwidth (32-bit interface instead of 64-bit).
The module is equipped with two Gigabit Ethernet PHYs and two USB 2.0 PHYs, making it ideal for commu-
nication applications.
A real-time clock is available on the Xilinx Zynq Ultrascale+ MPSoC device.
On-board clock generation is based on a 33.33 MHz crystal oscillator and a 100 MHz LVDS oscillator for the
PL. In addition, two oscillators delivering 100 MHz and 27 MHz reference clocks for the MGT GTR lines, are
equipped on the module.
The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of
these voltages are available on the Mercury module connectors to supply circuits on the base board.
Six LEDs are connected to the MPSoC pins for status signaling.
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2.2 Module Configuration and Product Codes
Table 1 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
Product Code MPSoC DDR4 (PS) DDR4 (PS) DDR4 (PL) Temperature
SDRAM ECC SDRAM Range
ME-XU5-2CG-1E-D10H1XCZU2CG-
1SFVC784E
1 GB 7512 MB 0 to +85◦C
ME-XU5-2EG-1I-D11E XCZU2EG-
1SFVC784I
2 GB 3512 MB -40 to +85◦C
ME-XU5-3EG-2I-D11E XCZU3EG-
2SFVC784I
2 GB 3512 MB -40 to +85◦C
ME-XU5-4CG-1E-D11E-G12XCZU4CG-
1SFVC784E
2 GB 3512 MB 0 to +85◦C
ME-XU5-4EV-1I-D11E XCZU4EV-
1SFVC784I
2 GB 3512 MB -40 to +85◦C
ME-XU5-4EV-1I-D11E-G12XCZU4EV-
1SFVC784I
2 GB 3512 MB -40 to +85◦C
ME-XU5-5EV-1E-D11E XCZU5EV-
1SFVC784E
2 GB 3512 MB 0 to +85◦C
ME-XU5-5EV-2I-D12E XCZU5EV-
2SFVC784I
4 GB 31 GB -40 to +85◦C
ME-XU5-5EV-2I-D12E-G12XCZU5EV-
2SFVC784I
4 GB 31 GB -40 to +85◦C
ME-XU5-5EV-3E-D13E XCZU5EV-
3SFVC784E
8 GB 32 GB 0 to +85◦C
Table 1: Standard Module Configurations
1 2
The product code indicates the module type and main features. Figure 3 describes the fields within the
product code.
1This variant supports only half of the DDR4 bandwidth on the PS side (32-bit interface instead of 64-bit). Refer to Section 2.15 for
details.
2G1 assembly variants offered for migration purposes or for cases where the end application does not require GTR transceivers,
but instead more regular I/Os. It can be used when porting an existing design from Mercury ZX1 or ZX5 to Mercury XU5 SoC module.
Please refer to Section 2.9.2 for details on assembly options and migration guidelines. This variant was referred to as “X1” variant in
previous user manual versions.
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Figure 3: Product Code Fields
Please note that for the first revision modules or early access modules, the product code may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 Article Numbers and Article Codes
Every module is uniquely labeled, showing the article number and serial number. An example is presented
in Figure 4.
Figure 4: Module Label
The correspondence between article number and article code is shown in Table 2. The article code repre-
sents the product code, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mercury XU5 SoC Module Known Issues
and Changes document [7].
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Article Number Article Code
EN101970 ME-XU5-2EG-1I-D11E-R1
EN102025 ME-XU5-3EG-2I-D11E-R1
EN102026 ME-XU5-4EV-1I-D11E-R1
EN102027 ME-XU5-5EV-2I-D12E-R1
EN102028 ME-XU5-5EV-3E-D13E-R1
EN102060 ME-XU5-5EV-2I-D12E-G1-R1
EN102596 ME-XU5-2CG-1E-D10H-R1.2
EN102224 ME-XU5-2EG-1I-D11E-R1.2
EN102225 ME-XU5-3EG-2I-D11E-R1.2
EN102598 ME-XU5-4CG-1E-D11E-G1-R1.2
EN102226 ME-XU5-4EV-1I-D11E-R1.2
EN102285 ME-XU5-4EV-1I-D11E-G1-R1.2
EN102599 ME-XU5-5EV-1E-D11E-R1.2
EN102227 ME-XU5-5EV-2I-D12E-R1.2
EN102229 ME-XU5-5EV-2I-D12E-G1-R1.2
EN102228 ME-XU5-5EV-3E-D13E-R1.2
Table 2: Article Numbers and Article Codes
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2.4 Top and Bottom Views
2.4.1 Top View
Figure 5: Module Top View
2.4.2 Bottom View
Figure 6: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 7: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 8: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.6 Module Footprint
Figure 9 shows the dimensions of the module footprint on the base board.
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 72 or 74
mm and having different topologies for the mounting holes. If different module types shall be fixed on the
base board by screws, additional mounting holes may be required to accommodate different modules. The
footprints of the module connectors for the base board design are available for different PCB design tools
(Altium, PADS, Eagle, Orcad) [8] and include the required information on the module sizes and holes.
The maximum component height under the module is dependent on the connector type - refer to Section
2.8 for detailed connector information.
Figure 9: Module Footprint - Top View
Warning!
It is possible to mount the Mercury XU5 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
XU5 SoC module.
2.7 Mechanical Data
Table 3 describes the mechanical characteristics of the Mercury XU5 SoC module. A 3D model (PDF) and a
STEP 3D model are available [9], [10].
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Symbol Value
Size 56 ×54 mm
Component height top 3.32 mm
Component height bottom 1.35 mm
Weight 26 g
Table 3: Mechanical Data
2.8 Module Connector
Two Hirose FX10 168-pin 0.5 mm pitch headers with a total of 336 pins have to be integrated on the base
board. Up to four M3 screws may be used to mechanically fasten the module to the base board. Do not
use excessive force to tighten the screws, as this could damage the module.
The pinout of the module connector is found in the Mercury Master Pinout Excel Sheet [12]. The connector
is available in different packaging options and different stacking heights. Some examples are presented in
Table 4. Please refer to the connector datasheet for more information.
Reference Type Description
Mercury module connector FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm pitch
Base board connector FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4 mm stacking
height
Base board connector FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5 mm stacking
height
Table 4: Module Connector Types
Figure 10 indicates the pin numbering for the Mercury module connectors from the top view of the base
board. The connector pins are numbered as follows:
•Connector A: from J800-1 to J800-168
•Connector B: from J801-1 to J801-168
Figure 10: Pin Numbering for the Module Connector
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Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9 User I/O
2.9.1 Pinout
Information on the Mercury XU5 SoC module pinout can be found in the Enclustra Mercury Master Pinout
[12], and in the additional document Enclustra Module Pin Connection Guidelines [11].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mercury XU5 SoC module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os located in HP banks is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B66_L4_AD7_G3_P is located on pin G3 of I/O bank 66, pair 4, it is a System Monitor differ-
ential auxiliary analog input capable pin and it has positive polarity, when used in a differential pair.
The HD banks are numbered differently depending on the MPSoC device equipped on the module:
•Bank E represents:
•I/O bank 25 for ZU2/ZU3 devices
•I/O bank 45 for ZU4/ZU5 devices
•Bank F represents:
•I/O bank 26 for ZU2/ZU3 devices
•I/O bank 46 for ZU4/ZU5 devices
•Bank N represents:
•I/O bank 24 for ZU2/ZU3 devices
•I/O bank 44 for ZU4/ZU5 devices
•Bank O represents:
•I/O bank 44 for ZU2/ZU3 devices
•I/O bank 43 for ZU4/ZU5 devices
The naming convention for the user I/Os located in HD banks is:
IO_B<BANK_LETTER>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>
For example, IO_BO_L6_HDGC_AD6_AD12_N is located on pin AD12 of I/O bank O, pair 6, it is a System
Monitor differential auxiliary analog input capable pin and also a clock capable pin and it has negative po-
larity, when used in a differential pair.
The global clock capable pins are marked with “GC” (HP I/O banks) or with “HDGC” (HD I/O banks) in the
signal name. For details on their function and usage, please refer to the Xilinx documentation.
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Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name Sign. Pairs Differential Single- I/O Bank
ended
IO_B65_<...> 44 22 In/Out In/Out 65 (HP)3
IO_B66_<...> 48 24 In/Out In/Out 66 (HP)3
IO_BE_<...> 4 2 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 25 (HD)3for ZU2/ZU3
45 (HD)3for ZU4/ZU5
Refer to Section 2.9.3 for details.
IO_BF_<...> 2 1 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 26 (HD)3for ZU2/ZU3
46 (HD)3for ZU4/ZU5
Refer to Section 2.9.3 for details.
IO_BN_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 24 (HD)3for ZU2/ZU3
44 (HD)3for ZU4/ZU5
Refer to Section 2.9.3 for details.
IO_BO_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 44 (HD)3for ZU2/ZU3
43 (HD)3for ZU4/ZU5
Refer to Section 2.9.3 for details.
Total 146 73 - - -
Table 5: User I/Os
Please note that not all I/Os listed in Table 5 are available on the module connector. Certain user I/Os on the
module connectors can be connected to various MPSoC I/Os, depending on the product variant. Section
2.9.2 lists and describes the connectivity for these pins for each assembly variant. The multi-use signals on
the module connector are not named according to the naming convention described above.
The multi-gigabit transceiver (MGT) are described in section 2.10.
2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination
with certain Mercury boards they may have a specific role).
3HD = high density pins, HP = high performance pins; Refer to the Zynq UltraScale+ MPSoC Overview [23] for details.
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