Enclustra Mercury ZX1 User manual

Mercury ZX1 SoC Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mercury ZX1 SoC module to the user, and
to provide the user with a comprehensive guide to understanding and using the Mercury ZX1 SoC module.
Summary
This document first gives an overview of the Mercury ZX1 SoC module followed by a detailed description of
its features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product ME-ZX1 Mercury ZX1 SoC Module
Document Information Reference Version Date
Reference / Version / Date D-0000-403-002 05 25.07.2019
Approval Information Name Position Date
Written by DIUN Design Engineer 05.09.2016
Verified by GLAC Design Expert 06.10.2016
Approved by DIUN Manager, BU SP 25.07.2019
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2019 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior
written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the date
of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
05 25.07.2019 DIUN Added information on voltage monitoring, power supplies, heat sink,
Linux how-to guide, updated DDR memory types and EEPROM map
description, corrected module dimensions, other style updates
04 21.08.2018 DIUN Minor corrections and style updates
03 29.09.2017 DIUN Updated for revision 3
02 04.05.2017 DIUN Updated EEPROM map, block diagram and footprint information
01 27.12.2016 DIUN Version 01
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Table of Contents
1 Overview 6
1.1 General ................................................... 6
1.1.1 Introduction ................................................ 6
1.1.2 Warranty .................................................. 6
1.1.3 RoHS .................................................... 6
1.1.4 DisposalandWEEE ............................................ 6
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.6 ElectrostaticDischarge .......................................... 7
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features................................................... 7
1.3 Deliverables ................................................ 8
1.4 Accessories................................................. 8
1.4.1 ReferenceDesign ............................................. 8
1.4.2 EnclustraBuildEnvironment ....................................... 8
1.4.3 Mercury+PE1BaseBoard ........................................ 8
1.5 XilinxToolSupport ............................................ 9
2 Module Description 10
2.1 BlockDiagram............................................... 10
2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 TopandBottomViews .......................................... 13
2.4.1 TopView .................................................. 13
2.4.2 BottomView................................................ 13
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1 TopAssemblyDrawing .......................................... 14
2.5.2 BottomAssemblyDrawing........................................ 14
2.6 ModuleFootprint ............................................. 15
2.7 MechanicalData.............................................. 16
2.8 ModuleConnector ............................................ 16
2.9 UserI/O................................................... 17
2.9.1 Pinout.................................................... 17
2.9.2 I/OPinExceptions............................................. 18
2.9.3 DifferentialI/Os .............................................. 19
2.9.4 I/OBanks.................................................. 19
2.9.5 VREFUsage................................................. 20
2.9.6 VCC_IOUsage ............................................... 20
2.9.7 SignalTerminations ............................................ 22
2.9.8 MultiplexedI/O(MIO)Pins........................................ 22
2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.11 Power.................................................... 24
2.11.1 PowerGenerationOverview ....................................... 24
2.11.2 PowerEnable/PowerGood........................................ 25
2.11.3 VoltageSupplyInputs........................................... 26
2.11.4 VoltageSupplyOutputs ......................................... 26
2.11.5 PowerConsumption............................................ 27
2.11.6 HeatDissipation.............................................. 27
2.11.7 VoltageMonitoring ............................................ 27
2.12 ClockGeneration ............................................. 28
2.13 Reset .................................................... 28
2.14 LEDs..................................................... 28
2.15 DDR3SDRAM(PS)............................................. 29
2.15.1 DDR3SDRAMType ............................................ 29
2.15.2 SignalDescription............................................. 30
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2.15.3 Termination................................................. 30
2.15.4 Parameters................................................. 30
2.15.5 DDR3LowVoltageOperation ...................................... 31
2.16 DDR3SDRAM(PL)............................................. 31
2.16.1 DDR3SDRAMType ............................................ 31
2.16.2 SignalDescription............................................. 32
2.16.3 Termination................................................. 32
2.16.4 Parameters................................................. 32
2.16.5 DDR3LowVoltageOperation ...................................... 33
2.17 QSPIFlash ................................................. 33
2.17.1 QSPIFlashType .............................................. 33
2.17.2 SignalDescription............................................. 34
2.17.3 Configuration ............................................... 34
2.17.4 QSPIFlashCorruptionRisk........................................ 34
2.18 NANDFlash ................................................ 35
2.18.1 NANDFlashType ............................................. 35
2.18.2 SignalDescription............................................. 35
2.18.3 Parameters................................................. 35
2.19 SDCard................................................... 35
2.20 GigabitEthernet.............................................. 36
2.20.1 EthernetPHYType............................................. 36
2.20.2 SignalDescription............................................. 36
2.20.3 ExternalConnectivity ........................................... 37
2.20.4 MDIOAddress............................................... 37
2.20.5 PHYConfiguration............................................. 37
2.21 DualFastEthernet............................................. 38
2.21.1 EthernetPHYType............................................. 38
2.21.2 SignalDescription............................................. 38
2.21.3 ExternalConnectivity ........................................... 39
2.21.4 MDIOAddress............................................... 39
2.21.5 PHYConfiguration............................................. 39
2.22 USB2.0 ................................................... 39
2.22.1 USBPHYType ............................................... 39
2.22.2 SignalDescription............................................. 39
2.23 Real-TimeClock(RTC)........................................... 40
2.23.1 RTCType .................................................. 40
2.24 SecureEEPROM .............................................. 40
2.24.1 EEPROMType ............................................... 40
3 Device Configuration 41
3.1 ConfigurationSignals........................................... 41
3.2 Pull-UpDuringConfiguration ...................................... 42
3.3 BootMode................................................. 43
3.4 JTAG..................................................... 43
3.4.1 JTAGonModuleConnector ....................................... 44
3.4.2 ExternalConnectivity ........................................... 44
3.5 QSPIBootMode.............................................. 44
3.6 SDCardBootMode............................................ 44
3.7 NANDBootMode............................................. 44
3.8 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.9 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . 45
3.10 NANDFlashProgramming........................................ 45
3.11 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 I2C Communication 47
4.1 Overview .................................................. 47
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4.2 SignalDescription............................................. 47
4.3 I2CAddressMap ............................................. 47
4.4 SecureEEPROM .............................................. 48
4.4.1 MemoryMap ............................................... 48
5 Operating Conditions 51
5.1 AbsoluteMaximumRatings ....................................... 51
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6 Ordering and Support 53
6.1 Ordering .................................................. 53
6.2 Support................................................... 53
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1 Overview
1.1 General
1.1.1 Introduction
The Mercury ZX1 SoC module combines the Xilinx Zynq®-7030/7035/7045 All Programmable SoC (System-
on-Chip) device with USB 2.0 On-The-Go PHY, PCIe® Gen2 ×4/×8, Gigabit Ethernet PHY, dual Fast Ethernet
PHY, two fast DDR3 SDRAM memory channels, NAND flash, multi-gigabit transceivers, high-speed LVDS I/O,
and a real-time clock, forming a complete and powerful embedded processing system.
The use of the Mercury ZX1 SoC module, in contrast to building a custom SoC hardware, significantly re-
duces development effort and redesign risk and improves time-to-market for the embedded system.
Together with Mercury base boards, the Mercury ZX1 SoC module allows the user to quickly build a system
prototype and start with application development.
The Enclustra Build Environment [14] is available for the Mercury ZX1 SoC module. This build system allows
the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the
desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader).
It downloads and compiles all required software, such as U-Boot, Linux, and BusyBox based root file system.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
1.1.3 RoHS
The Mercury ZX1 SoC module is designed and produced according to the Restriction of Hazardous Sub-
stances (RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mercury ZX1 SoC module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mer-
cury ZX1 SoC module.
1.1.5 Safety Recommendations and Warnings
Mercury modules are not designed to be “ready for operation” for the end-user. These can only be used in
combination with suitable base boards. Proper configuration of the hardware before usage is required.
Ensure that the power supply is disconnected from the board before inserting or removing the Mercury ZX1
SoC module, connecting interfaces, replacing batteries, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-
voltage on power or signal lines can also cause permanent damage to the module.
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Warning!
It is possible to mount the Mercury ZX1 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
ZX1 SoC module.
The base board and module may be damaged if the module is mounted the wrong way round and
powered up.
1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mercury ZX1 SoC module is a Class A product and is not intended for use in domestic environments.
The product may cause electromagnetic interference, for which appropriate measures must be taken.
1.2 Features
•Xilinx Zynq®-7030/7035/7045 All Programmable SoC, FBG676/FFG676 package
•Dual ARM® Cortex™-A9 MPCore™with CoreSight™ and NEON™ extension
•Xilinx Kintex-7 28 nm FPGA fabric
•Zynq-7030: 170 user I/Os
•12 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART) shared with FPGA I/Os
•138 FPGA I/Os (single-ended or differential)
•66 FPGA I/Os up to 3.3 V
•84 FPGA I/Os up to 1.8 V
•20 MGT signals (clock and data)
•Zynq-7035/7045: 178 user I/Os
•12 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART) shared with FPGA I/Os
•126 FPGA I/Os (single-ended or differential)
•66 FPGA I/Os up to 3.3 V
•72 FPGA I/Os up to 1.8 V
•40 MGT signals (clock and data)
•Zynq-7030: 4 MGTs @ 6.6 Gbit/sec and 2 reference input clock differential pairs
•Zynq-7035: 8 MGTs @ 6.6 Gbit/sec and 4 reference input clock differential pairs
•Zynq-7045: 8 MGTs @ 10.3125 Gbit/sec and 4 reference input clock differential pairs
•PCIe Gen2 ×4/×8 (Xilinx integrated PCIe block)
•1 GB DDR3 SDRAM connected to the Processing System (PS)
•256 MB DDR3 SDRAM connected to the Programmable Logic (PL)
•512 MB NAND flash
•64 MB quad SPI flash
•Gigabit Ethernet
•Dual Fast Ethernet
•USB 2.0 On-The-Go (OTG)
•Real-time clock
•5 to 15 V supply voltage
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1.3 Deliverables
•Mercury ZX1 SoC module
•Mercury ZX1 SoC module documentation, available via download:
•Mercury ZX1 SoC Module User Manual (this document)
•Mercury ZX1 SoC Module Reference Design [2]
•Mercury ZX1 SoC Module IO Net Length Excel Sheet [3]
•Mercury ZX1 SoC Module FPGA Pinout Excel Sheet [4]
•Mercury ZX1 SoC Module User Schematics (PDF) [5]
•Mercury ZX1 SoC Module Known Issues and Changes [6]
•Mercury ZX1 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [7]
•Mercury ZX1 SoC Module 3D Model (PDF) [8]
•Mercury ZX1 SoC Module STEP 3D Model [9]
•Module Pin Connection Guidelines [10]
•Mercury Master Pinout [11]
•Enclustra Modules Heat Sink Application Note [17]
•Enclustra Build Environment [14] (Linux build environment; refer to Section 1.4.2 for details)
•Enclustra Build Environment How-To Guide [15]
1.4 Accessories
1.4.1 Reference Design
The Mercury ZX1 SoC module reference design features an example configuration for the Zynq-7000 SoC
device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from the Enclustra download page [2].
1.4.2 Enclustra Build Environment
The Enclustra Build Environment (EBE) [14] enables the user to quickly set up and run Linux on any Enclustra
SoC module or system board. It allows the user to choose the desired target, and download all the required
binaries, such as bitstream and FSBL. It downloads and compiles all required software, such as U-Boot, Linux,
and BusyBox based root file system.
The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface (CLI)
that facilitates the automatic build flow.
The Enclustra Build Environment How-To Guide [15] describes in more detail how to use the EBE to customize
the provided software for the user application. The document provides information on the configuration
options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications, customization
of device trees and integration of existing or new kernel drivers.
1.4.3 Mercury+ PE1 Base Board
•168-pin Hirose FX10 module connectors (PE1-200: 2 connectors; PE1-300/400: 3 connectors)
•System controller
•Power control
•System monitor (PE1-300/400)
•Current sense (PE1-300/400)
•Low-jitter clock generator (PE1-300/400)
•Accelerometer/magnetometer/temperature sensor (PE1-300/400)
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•microSD card holder
•User EEPROM
•eMMC managed NAND flash (PE1-300/400)
•PCIe ×4 interface
•USB 3.0 device connector
•USB 2.0 host connector (PE1-200: 1 connector; PE1-300/400: 4 connectors)
•Micro USB 2.0 device (UART, SPI, I2C, JTAG) connector
•2×RJ45 Gigabit Ethernet connectors
•mPCIe/mSATA card holder (USB only) (PE1-300/400)
•SIM card holder (optional, PE1-300/400 only)
•SMA clock and data in/out (optional, PE1-300/400 only)
•1×FMC LPC connector (PE1-200)
•1×FMC HPC connector (PE1-300)
•2×FMC LPC connector (PE1-400)
•2×40-pin Anios pin header
•3×12-pin Pmod™ pin header
•5 to 15 V DC supply voltage
•USB bus power (with restrictions)
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
1.5 Xilinx Tool Support
The SoC devices equipped on the Mercury ZX1 SoC module are supported by the Vivado HL WebPACK
Edition or by the Vivado HL Design Edition software, depending on the device’s density. Table 1 presents
the correspondence between devices and tools. Please contact Xilinx for further information.
Module Xilinx Tool Support Costs
ME-ZX1-30 Vivado HL WebPACK Edition Free of charge
ME-ZX1-35 Vivado HL Design Edition Paid license required
ME-ZX1-45 Vivado HL Design Edition Paid license required
Table 1: Xilinx Tool Support
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2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mercury ZX1 SoC module is the Xilinx Zynq-7000 SoC device. Most of its I/O
pins are connected to the Mercury module connector, making up to 150 regular user I/Os available to the
user. Further, up to eight multi-gigabit transceivers with support for PCIe Gen2 ×8 are available on the
module connector.
The SoC device can boot from the on-board QSPI flash, NAND flash or from an external SD card. For de-
velopment purposes, a JTAG interface is connected to Mercury module connector.
The memory subsystem is built from a 512 MB NAND flash, a 64 MB quad SPI flash, 1 GB DDR3 SDRAM con-
nected to the Processing System (PS) and 256 MB DDR3 SDRAM connected to the Programmable Logic (PL).
Further, the module is equipped with a Gigabit Ethernet PHY, dual Fast Ethernet PHY, and a USB 2.0 OTG
PHY, making it ideal for communication applications.
A real-time clock is available on the module and is connected to the global I2C bus.
On-board clock generation is based on a 33.33 MHz crystal oscillator for the PS and a 200 MHz LVDS oscil-
lator for the PL.
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The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of
these voltages are available on the Mercury module connectors to supply circuits on the base board.
Four LEDs are connected to the SoC pins for status signaling.
2.2 Module Configuration and Product Codes
Table 2 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
Product Code SoC DDR3/DDR3L DDR3/DDR3L Temperature
SDRAM (PS) SDRAM (PL) Range
ME-ZX1-30-2I-D10 XC7Z030-2FBG676I 1024 MB 256 MB -40 to +85◦C
ME-ZX1-35-1I-D10 XC7Z035-1FBG676I 1024 MB 256 MB -40 to +85◦C
ME-ZX1-45-2I-D10-P XC7Z045-2FFG676I 1024 MB 256 MB -40 to +85◦C
Table 2: Standard Module Configurations
The product code indicates the module type and main features. Figure 2 describes the fields within the
product code.
Figure 2: Product Code Fields
Please note that for the first revision modules or early access modules, the product code may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 Article Numbers and Article Codes
Every module is uniquely labeled, showing the article number and serial number. An example is presented
in Figure 3.
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Figure 3: Module Label
The correspondence between article number and article code is shown in Table 3. The article code repre-
sents the product code, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mercury ZX1 SoC Module Known Issues
and Changes document [6].
Article Number Article Code
EN100644 ME-ZX1-30-2I-D10-R1
EN100645 ME-ZX1-35-1I-D10-R1
EN100646 ME-ZX1-45-2I-D10-P-R1
EN101075 ME-ZX1-30-2C-D10-R2
EN101076 ME-ZX1-30-2I-D10-R2
EN101077 ME-ZX1-35-1C-D10-R2
EN101078 ME-ZX1-35-1I-D10-R2
EN101079 ME-ZX1-45-2C-D10-P-R2
EN101080 ME-ZX1-45-2I-D10-P-R2
EN101723 ME-ZX1-30-2C-D10-R3
EN101724 ME-ZX1-30-2I-D10-R3
EN101725 ME-ZX1-35-1C-D10-R3
EN101726 ME-ZX1-35-1I-D10-R3
EN101727 ME-ZX1-45-2C-D10-P-R3
EN101728 ME-ZX1-45-2I-D10-P-R3
Table 3: Article Numbers and Article Codes
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2.4 Top and Bottom Views
2.4.1 Top View
Figure 4: Module Top View
2.4.2 Bottom View
Figure 5: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 6: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 7: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.6 Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board.
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 72 or 74
mm and having different topologies for the mounting holes. If different module types shall be fixed on the
base board by screws, additional mounting holes may be required to accommodate different modules. The
footprints of the module connectors for the base board design are available for different PCB design tools
(Altium, PADS, Eagle, Orcad) [7] and include the required information on the module sizes and holes.
The maximum component height under the module is dependent on the connector type - refer to Section
2.8 for detailed connector information.
Figure 8: Module Footprint - Top View
Warning!
It is possible to mount the Mercury ZX1 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
ZX1 SoC module.
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2.7 Mechanical Data
Table 4 describes the mechanical characteristics of the Mercury ZX1 SoC module. A 3D model (PDF) and a
STEP 3D model are available [8], [9].
Symbol Value
Size 64 ×54 mm
Component height top 3.0 mm
Component height bottom 1.45 mm
Weight 28 g
Table 4: Mechanical Data
2.8 Module Connector
Two Hirose FX10 168-pin 0.5 mm pitch headers with a total of 336 pins have to be integrated on the base
board. Up to four M3 screws may be used to mechanically fasten the module to the base board. Do not
use excessive force to tighten the screws, as this could damage the module.
The pinout of the module connector is found in the Mercury Master Pinout Excel Sheet [11]. The connector
is available in different packaging options and different stacking heights. Some examples are presented in
Table 5. Please refer to the connector datasheet for more information.
Reference Type Description
Mercury module connector FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm pitch
Base board connector FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4 mm stacking
height
Base board connector FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5 mm stacking
height
Table 5: Module Connector Types
Figure 9 indicates the pin numbering for the Mercury module connectors from the top view of the base
board. The connector pins are numbered as follows:
•Connector A: from J700-1 to J700-168
•Connector B: from J701-1 to J701-168
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Figure 9: Pin Numbering for the Module Connector
Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9 User I/O
2.9.1 Pinout
Information on the Mercury ZX1 SoC module pinout can be found in the Enclustra Mercury Master Pinout
[11], and in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mercury ZX1 SoC module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B33_L12_MRCC_J3_N is located on pin J3 of I/O bank 33, pair 12, it is an MRCC (Multi-Region
Clock Capable) pin and it has negative polarity, when used in a differential pair.
For the signal lines shared between Programmable Logic (PL) and Processing System (PS), the naming con-
vention is:
IO_<MIO_PIN>_<FUNCTION>_B<BANK>_<PACKAGE_PIN>
For example, IO_MIO44_SDD2_B12_AC17 is connected to FPGA pin AC17 and in parallel to the PS MIO pin 44.
Please note that for the shared pins only one of the driving pins (FPGA pin, MIO pin) may be active.
The multi-region clock capable pins are marked with “MRCC”, while the single region clock capable pins are
marked with “SRCC” in the signal name. For details on their function and usage, please refer to the Xilinx
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documentation.
Table 6 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name Signals Pairs Diff. Single- I/O Comments
ended Bank
IO_<MIO_PIN>_<...>_B12_<...> 12 6 In/Out In/Out 12 Shared between PL
and PS
IO_B12_<...> 4 2 In/Out In/Out 12
IO_B13_<...> 50 24 In/Out In/Out 13
IO_B33_<...> 46 23 In/Out In/Out 33 Only 36 sig-
nals available on
XC7Z035/XC7Z045
devices
IO_B34_<...> 38 19 In/Out In/Out 34 Only 36 sig-
nals available on
XC7Z035/XC7Z045
devices
Total (XC7Z030) 150 75 - - -
Total (XC7Z035/XC7Z045) 138 68 - - -
Table 6: User I/Os
Please note that for the 7 Series FPGAs there are restrictions on the VCCO voltage when using LVDS I/Os;
refer to Xilinx AR# 43989 for details.
2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions.
I/O Pins with Different Functions Depending on the Equipped SoC Device
On the Mercury ZX1 SoC modules equipped with bigger SoC devices (XC7Z035/XC7Z045) there are eight
MGT transceiver lines and four differential clock inputs available.
On the modules equipped with smaller SoC devices (XC7Z030) there are only four MGT transceiver lines and
2 differential clock inputs available. Instead, the transmission (TX) signals of the upper MGT pairs (pairs 4-7)
and two differential clock pairs are rerouted to regular user I/Os from FPGA banks 33 and 34. The receiver
(RX) signals of the upper MGT pairs are not connected to any FPGA bank on the smaller module.
Table 7 presents the I/O pin exceptions on the Mercury ZX1 SoC module.
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I/O Module Description
Name Conn. Pin XC7Z030 XC7Z035/XC7Z045
MGT_REFCLK<2-3>_<...> B-3, 5, 7, 9 These pins are connected to
user I/Os in FPGA banks 33
and 34
These pins are connected
to the MGTs in FPGA
bank 111
MGT_TX<4-7>_<...> B-45, 47, 51, 53, 63,
65, 69, 71
MGT_RX<4-7>_<...> B-48, 50, 54, 56, 60,
62, 66, 68
These pins are not con-
nected
These pins are connected
to the MGTs in FPGA
bank 111
Table 7: I/O Pin Exceptions - I/O Pins with Different Functions Depending on the Equipped SoC Device
2.9.3 Differential I/Os
When using differential pairs, a differential impedance of 100 Ωmust be matched on the base board, and
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the SoC device to the module connector is
available in Mercury ZX1 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total
length of the differential pairs on the base board if required by the application.
2.9.4 I/O Banks
Table 8 describes the main attributes of the Programmable Logic (PL) and Processing System (PS) I/O banks,
and indicates which peripherals are connected to each I/O bank. All I/O pins within a particular I/O bank
must use the same I/O (VCC_IO) and reference (VREF) voltages.
Bank Connectivity VCC_IO VREF
MGT Bank 111
Module connector 1.2 V -
(not available on
XC7Z030 device)
MGT Bank 112 Module connector 1.2 V -
Bank 0 Configuration User selectable -
VCC_CFG_MIO_B12
Bank 12 Module connector, User selectable -
Fast Ethernet PHYs, I2C VCC_CFG_MIO_B12
Bank 13 Module connector User selectable IO_B13_L6_VREF_AB24_N
VCC_IO_B13 IO_B13_L19_VREF_Y20_N
Bank 33 Module connector, oscillator User selectable IO_B33_L6_VREF_E3_N
VCC_IO_B33 IO_B33_L19_VREF_L7_N
Continued on next page...
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Bank Connectivity VCC_IO VREF
Bank 34 Module connector, I2C, User selectable IO_B34_L6_VREF_H8_N
Fast Ethernet PHYs, LEDs VCC_IO_B34 IO_B34_L19_VREF_C3_N
Bank 35 DDR3 SDRAM (PL) User selectable1 0.5 ×VCC_DDR3
VCC_DDR3
PS MIO0 QSPI and NAND flash User selectable -
VCC_CFG_MIO_B12
PS MIO1 Module connector, USB PHY, User selectable 0.9 V
Gigabit Ethernet PHY VCC_CFG_MIO_B12
PS DDR DDR3 SDRAM (PS) User selectable1 0.5 ×VCC_DDR3
VCC_DDR3
Table 8: I/O Banks
1
2.9.5 VREF Usage
I/O standards referenced using VREF can be used on the Mercury module connector. The reference voltage
has to be applied to all VREF pins of the respective I/O banks. If a bank is configured to use an I/O standard
that does not need a reference voltage, the VREF pins of this bank on the module connector are available
as user I/O pins.
The VREF pins are listed in the Mercury Master Pinout Excel Sheet [11].
Warning!
Use only VREF voltages compliant with the equipped SoC device; any other voltages may damage the
equipped SoC device, as well as other devices on the Mercury ZX1 SoC module.
Do not leave a VREF pin floating when the used I/O standard requires a reference voltage, as this may
damage the equipped SoC device, as well as other devices on the Mercury ZX1 SoC module.
2.9.6 VCC_IO Usage
The VCC_IO voltages for the I/O banks located on the module connector are configurable by applying the
required voltage to the VCC_IO_B[x], respectively VCC_CFG_[x] pins. All VCC_IO_B[x] or VCC_CFG_[x] pins of
the same bank must be connected to the same voltage.
For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per
module connector.
The high performance (HP) I/O banks 33 and 34 are protected against too high supply voltages. If a voltage
higher than 2.2 V is applied to the corresponding supply inputs on the module connector, the supply pins
of the SoC device are disconnected, and the device is held in reset.
1The DDR3 SDRAM supports voltages of 1.5 or 1.35 V. Please refer to Sections 2.15 and 2.16 for details.
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