Enclustra Mercury SA1 SoC Module User manual

Mercury SA1 SoC Module
User Manual
Purpose
The purpose of this document is to present the characteristics of Mercury SA1 SoC module to the user, and
to provide the user with a comprehensive guide to understanding and using the Mercury SA1 SoC module.
Summary
This document first gives an overview of the Mercury SA1 SoC module followed by a detailed description of
its features and configuration options. In addition, references to other useful documents are included.
Product Information Code Name
Product ME-SA1 Mercury SA1 SoC Module
Document Information Reference Version Date
Reference / Version / Date D-0000-402-002 06 16.02.2021
Approval Information Name Position Date
Written by DIUN Design Engineer 05.08.2016
Verified by GLAC Design Expert 06.09.2016
Approved by DIUN Manager, BU SP 16.02.2021
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Phone [phone] – www.enclustra.com

Copyright Reminder
Copyright 2021 by Enclustra GmbH, Switzerland. All rights are reserved.
Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior
written permission of Enclustra GmbH, Switzerland.
Although Enclustra GmbH believes that the information included in this publication is correct as of the date
of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
All information in this document is strictly confidential and may only be published by Enclustra GmbH,
Switzerland.
All referenced trademarks are the property of their respective owners.
Document History
Version Date Author Comment
06 16.02.2021 DIUN Cleaned-up product variants, added information on Mercury
heatsinks, added Mercury+ ST1 to accesories section, added infor-
mation on FPGA fuses and warranty, on differential I/Os, on voltage
monitoring outputs, other style updates
05 25.07.2019 DIUN Added information on power supplies, Linux how-to guide, JTAG in-
terface, other style updates
04 03.01.2019 DIUN Updated for revision 3 modules, added information on voltage mon-
itoring and heat sink
03 21.08.2018 DIUN Minor corrections and style updates
02 04.05.2017 DIUN Updated EEPROM map, block diagram and footprint information
01 27.12.2016 DIUN Version 01
D-0000-402-002 2 / 49 Version 06, 16.02.2021

Table of Contents
1 Overview 5
1.1 General ................................................... 5
1.1.1 Introduction ................................................ 5
1.1.2 Warranty .................................................. 5
1.1.3 RoHS .................................................... 5
1.1.4 DisposalandWEEE ............................................ 5
1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.6 ElectrostaticDischarge .......................................... 6
1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Features................................................... 6
1.3 Deliverables ................................................ 6
1.4 Accessories................................................. 7
1.4.1 ReferenceDesign ............................................. 7
1.4.2 EnclustraBuildEnvironment ....................................... 7
1.4.3 EnclustraHeatSink ............................................ 7
1.4.4 Mercury+PE1BaseBoard ........................................ 7
1.4.5 Mercury+ST1BaseBoard ........................................ 8
1.5 IntelToolSupport............................................. 8
2 Module Description 9
2.1 BlockDiagram............................................... 9
2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 TopandBottomViews .......................................... 12
2.4.1 TopView .................................................. 12
2.4.2 BottomView................................................ 12
2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 TopAssemblyDrawing .......................................... 13
2.5.2 BottomAssemblyDrawing........................................ 13
2.6 ModuleFootprint ............................................. 14
2.7 MechanicalData.............................................. 15
2.8 ModuleConnector ............................................ 15
2.9 UserI/O................................................... 16
2.9.1 Pinout.................................................... 16
2.9.2 I/OPinExceptions............................................. 17
2.9.3 DifferentialI/Os .............................................. 18
2.9.4 I/OBanks.................................................. 19
2.9.5 VCC_IOUsage ............................................... 20
2.9.6 SignalTerminations ............................................ 21
2.9.7 HPSI/OPins ................................................ 21
2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.11 Power.................................................... 23
2.11.1 PowerGenerationOverview ....................................... 23
2.11.2 PowerEnable/PowerGood........................................ 23
2.11.3 VoltageSupplyInputs........................................... 24
2.11.4 VoltageSupplyOutputs ......................................... 24
2.11.5 PowerConsumption............................................ 25
2.11.6 HeatDissipation.............................................. 25
2.11.7 VoltageMonitoring ............................................ 26
2.12 ClockGeneration ............................................. 26
2.13 Reset .................................................... 27
2.14 LEDs..................................................... 27
2.15 DDR3LSDRAM............................................... 28
2.15.1 DDR3LSDRAMType ........................................... 28
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2.15.2 SignalDescription............................................. 28
2.15.3 Termination................................................. 28
2.15.4 Parameters................................................. 29
2.16 QSPIFlash ................................................. 30
2.16.1 QSPIFlashType .............................................. 30
2.16.2 SignalDescription............................................. 30
2.16.3 QSPIFlashCorruptionRisk........................................ 30
2.17 SDCard................................................... 30
2.17.1 SignalDescription............................................. 31
2.18 eMMCFlash ................................................ 31
2.18.1 eMMCFlashType ............................................. 31
2.18.2 SignalDescription............................................. 32
2.19 GigabitEthernet.............................................. 32
2.19.1 EthernetPHYType............................................. 32
2.19.2 SignalDescription............................................. 32
2.19.3 ExternalConnectivity ........................................... 32
2.19.4 MDIOAddress............................................... 32
2.19.5 PHYConfiguration............................................. 32
2.20 USB2.0 ................................................... 33
2.20.1 USBPHYType ............................................... 33
2.20.2 SignalDescription............................................. 33
2.21 Real-TimeClock(RTC)........................................... 33
2.21.1 RTCType .................................................. 34
2.22 SecureEEPROM .............................................. 34
2.22.1 EEPROMType ............................................... 34
3 Device Configuration 35
3.1 ConfigurationSignals........................................... 35
3.2 BootMode................................................. 36
3.3 JTAG..................................................... 37
3.3.1 JTAGonModuleConnector ....................................... 37
3.3.2 HPSJTAGConnector ........................................... 38
3.3.3 ExternalConnectivity ........................................... 38
3.4 PassiveSerialConfiguration ....................................... 38
3.5 eMMCBootMode............................................. 38
3.6 QSPIBootMode.............................................. 39
3.7 SDCardBootMode............................................ 39
3.8 eMMCFlashProgramming........................................ 39
3.9 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 I2C Communication 41
4.1 Overview .................................................. 41
4.2 SignalDescription............................................. 41
4.3 I2CAddressMap ............................................. 41
4.4 SecureEEPROM .............................................. 42
4.4.1 MemoryMap ............................................... 42
5 Operating Conditions 45
5.1 AbsoluteMaximumRatings ....................................... 45
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 Ordering and Support 46
6.1 Ordering .................................................. 46
6.2 Support................................................... 46
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1 Overview
1.1 General
1.1.1 Introduction
The Mercury SA1 SoC module combines the Altera Cyclone® V ARM® processor-based SoC (System-on-
Chip) device with fast DDR3L SDRAM, USB 2.0 On-The-Go PHY, PCIe® Gen1 ×4, Gigabit Ethernet, multi-
gigabit transceivers, high-speed LVDS I/O, and is available in industrial temperature range, forming a com-
plete and powerful embedded processing system.
The use of the Mercury SA1 SoC module, in contrast to building a custom SoC hardware, significantly simpli-
fies system design and thus shortens time to market and decreases the development effort of your product.
Together with Mercury base boards, the Mercury SA1 SoC module allows the user to quickly build a system
prototype and start with application development.
The Enclustra Build Environment [14] is available for the Mercury SA1 SoC module. This build system allows
the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the
desired target, and download all the required binaries, such as bitstream and preloader. It downloads and
compiles all required software, such as U-Boot, Linux, and BusyBox based root file system.
1.1.2 Warranty
Please refer to the General Business Conditions, available on the Enclustra website [1].
Warning!
Please note that the warranty of an Enclustra module is voided if the FPGA fuses are blown. This
operation is done at own risk, as it is irreversible. Enclustra cannot test the module in case of a warranty
product return.
1.1.3 RoHS
The Mercury SA1 SoC module is designed and produced according to the Restriction of Hazardous Sub-
stances (RoHS) Directive (2011/65/EC).
1.1.4 Disposal and WEEE
The Mercury SA1 SoC module must be properly disposed of at the end of its life.
The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mer-
cury SA1 SoC module.
1.1.5 Safety Recommendations and Warnings
Mercury modules are not designed to be “ready for operation” for the end-user. These can only be used in
combination with suitable base boards. Proper configuration of the hardware before usage is required.
Ensure that the power supply is disconnected from the board before inserting or removing the Mercury SA1
SoC module, connecting interfaces, or connecting jumpers.
Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-
voltage on power or signal lines can also cause permanent damage to the module.
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Warning!
It is possible to mount the Mercury SA1 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
SA1 SoC module.
The base board and module may be damaged if the module is mounted the wrong way round and
powered up.
1.1.6 Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7 Electromagnetic Compatibility
The Mercury SA1 SoC module is a Class A product (as defined in IEC 61000-3-2 standard) and is not in-
tended for use in domestic environments. The product may cause electromagnetic interference, for which
appropriate measures must be taken.
1.2 Features
•Altera Cyclone V SOC 5CSXFC6C6U23C8N/5CSXFC6C6U23I7N
•ARM dual-core Cortex A9
•Altera Cyclone V 28 nm FPGA fabric
•178 user I/Os up to 3.3 V
•16 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)
•134 FPGA I/Os (single-ended or differential)
•28 MGT signals (clock and data)
•6 MGTs @ 3.125 Gbit/sec and 2 reference input clock differential pairs
•PCIe Gen1 ×4 (Altera PCIe hardened IP block)
•1 GB DDR3L SDRAM
•64 MB quad SPI flash
•16 GB eMMC flash (starting with revision 3)
•Gigabit Ethernet
•USB 2.0 On-The-Go (OTG)
•CAN, UART, SPI, I2C, SDIO/MMC
•Real-time clock
•Small form factor (56 ×54 mm)
•5 to 15 V supply voltage
1.3 Deliverables
•Mercury SA1 SoC module
•Mercury SA1 SoC module documentation, available via download:
•Mercury SA1 SoC Module User Manual (this document)
•Mercury SA1 SoC Module Reference Design [2]
•Mercury SA1 SoC Module IO Net Length Excel Sheet [3]
•Mercury SA1 SoC Module FPGA Pinout Excel Sheet [4]
•Mercury SA1 SoC Module User Schematics (PDF) [5]
•Mercury SA1 SoC Module Known Issues and Changes [6]
•Mercury SA1 SoC Module Footprint (Altium, Eagle, Orcad and PADS) [7]
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•Mercury SA1 SoC Module 3D Model (PDF) [8]
•Mercury SA1 SoC Module STEP 3D Model [9]
•Mercury Mars Module Pin Connection Guidelines [10]
•Mercury Master Pinout [11]
•Mercury Heatsink Application Note [17]
•Enclustra Build Environment [14] (Linux build environment; refer to Section 1.4.2 for details)
•Enclustra Build Environment How-To Guide [15]
1.4 Accessories
1.4.1 Reference Design
The Mercury SA1 SoC module reference design features an example configuration for the Cyclone V SoC
device, together with an example top level HDL file for the user logic.
A number of software applications are available for the reference design, that show how to initialize the
peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the
archive, so that the user can easily check that the hardware is functional.
The reference design can be downloaded from the Enclustra download page [2].
1.4.2 Enclustra Build Environment
The Enclustra Build Environment (EBE) [14] enables the user to quickly set up and run Linux on any Enclustra
SoC module or system board. It allows the user to choose the desired target, and download all the required
binaries, such as bitstream and preloader/bootloader. It downloads and compiles all required software, such
as U-Boot, Linux, and BusyBox based root file system.
The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface (CLI)
that facilitates the automatic build flow.
The Enclustra Build Environment How-To Guide [15] describes in more detail how to use the EBE to customize
the provided software for the user application. The document provides information on the configuration
options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications, customization
of device trees and integration of existing or new kernel drivers.
1.4.3 Enclustra Heat Sink
For Mercury modules an Enclustra heat sink is available for purchase along with the product. Please refer
to section 2.11.6 for further information on the available cooling options.
1.4.4 Mercury+ PE1 Base Board
•168-pin Hirose FX10 module connectors (PE1-200: 2 connectors; PE1-300/400: 3 connectors)
•System controller
•Power control
•System monitor (PE1-300/400)
•Current sense (PE1-300/400)
•Low-jitter clock generator (PE1-300/400)
•microSD card holder
•User EEPROM
•eMMC managed NAND flash (PE1-300/400)
•PCIe ×4 interface
•USB 3.0 device connector
•USB 2.0 host connector (PE1-200: 1 connector; PE1-300/400: 4 connectors)
•Micro USB 2.0 device (UART, SPI, I2C, JTAG) connector
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•2×RJ45 Gigabit Ethernet connectors
•mPCIe/mSATA card holder (USB only) (PE1-300/400)
•SIM card holder (optional, PE1-300/400 only)
•SMA clock and data in/out (optional, PE1-300/400 only)
•1×FMC LPC connector (PE1-200)
•1×FMC HPC connector (PE1-300)
•2×FMC LPC connector (PE1-400)
•2×40-pin Anios pin header
•3×12-pin IO headers
•5 to 15 V DC supply voltage
•USB bus power (with restrictions)
Please note that the available features depend on the equipped Mercury module type and on the selected
base board variant.
1.4.5 Mercury+ ST1 Base Board
•168-pin Hirose FX10 module connectors (3 connectors)
•2×MIPI D-PHY connectors: CSI and CSI/DSI (requires FPGA support)
•Mini DisplayPort connector (requires FPGA support)
•HDMI connector (requires FPGA support)
•SFP+ connector
•Low-jitter clock generator
•USB 3.0 device connector
•USB 3.0 host connector
•FTDI USB 2.0 device controller with micro USB device connector (UART, SPI, I2C, JTAG)
•2×RJ45 Gigabit Ethernet connectors
•1×FMC HPC connector (note: not all pins are available)
•2×40-pin Anios pin header
•3×12-pin IO headers
•microSD card holder
•5 to 15 V DC supply voltage
•Form factor: 100 ×120 mm
Please note that the available features depend on the equipped Mercury module type.
1.5 Intel Tool Support
The SoC devices equipped on the Mercury SA1 SoC module are supported by the Quartus Prime Lite Edition
(or Quartus II Web Edition, for older software versions), which is available free of charge. Please contact Intel
for further information.
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2 Module Description
2.1 Block Diagram
Figure 1: Hardware Block Diagram
The main component of the Mercury SA1 SoC module is the Intel Cyclone V SoC device. Most of its I/O
pins are connected to the Mercury module connectors, making 150 regular user I/Os available to the user.
Further, six multi-gigabit transceivers with support for PCIe Gen1 ×4 are available on the module connectors.
The SoC device can boot from the on-board QSPI flash or from an external SD card. For development pur-
poses, a JTAG interface is connected to Mercury module connector.
The memory subsystem is built from a 64 MB QSPI flash and 1 GB DDR3L SDRAM in the standard config-
uration. Starting with revision 3 modules, a 16 GB eMMC flash is available on the module for booting the
SoC device or for storing user data.
Further, the module is equipped with a Gigabit Ethernet PHY and a USB 2.0 OTG PHY, making it ideal for
communication applications.
A real-time clock is available on the module and is connected to the global I2C bus.
On-board clock generation is based on a 50 MHz crystal oscillator.
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The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of
these voltages are available on the Mercury module connectors to supply circuits on the base board.
Four LEDs are connected to the SoC pins for status signaling.
2.2 Module Configuration and Product Codes
Table 1 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
Product Code SoC DDR3L SDRAM PCI Express Temperature Range
ME-SA1-C6-7I-D10 5CSXFC6C6U23I7N 1 GB X-40 to +85◦C
Table 1: Standard Module Configurations
The product code indicates the module type and main features. Figure 2 describes the fields within the
product code.
Figure 2: Product Code Fields
Please note that for the first revision modules or early access modules, the product code may not respect
entirely this naming convention. Please contact Enclustra for details on this aspect.
2.3 Article Numbers and Article Codes
Every module is uniquely labeled, showing the article number and serial number. An example is presented
in Figure 3.
Figure 3: Module Label
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The correspondence between article number and article code is shown in Table 2. The article code repre-
sents the product code, followed by the revision; the R suffix and number represent the revision number.
The revision changes and product known issues are described in the Mercury SA1 SoC Module Known Issues
and Changes document [6].
Article Number Article Code
EN100638 ME-SA1-C6-8C-D10-R1
EN100639 ME-SA1-C6-7I-D10-R1
EN100997 ME-SA1-C5-8C-D10-R2
EN100998 ME-SA1-C5-7I-D10-R2
EN100999 ME-SA1-C6-8C-D10-R2
EN101000 ME-SA1-C6-7I-D10-R2
EN102107 ME-SA1-C5-8C-D10-R3
EN102108 ME-SA1-C6-7I-D10-R3
Table 2: Article Numbers and Article Codes
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2.4 Top and Bottom Views
2.4.1 Top View
Figure 4: Module Top View
2.4.2 Bottom View
Figure 5: Module Bottom View
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.5 Top and Bottom Assembly Drawings
2.5.1 Top Assembly Drawing
Figure 6: Module Top Assembly Drawing
2.5.2 Bottom Assembly Drawing
Figure 7: Module Bottom Assembly Drawing
Please note that depending on the hardware revision and configuration, the module may look slightly dif-
ferent than shown in this document.
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2.6 Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board.
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74
mm and having different topologies for the mounting holes. If different module types shall be fixed on the
base board by screws, additional mounting holes may be required to accommodate different modules. The
footprints of the module connectors for the base board design are available for different PCB design tools
(Altium, PADS, Eagle, Orcad) [7] and include the required information on the module sizes and holes.
The maximum component height on the base board under the module is dependent on the connector
type. Please refer to the Hirose FX10 series product website for detailed connector information [12]. The two
connectors are called A (J700) and B (7801).
Figure 8: Module Footprint - Top View
Warning!
It is possible to mount the Mercury SA1 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the Mercury
SA1 SoC module.
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2.7 Mechanical Data
Table 3 describes the mechanical characteristics of the Mercury SA1 SoC module. A 3D model (PDF) and a
STEP 3D model are available [8], [9].
Symbol Value
Size 56 ×54 mm
Component height top 5.0 mm
Component height bottom 1.35 mm
Weight 20 g
Table 3: Mechanical Data
2.8 Module Connector
Two Hirose FX10 168-pin 0.5 mm pitch headers with a total of 336 pins have to be integrated on the base
board. Up to four M3 screws may be used to mechanically fasten the module to the base board. Do not
use excessive force to tighten the screws, as this could damage the module.
The pinout of the module connector is found in the Mercury Master Pinout Excel Sheet [11]. The connector
is available in different packaging options and different stacking heights. Some examples are presented in
Table 4. Please refer to the connector datasheet for more information.
Reference Type Description
Mercury module connector FX10A-168S-SV Hirose FX10, 168-pin, 0.5 mm pitch
Base board connector FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm pitch, 4 mm stacking
height
Base board connector FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm pitch, 5 mm stacking
height
Table 4: Module Connector Types
Figure 9 indicates the pin numbering for the Mercury module connectors from the top view of the base
board. The connector pins are numbered as follows:
•Connector A: from J700-1 to J700-168
•Connector B: from J701-1 to J701-168
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Figure 9: Pin Numbering for the Module Connector
Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9 User I/O
2.9.1 Pinout
Information on the Mercury SA1 SoC module pinout can be found in the Enclustra Mercury Master Pinout
[11], and in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mercury SA1 SoC module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_<FUNCTION>_<PIN_NAME>_<PACKAGE_PIN>_<POLARITY>
For example, IO_B5A_TX_R5_AC24_P is located on pin AC24 of I/O bank 5A, and when used in a differential
pair it is a transmit pin and has positive polarity.
The clock capable pins are marked with “CLK” in the signal name. For details on their function and usage,
please refer to the Intel documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Please note that Cyclone V devices can only use I/O pins marked with “RX” in the signal name as differential
inputs and only pins marked with “TX” as differential outputs. The I/O pins marked with “CLK” are receive-
only differential signals and can be used as dedicated clock differential inputs. All pins can be used as
single-ended inputs or outputs.
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Signal Name Signals Pairs Differential Single-ended I/O Bank
IO_B3A_RX<...> 8 4 In In/Out 3A
IO_B3A_TX<...> 8 4 Out In/Out 3A
IO_B3B_RX<...> 12 6 In In/Out 3B
IO_B3B_TX<...> 14 7 Out In/Out 3B
IO_B3B_CLK<...> 4 2 In In/Out 3B
IO_B4A_RX<...> 30 15 In In/Out 4A
IO_B4A_CLK<...> 4 2 In In/Out 4A
IO_B4A_TX<...> 28 14 Out In/Out 4A
IO_B5A_RX<...> 8 4 In In/Out 5A
IO_B5A_TX<...> 8 4 Out In/Out 5A
IO_B5B_CLK<...> 4 2 In In/Out 5B
IO_B5B_TX<...> 2 1 Out In/Out 5B
IO_B8A_CLK<...> 2 1 In In/Out 8A
IO_B8A_TX<...> 2 1 Out In/Out 8A
Total 134 67 - - -
Table 5: User I/Os
The IO_B3B_CLK0_B31_<...>_B32_<...> pair is connected to the two FPGA pin pairs B31 and B32. This pair
can be used either as LVDS receive using the B31 pair or as LVDS transmit using the B32 pair. The user may
only use one of these pairs, hence the FPGA design should set both pins of the unused pin pair to high
impedance in order to prevent contention. These pins are regular I/O pins for non-differential applications.
The reason for this special connection is compatibility with certain Mercury base boards.
2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination
with certain Mercury boards they may have a specific role).
Table 6 lists the I/O pin exceptions on the Mercury SA1 SoC module.
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I/O Name Module Connector Pin Description
HPS_GPIO59_MISO A-104 Connected via a 47 kΩresistor to
IO_B5A_RX_R6_PERST#_W15_N pin (A-36) for PCIe
PERST# connection implementation
HPS_GPIO57_CLK A-98 Can optionally be connected via a 47 kΩresistor to
IO_B5A_TX_R3_CVP_AD26_N pin (A-21) for Configura-
tion via Protocol (CVP) implementation (CVP pin can
be connected to PCIe WAKE# pin)
Table 6: I/O Pin Exceptions
When the Mercury SA1 SoC module is used in combination with a Mercury+ PE1 base board as a PCIe
device, the PERST# signal coming from the PCIe edge connector on the module connector pin A-104
(HPS_GPIO59_MISO) is driven further to IO_B5A_RX_R6_PERST#_W15_N.
Because the PCIe block inside the FPGA logic side requires this reset signal, the PERST# signal is connected
to the FPGA pin IO_B5A_RX_R6_PERST#_W15_N via a 47 kΩresistor. In situations in which a custom board is
used or PCIe functionality is not required, this FPGA pin can be used in the same manner as a regular I/O pin.
The connection of the CVP pin to the PCIe WAKE# pin on the Mercury+ PE1 base board is made in a similar
manner - note that the connection is not available in the standard configuration, as not all PCIe cards support
the wake function. Details on the CVP implementation can be found in the Altera CVP documentation [23]
and details on the WAKE# pin are available in the PCIe specification.
2.9.3 Differential I/Os
When using differential pairs, a differential impedance of 100 Ωmust be matched on the base board, and
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the SoC device to the module connector is
available in Mercury SA1 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total
length of the differential pairs on the base board if required by the application.
Warning!
Please note that the trace length of various signals may change between revisions of the Mercury SA1
SoC module. Please use the information provided in the Mercury SA1 SoC Module IO Net Length Excel
Sheet [3] to check which signals are affected. The differential signals will still be routed differentially
in subsequent product revisions.
Please note that Cyclone V devices can only use I/O pins marked with “RX” in the signal name as differential
inputs and only pins marked with “TX” as differential outputs. All pins can be used as single-ended inputs
or outputs.
Warning!
Check Mercury SA1 SoC module pinout with Quartus before producing your own base board hardware,
to make sure that all pins are used according to the correct direction.
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2.9.4 I/O Banks
Table 7 describes the main attributes of the FPGA and Hard Processing System (HPS) I/O banks, and indicates
which peripherals are connected to each I/O bank. All I/O pins within a particular I/O bank must use the
same I/O (VCC_IO) and reference (VREF) voltages.
Bank Connectivity VCC_IO VREF
MGT Bank L0 Module connector 1.1 V -
MGT Bank L1 Module connector 1.1 V -
Bank 3A Module connector User selectable 0 V
VCC_CFG_HPS_B3A_B8A
Bank 3B Module connector User selectable 0.5 ×VCC_IO_B3B_B4A
VCC_IO_B3B_B4A
Bank 4A Module connector User selectable 0.5 ×VCC_IO_B3B_B4A
VCC_IO_B3B_B4A
Bank 5A Module connector User selectable 0.5 ×VCC_IO_B5A_B5B
VCC_IO_B5A_B5B
Bank 5B Module connector User selectable 0.5 ×VCC_IO_B5A_B5B
VCC_IO_B5A_B5B
Bank 8A Module connector, LEDs User selectable 0.5 ×VCC_CFG_HPS_B3A_B8A
VCC_CFG_HPS_B3A_B8A
HPS Bank 6A DDR3L SDRAM 1.35 V 0.68 V
HPS Bank 6B DDR3L SDRAM 1.35 V 0.68 V
HPS Bank 7A Configuration, I2C, LEDs, User selectable 0 V
module connector VCC_CFG_HPS_B3A_B8A
HPS Bank 7B Ethernet PHY, QSPI flash User selectable 0 V
VCC_CFG_HPS_B3A_B8A
HPS Bank 7C
Gigabit Ethernet PHY,
User selectable
0 V
configuration signals,
VCC_CFG_HPS_B3A_B8A
eMMC flash, module
connector
HPS Bank 7D USB PHY User selectable 0 V
VCC_CFG_HPS_B3A_B8A
Table 7: I/O Banks
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2.9.5 VCC_IO Usage
The VCC_IO voltages for the I/O banks located on the module connector are configurable by applying the
required voltage to the VCC_IO_B[x] or VCC_CFG_[x] pins. All VCC_IO_B[x] or VCC_CFG_[x] pins of the same
bank must be connected to the same voltage.
For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per
module connector.
Signal Name SoC Pins Supported Voltages Connector A
Pins
Connector B
Pins
VCC_CFG_HPS_B3A_B8A VCCIO3A,
VCCIO8A,
VCCIO7A-D
1.8 V, 2.5 V - 3.3 V1±5% 74, 77 -
VCC_IO_B3B_B4A VCCIO3B,
VCCIO4A
1.2 V - 3.3 V ±5% - 64, 67, 88, 95,
140, 143
VCC_IO_B5A_B5B VCCIO5A,
VCCIO5B
1.2 V - 3.3 V ±5% 38, 41 -
Table 8: VCC_IO Pins
Note that the VCCPD (I/O pre-driver power supply) for each bank is set automatically to 2.5 V (if the corre-
sponding VCCIO is less than or equal to 2.5 V) or to VCCIO (if the corresponding VCCIO is higher or equal
to 3.0 V).
Warning!
Use only VCC_IO voltages compliant with the equipped SoC device; any other voltages may damage
the equipped SoC device, as well as other devices on the Mercury SA1 SoC module.
Do not leave a VCC_IO pin floating, as this may damage the equipped SoC device, as well as other
devices on the Mercury SA1 SoC module.
Warning!
Do not power the VCC_IO pins when PWR_GOOD and PWR_EN signals are not active. If the module
is not powered, you need to make sure that the VCC_IO voltages are disabled (for example, by using a
switch on the base board, which uses PWR_GOOD as enable signal). Figure 10 illustrates the VCC_IO
power requirements.
1For eMMC flash support VCC_CFG_HPS_B3A_B8A must be either 1.8 V or 3.3 V. The eMMC flash is equipped starting with revision
3 modules.
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