Epson S1D13503 Series User manual

S1D13503 Graphics LCD Controller
S1D13503
TECHNICAL MANUAL
Issue Date: 01/01/30
Document Number: X18A-Q-001-07
Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Downloaded from Elcodis.com electronic components distributor

Page ii Epson Research and Development
Vancouver Design Center
S1D13503 Issue Date: 01/01/30
THIS PAGE LEFT BLANK
Downloaded from Elcodis.com electronic components distributor

Epson Research and Development Page iii
Vancouver Design Center
Issue Date: 01/01/30 S1D13503
CUSTOMER SUPPORT INFORMATION
Comprehensive Support Tools
Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools
for the development of graphics systems.
Evaluation / Demonstration Board
• Assembled and fully tested graphics evaluation board with installation guide and schematics
• To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative
VGA Chip Documentation
• Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference
Software
•VideoBIOS
• OEM Utilities
• User Utilities
• Evaluation Software
• To obtain these programs, contact Application Engineering Support
Application Engineering Support
Engineering and Sales Support is provided by:
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: [phone]
Fax: [phone]
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: [phone]
Fax: [phone]
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: [phone]
Fax: [phone]
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: [phone]
Fax: [phone]
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: [phone]
Fax: [phone]
http://www.eea.epson.com
Downloaded from Elcodis.com electronic components distributor

Page iv Epson Research and Development
Vancouver Design Center
S1D13503 Issue Date: 01/01/30
THIS PAGE LEFT BLANK
Downloaded from Elcodis.com electronic components distributor

Epson Research and Development Page v
Vancouver Design Center
Issue Date: 01/01/30 S1D13503
TABLE OF CONTENTS
INTRODUCTION
S1D13503 Graphics LCD Controller Data Sheet
SPECIFICATION
S1D13503 Hardware Functional Specification
PROGRAMMER’S REFERENCE
S1D13503 Programming Notes and Examples
UTILITIES
13503SHOW.EXE Display Utility
13503VIRT.EXE Display Utility
13503BIOS.COM Display Utility
13503MODE.EXE Display Utility
13503PD.EXE Power Down Utility
13503READ.EXE Diagnostic Utility
EVALUATION
S5U13503B00C Rev 1 Evaluation Board User Manual
APPLICATION NOTES
Power Consumption
ISA Bus Interface Considerations
MC68340 Interface Considerations
LCD Panel Options/Memory Requirements
S1D13503/S1D13502 Feature Comparison
Downloaded from Elcodis.com electronic components distributor

Page vi Epson Research and Development
Vancouver Design Center
S1D13503 Issue Date: 01/01/30
THIS PAGE LEFT BLANK
Downloaded from Elcodis.com electronic components distributor

GRAPHICS
S1D13503
X18A-C-002-03 1
January 2001
S1D13503 GRAPHICS LCD CONTROLLER
■DESCRIPTION
The S1D13503 is a dot matrix graphic LCD controller supporting resolutions up to 1024x1024. It is
capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades.
Design flexibility allows the S1D13503 to interface to either an MC68000 family microprocessor or an
8/16-bit MPU/bus with minimum external logic. The Static RAM (SRAM) interface used for the display
buffer is optimized for speed and performance, supporting up to 128K bytes.
Two power save modes, combined with operating voltages of 2.7 volts through 5.5 volts, allow for a wide
range of applications while providing minimum power consumption.
■FEATURES
CPU Interface
•Pin compatible with the S1D13502.
•16-bit 16 MHz MC68xxx MPU interface.
•8/16-bit MPU interface controlled by a READY
(or WAIT#) signal.
•Option to use built-in index register or direct-map-
ping to access one of sixteen internal registers.
Memory Interface
•8/16-bit SRAM interface configurations:
128K bytes using one 64Kx16 SRAMs.
128K bytes using two 64Kx8 SRAMs.
64K bytes using two 32Kx8 SRAMs.
40K bytes using one 8Kx8 and one 32Kx8
SRAM.
32K bytes using one 32Kx8 SRAM.
16K bytes using two 8Kx8 SRAMs.
8K bytes using one 8Kx8 SRAM.
Display Modes
•Black-and-white display.
•2/4 bits-per-pixel, 4/16-level gray-scale display.
•2/4/8 bits-per-pixel, 4/16/256-level color display.
Display Support
•Single-panel, single-drive passive display.
Dual-panel, dual-drive passive display.
•Maximum number of vertical lines:
1,024 lines (single-panel, single-drive display).
2,048 lines (dual-panel, dual-drive display).
•Split screen display support allowing two different
images to be simultaneously displayed.
•Virtual display support (displays images larger than
the panel size through the use of panning).
Clock Source
•2-terminal crystal or external oscillator.
Power Down Modes
•Low power consumption.
•Two software power-save modes.
Package
•QFP5-100-S2 package (F00A).
•QFP15-100-STD package (F01A).
Downloaded from Elcodis.com electronic components distributor

GRAPHICS
S1D13503
X18A-C-002-03
2
■SYSTEM BLOCK DIAGRAM
QFP5-100-S2
S1D13503
Flat Panel
Digital Out
CPU
SRAM
Control
Clock
CLOCK
(S1D13503F00A) QFP15-100-STD (S1D13503F01A)
CONTACT YOUR SALES REPRESENTATIVE FOR THESE
COMPREHENSIVE DESIGN TOOLS:
• S1D13503 Technical Manual
• S5U13503 Evaluation Boards
• CPU Independent Software Utilities
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: [phone]
Fax: [phone]
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: [phone]
Fax: [phone]
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: [phone]
Fax: [phone]
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: [phone]
Fax: [phone]
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: [phone]
Fax: [phone]
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: [phone]
Fax: [phone]
http://www.eea.epson.com
Copyright ©1997, 2001 Epson Research and Development, Inc. All rights reserved. VDC
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/
EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are
accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.
Downloaded from Elcodis.com electronic components distributor

S1D13503 Dot Matrix Graphics Color LCD Controller
Hardware Functional Specification
Document Number: X18A-A-001-08
Copyright © 1997, 2001Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Downloaded from Elcodis.com electronic components distributor

Page 2 Epson Research and Development
Vancouver Design Center
S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date: 01/01/29
THIS PAGE LEFT BLANK
Downloaded from Elcodis.com electronic components distributor

Epson Research and Development Page 3
Vancouver Design Center
Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 TYPICAL SYSTEM BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . 12
3.1 16-Bit MC68000 MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 MPU with READY (or WAIT#) signal . . . . . . . . . . . . . . . . . . . . . . 13
3.3 ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.1 Bus Signal Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.3 Sequence Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 LCD Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.5 Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.6 Port Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.7 Memory Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.8 Data Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.9 Address Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.10 MPU / CRT Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.11 Display Data Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.12 Clock Inputs / Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.13 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 PINOUT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . 26
6 D.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 A.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1 Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.1 MC68000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.2 Non-MC68000, MPU/Bus With READY (or WAIT#) Signal . . . . . . . . . . . . . . . 33
7.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.1 Recommended Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Downloaded from Elcodis.com electronic components distributor

Page 4 Epson Research and Development
Vancouver Design Center
S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date: 01/01/29
7.3 Display Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.1 Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.2 Read Data From Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4.1 LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels . . . . . . . 41
7.4.2 LCD Interface Timing - 4-Bit Single Color Panel . . . . . . . . . . . . . . . . . . . . . . 44
7.4.3 LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels . . . 46
7.4.4 LCD Interface Timing - 16-Bit Single/Dual Color Panels . . . . . . . . . . . . . . . . . . 48
7.4.5 LCD Interface Timing - 8-Bit Single Color Panels Format 1 . . . . . . . . . . . . . . . . 50
7.4.6 LCD Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8 HARDWARE REGISTER INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .61
8.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.2 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.2.1 Gray Shade Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.2.2 Color Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.3 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.3.1 Power Save Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.3.2 Power Save Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.3.3 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.3.4 Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9 DISPLAY MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.1 SRAM Configurations Supported . . . . . . . . . . . . . . . . . . . . . . . . 79
9.1.1 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.1.2 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.2 SRAM Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.2.1 8-bit Display Memory Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.2.2 16-bit Display Memory Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.3 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.3.1 For single panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.3.2 For dual panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.4 Memory Size Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.5 Memory Size Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10 MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Downloaded from Elcodis.com electronic components distributor

Epson Research and Development Page 5
Vancouver Design Center
Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08
List of Tables
Table 4-1: PAD Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 5-1: Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 5-2: Display Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 5-3: LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 5-4: Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 5-5: Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 5-6: Summary of Power On / Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 5-7: I/O and Memory Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 6-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 6-3: Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 6-4: Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 7-1: IOW# Timing (MC68000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 7-2: IOR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 7-3: MEMW# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 7-4: MEMR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 7-5: IOW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 7-6: IOR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 7-7: MEMW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 7-8: MEMR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 7-9: Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 7-10: Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7-11: Read Data From Display Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel . . . . . . . . . . .42
Table 7-13: LCD Interface Timing - 4-Bit Single Color Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 7-14: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels. . . . . . . . .47
Table 7-15: LCD Interface Timing - 16-Bit Single/Dual Color Panels . . . . . . . . . . . . . . . . . . . . . . .49
Table 7-16: LCD Interface Timing - 8-Bit Single Color Panels Format 1 . . . . . . . . . . . . . . . . . . . . . .51
Table 8-1: Gray Shade/Color Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 8-2: LCD Data Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 8-3: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface . . . . . . . . . . .64
Table 8-4: Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface . . . . . . . . . .64
Table 8-5: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 8-6: ID Bit Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 8-7: Look-Up Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 8-8: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 8-9: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Table 8-10: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 8-11: Pin States in Power Save Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 9-1: 8-Bit Display Memory Interface SRAM Access Time . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 9-2: 16-Bit Display Memory Interface SRAM Access Time. . . . . . . . . . . . . . . . . . . . . . . . .83
Table 9-3: Memory Size Requirement: Number of Horizontal Pixels = 640 . . . . . . . . . . . . . . . . . . . .85
Table 9-4: Memory Size Requirement: Number of Horizontal Pixels = 480 . . . . . . . . . . . . . . . . . . . .86
Table 9-5: Memory Size Requirement: Number of Horizontal Pixels = 320 . . . . . . . . . . . . . . . . . . . .86
Downloaded from Elcodis.com electronic components distributor

Page 6 Epson Research and Development
Vancouver Design Center
S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date: 01/01/29
THIS PAGE LEFT BLANK
Downloaded from Elcodis.com electronic components distributor

Epson Research and Development Page 7
Vancouver Design Center
Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08
List of Figures
Figure 1: 16-Bit 68000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 2: 8-Bit Mode, Example: Z80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 3: 16-Bit Mode, Example: i8086 (maximum mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 4: 8-Bit Mode (ISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 5: 16-Bit Mode (ISA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 6: Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 7: S1D13503 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 8: S1D13503 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 9: S1D13503 Pad Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 10: IOW# Timing (MC68000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 11: IOR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 12: MEMW# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 13: MEMR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 14: IOW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 15: IOR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 16: MEMW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 17: MEMR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 18: Clock Input Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 19: Recommended Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 20: Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 21: Read Data From Display Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 22: LCD Interface Timing - Monochrome Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 23: LCD Interface Timing - 4-Bit Single Color Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 24: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels. . . . . . . . .46
Figure 25: LCD Interface Timing - 16-Bit Single/Dual Color Panels . . . . . . . . . . . . . . . . . . . . . . .48
Figure 26: LCD Interface Timing - 8-Bit Single Color Panels Format 1 . . . . . . . . . . . . . . . . . . . . . .50
Figure 27: 4-Bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 28: 8-Bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 29: 8-Bit Dual Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 30: 4-Bit Single Color Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 31: 8-Bit Single Color Panel Timing - Format 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 32: 8-Bit Single Color Panel Timing - Format 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 33: 8-Bit Dual Color Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 34: External Circuit Required for 16-Bit Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 35: 16-Bit Single Color Panel Timing with External Circuit . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 36: 16-Bit Dual Color Panel Timing with External Circuit . . . . . . . . . . . . . . . . . . . . . . . . .60
Downloaded from Elcodis.com electronic components distributor

Page 8 Epson Research and Development
Vancouver Design Center
S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date: 01/01/29
Figure 37: 4-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture. . . . . . . . . . . . . . . . . . . . . . . 73
Figure 39: 4-Level Color Mode Look-Up Table Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 40: 16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 41: 256-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 42: 8-Bit Mode - 8K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 43: 8-Bit Mode - 16K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 44: 8-Bit Mode - 32K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 45: 8-Bit Mode - 40K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 46: 8-Bit Mode - 64K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 47: 16-Bit Mode - 16K bytes SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 48: 16-Bit Mode - 64K bytes SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 49: 16-Bit Mode - 128K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503). . . . . . . . . . . . . . . . . . . . . . . . . . 88
Downloaded from Elcodis.com electronic components distributor

Epson Research and Development Page 9
Vancouver Design Center
Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08
1 INTRODUCTION
1.1 Scope
This is the Functional Specification for the S1D13503 Dot Matrix Graphic Color LCD Controller. Included in this
document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This
document is intended for two audiences, Video Subsystem Designers and Software Developers.
1.2 Overview Description
This device is designed for products where low cost, low power consumption, and low component count are the major
design considerations. This chip operates from 2.7 Volts to 5.5 Volts and up to 25MHz to suit different power consumption,
speed and cost requirements. The S1D13503 offers a flexible microprocessor interface, and is pin compatible with the
S1D13502 within the same package types (e.g. the 13503D0A is pin compatible with the 13502; the 13503 is pin
compatible with the 13502).
The S1D13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous colors. In gray shade
modes, a 16x4 Look-Up Table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel.
In color modes, three 16x4 Look-Up Tables are provided to allow remapping of the 4096 possible colors displayed on the
LCD panel. The S1D13503S1D13503 can interface to an MC68000 family microprocessor or an 8/16-bit MPU/Bus with
minimum external “glue” logic. This device can directly control up to 128K bytes of static RAM with a 16-bit data path,
or up to 64K bytes with an 8-bit data path.
Downloaded from Elcodis.com electronic components distributor

Page 10 Epson Research and Development
Vancouver Design Center
S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date: 01/01/29
2 FEATURES
2.1 Technology
• low power CMOS
• 2.7 to 5.5 volt operation
• 100 pin QFP5-S2 surface mount package
• 100 pin QFP15-STD surface mount package
2.2 System
• maximum 25 MHz input clock (or pixel clock)
• 2-terminal crystal input for internal oscillator or direct connection to external clock source
• maximum 16 MHz, 16-bit MC68000 MPU interface
• 8-bit or 16-bit MPU/Bus interface with memory accesses controlled by a READY (or WAIT#) signal
• option to use built-in index register or direct-mapping to access one of sixteen internal registers
• 8-bit or 16-bit SRAM data bus interface configurations
• display memory configurations :
• 128k bytes using one 64Kx16 SRAM
• 128k bytes using two 64Kx8 SRAMs
• 64k bytes using two 32Kx8 SRAMs
• 40k bytes using one 8Kx8 and one 32Kx8 SRAM
• 32k bytes using one 32Kx8 SRAM
• 16k bytes using two 8Kx8 SRAMs
• 8k bytes using one 8Kx8 SRAM
2.3 Display Modes
• 1 bit-per-pixel, black-and-white display mode
• 2/4 bits-per-pixel, 4/16 level gray shade display modes
• 2/4/8 bits-per-pixel, 4/16/256 level color display modes
• one 16x4 Look-Up Table provided for gray shade display modes
• three 16x4 Look-Up Tables provided for color display modes
• maximum 16 shades of gray
• maximum 256 simultaneous colors from a possible 4096 colors
• split screen display mode (see AUX[0A])
• virtual display mode (see AUX[0D])
Note
256 color display mode support requires a 16-bit display memory interface
Downloaded from Elcodis.com electronic components distributor

Epson Research and Development Page 11
Vancouver Design Center
Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08
2.4 Display Support
• example resolutions:
• 1024 x 768 black-and-white
• 640 x 480 with 4 colors/grays
• 640 x 400 with 16 colors/grays
• 320 x 240 with 256 colors
• passive monochrome LCD panels:
• 4-bit single (4-bit data transfer)
• 8-bit single (8-bit data transfer)
• 8-bit dual (4-bit data transfer for each half panel)
• passive color LCD panels:
• 4-bit single (4-bit data transfer)
• 8-bit single (8-bit data transfer)
• 8-bit dual (4-bit data transfer for each half panel)
• 16-bit single (8-bit data transfer with external circuit)
• 16-bit dual (8-bit data transfer with external circuit)
See Section 9.5 on page 85 for complete details
2.5 Power Management
• two software power-save modes
• low power consumption
• panel power control switch (see AUX[01] bit 4)
Downloaded from Elcodis.com electronic components distributor

Page 12 Epson Research and Development
Vancouver Design Center
S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date: 01/01/29
3 TYPICAL SYSTEM BLOCK DIAGRAMS
The following figures show typical system implementations of the S1D13503. All of the following block diagrams are
shown without SRAM or LCD display. Refer to the interface specific Application Notes for complete details.
3.1 16-Bit MC68000 MPU
Figure 1: 16-Bit 68000 Series
(example implementation only - actual may vary)
S1D13503
MEMCS#
IOCS#
MC68000
DTACK#
D0 to D15
A1 to A19 AB1 to AB19
DB0 to DB15
IOW#
IOR#
Decoder
AS#
R/W#
BHE#
UDS#
READY
A20 to A23
AB0
LDS#
Decoder
A14 to A16
A10 to A19
FC0 to FC1
Downloaded from Elcodis.com electronic components distributor